1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86MCInstLower.h"
16 #include "X86AsmPrinter.h"
17 #include "X86COFFMachineModuleInfo.h"
18 #include "X86MCAsmInfo.h"
19 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Target/Mangler.h"
26 #include "llvm/Support/FormattedStream.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/Type.h"
31 X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf,
32 X86AsmPrinter &asmprinter)
33 : Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()),
34 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
36 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
37 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
41 MCSymbol *X86MCInstLower::GetPICBaseSymbol() const {
42 return static_cast<const X86TargetLowering*>(TM.getTargetLowering())->
43 getPICBaseSymbol(&MF, Ctx);
46 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
47 /// operand to an MCSymbol.
48 MCSymbol *X86MCInstLower::
49 GetSymbolFromOperand(const MachineOperand &MO) const {
50 assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference");
52 SmallString<128> Name;
55 assert(MO.isSymbol());
56 Name += MAI.getGlobalPrefix();
57 Name += MO.getSymbolName();
59 const GlobalValue *GV = MO.getGlobal();
60 bool isImplicitlyPrivate = false;
61 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
62 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
63 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
64 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
65 isImplicitlyPrivate = true;
67 Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
70 // If the target flags on the operand changes the name of the symbol, do that
71 // before we return the symbol.
72 switch (MO.getTargetFlags()) {
74 case X86II::MO_DLLIMPORT: {
75 // Handle dllimport linkage.
76 const char *Prefix = "__imp_";
77 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
80 case X86II::MO_DARWIN_NONLAZY:
81 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
82 Name += "$non_lazy_ptr";
83 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
85 MachineModuleInfoImpl::StubValueTy &StubSym =
86 getMachOMMI().getGVStubEntry(Sym);
87 if (StubSym.getPointer() == 0) {
88 assert(MO.isGlobal() && "Extern symbol not handled yet");
90 MachineModuleInfoImpl::
91 StubValueTy(Mang->getSymbol(MO.getGlobal()),
92 !MO.getGlobal()->hasInternalLinkage());
96 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
97 Name += "$non_lazy_ptr";
98 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
99 MachineModuleInfoImpl::StubValueTy &StubSym =
100 getMachOMMI().getHiddenGVStubEntry(Sym);
101 if (StubSym.getPointer() == 0) {
102 assert(MO.isGlobal() && "Extern symbol not handled yet");
104 MachineModuleInfoImpl::
105 StubValueTy(Mang->getSymbol(MO.getGlobal()),
106 !MO.getGlobal()->hasInternalLinkage());
110 case X86II::MO_DARWIN_STUB: {
112 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
113 MachineModuleInfoImpl::StubValueTy &StubSym =
114 getMachOMMI().getFnStubEntry(Sym);
115 if (StubSym.getPointer())
120 MachineModuleInfoImpl::
121 StubValueTy(Mang->getSymbol(MO.getGlobal()),
122 !MO.getGlobal()->hasInternalLinkage());
124 Name.erase(Name.end()-5, Name.end());
126 MachineModuleInfoImpl::
127 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
133 return Ctx.GetOrCreateSymbol(Name.str());
136 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
137 MCSymbol *Sym) const {
138 // FIXME: We would like an efficient form for this, so we don't have to do a
139 // lot of extra uniquing.
140 const MCExpr *Expr = 0;
141 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
143 switch (MO.getTargetFlags()) {
144 default: llvm_unreachable("Unknown target flag on GV operand");
145 case X86II::MO_NO_FLAG: // No flag.
146 // These affect the name of the symbol, not any suffix.
147 case X86II::MO_DARWIN_NONLAZY:
148 case X86II::MO_DLLIMPORT:
149 case X86II::MO_DARWIN_STUB:
152 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
153 case X86II::MO_TLVP_PIC_BASE:
154 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
155 // Subtract the pic base.
156 Expr = MCBinaryExpr::CreateSub(Expr,
157 MCSymbolRefExpr::Create(GetPICBaseSymbol(),
161 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
162 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
163 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
164 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
165 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
166 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
167 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
168 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
169 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
170 case X86II::MO_PIC_BASE_OFFSET:
171 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
172 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
173 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
174 // Subtract the pic base.
175 Expr = MCBinaryExpr::CreateSub(Expr,
176 MCSymbolRefExpr::Create(GetPICBaseSymbol(), Ctx),
178 if (MO.isJTI() && MAI.hasSetDirective()) {
179 // If .set directive is supported, use it to reduce the number of
180 // relocations the assembler will generate for differences between
181 // local labels. This is only safe when the symbols are in the same
182 // section so we are restricting it to jumptable references.
183 MCSymbol *Label = Ctx.CreateTempSymbol();
184 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
185 Expr = MCSymbolRefExpr::Create(Label, Ctx);
191 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
193 if (!MO.isJTI() && MO.getOffset())
194 Expr = MCBinaryExpr::CreateAdd(Expr,
195 MCConstantExpr::Create(MO.getOffset(), Ctx),
197 return MCOperand::CreateExpr(Expr);
202 static void lower_subreg32(MCInst *MI, unsigned OpNo) {
203 // Convert registers in the addr mode according to subreg32.
204 unsigned Reg = MI->getOperand(OpNo).getReg();
206 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
209 static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
210 // Convert registers in the addr mode according to subreg64.
211 for (unsigned i = 0; i != 4; ++i) {
212 if (!MI->getOperand(OpNo+i).isReg()) continue;
214 unsigned Reg = MI->getOperand(OpNo+i).getReg();
215 if (Reg == 0) continue;
217 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
221 /// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
222 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
223 OutMI.setOpcode(NewOpc);
224 lower_subreg32(&OutMI, 0);
226 /// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
227 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
228 OutMI.setOpcode(NewOpc);
229 OutMI.addOperand(OutMI.getOperand(0));
230 OutMI.addOperand(OutMI.getOperand(0));
233 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
234 /// a short fixed-register form.
235 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
236 unsigned ImmOp = Inst.getNumOperands() - 1;
237 assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() &&
238 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
239 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
240 Inst.getNumOperands() == 2) && "Unexpected instruction!");
242 // Check whether the destination register can be fixed.
243 unsigned Reg = Inst.getOperand(0).getReg();
244 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
247 // If so, rewrite the instruction.
248 MCOperand Saved = Inst.getOperand(ImmOp);
250 Inst.setOpcode(Opcode);
251 Inst.addOperand(Saved);
254 /// \brief Simplify things like MOV32rm to MOV32o32a.
255 static void SimplifyShortMoveForm(MCInst &Inst, unsigned Opcode) {
256 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
257 unsigned AddrBase = IsStore;
258 unsigned RegOp = IsStore ? 0 : 5;
259 unsigned AddrOp = AddrBase + 3;
260 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
261 Inst.getOperand(AddrBase + 0).isReg() && // base
262 Inst.getOperand(AddrBase + 1).isImm() && // scale
263 Inst.getOperand(AddrBase + 2).isReg() && // index register
264 (Inst.getOperand(AddrOp).isExpr() || // address
265 Inst.getOperand(AddrOp).isImm())&&
266 Inst.getOperand(AddrBase + 4).isReg() && // segment
267 "Unexpected instruction!");
269 // Check whether the destination register can be fixed.
270 unsigned Reg = Inst.getOperand(RegOp).getReg();
271 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
274 // Check whether this is an absolute address.
275 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
277 bool Absolute = true;
278 if (Inst.getOperand(AddrOp).isExpr()) {
279 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
280 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
281 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
286 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
287 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
288 Inst.getOperand(AddrBase + 4).getReg() != 0 ||
289 Inst.getOperand(AddrBase + 1).getImm() != 1))
292 // If so, rewrite the instruction.
293 MCOperand Saved = Inst.getOperand(AddrOp);
295 Inst.setOpcode(Opcode);
296 Inst.addOperand(Saved);
299 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
300 OutMI.setOpcode(MI->getOpcode());
302 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
303 const MachineOperand &MO = MI->getOperand(i);
306 switch (MO.getType()) {
309 llvm_unreachable("unknown operand type");
310 case MachineOperand::MO_Register:
311 // Ignore all implicit register operands.
312 if (MO.isImplicit()) continue;
313 MCOp = MCOperand::CreateReg(MO.getReg());
315 case MachineOperand::MO_Immediate:
316 MCOp = MCOperand::CreateImm(MO.getImm());
318 case MachineOperand::MO_MachineBasicBlock:
319 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
320 MO.getMBB()->getSymbol(), Ctx));
322 case MachineOperand::MO_GlobalAddress:
323 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
325 case MachineOperand::MO_ExternalSymbol:
326 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
328 case MachineOperand::MO_JumpTableIndex:
329 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
331 case MachineOperand::MO_ConstantPoolIndex:
332 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
334 case MachineOperand::MO_BlockAddress:
335 MCOp = LowerSymbolOperand(MO,
336 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
340 OutMI.addOperand(MCOp);
343 // Handle a few special cases to eliminate operand modifiers.
344 switch (OutMI.getOpcode()) {
345 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
346 lower_lea64_32mem(&OutMI, 1);
351 // LEA should have a segment register, but it must be empty.
352 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
353 "Unexpected # of LEA operands");
354 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
355 "LEA has segment specified!");
357 case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
358 case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
359 case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break;
360 case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break;
361 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
362 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
363 case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
364 case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
365 case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
366 case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
367 case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
368 case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
369 case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
370 case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
371 case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
372 case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
373 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
374 case X86::MMX_V_SET0: LowerUnaryToTwoAddr(OutMI, X86::MMX_PXORrr); break;
375 case X86::MMX_V_SETALLONES:
376 LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break;
377 case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
378 case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
379 case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
380 case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
381 case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
382 case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
385 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
386 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
389 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
390 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
393 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have
394 // register inputs modeled as normal uses instead of implicit uses. As such,
395 // truncate off all but the first operand (the callee). FIXME: Change isel.
396 case X86::TAILJMPr64:
398 case X86::CALL64pcrel32: {
399 unsigned Opcode = OutMI.getOpcode();
400 MCOperand Saved = OutMI.getOperand(0);
402 OutMI.setOpcode(Opcode);
403 OutMI.addOperand(Saved);
407 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
410 case X86::TAILJMPd64: {
412 switch (OutMI.getOpcode()) {
413 default: assert(0 && "Invalid opcode");
414 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
416 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
419 MCOperand Saved = OutMI.getOperand(0);
421 OutMI.setOpcode(Opcode);
422 OutMI.addOperand(Saved);
426 // The assembler backend wants to see branches in their small form and relax
427 // them to their large form. The JIT can only handle the large form because
428 // it does not do relaxation. For now, translate the large form to the
430 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
431 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
432 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
433 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
434 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
435 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
436 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
437 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
438 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
439 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
440 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
441 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
442 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
443 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
444 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
445 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
446 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
448 // We don't currently select the correct instruction form for instructions
449 // which have a short %eax, etc. form. Handle this by custom lowering, for
452 // Note, we are currently not handling the following instructions:
453 // MOV64ao8, MOV64o8a
454 // XCHG16ar, XCHG32ar, XCHG64ar
455 case X86::MOV8mr_NOREX:
456 case X86::MOV8mr: SimplifyShortMoveForm(OutMI, X86::MOV8ao8); break;
457 case X86::MOV8rm_NOREX:
458 case X86::MOV8rm: SimplifyShortMoveForm(OutMI, X86::MOV8o8a); break;
459 case X86::MOV16mr: SimplifyShortMoveForm(OutMI, X86::MOV16ao16); break;
460 case X86::MOV16rm: SimplifyShortMoveForm(OutMI, X86::MOV16o16a); break;
461 case X86::MOV32mr: SimplifyShortMoveForm(OutMI, X86::MOV32ao32); break;
462 case X86::MOV32rm: SimplifyShortMoveForm(OutMI, X86::MOV32o32a); break;
463 case X86::MOV64mr: SimplifyShortMoveForm(OutMI, X86::MOV64ao64); break;
464 case X86::MOV64rm: SimplifyShortMoveForm(OutMI, X86::MOV64o64a); break;
466 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
467 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
468 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
469 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
470 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
471 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
472 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
473 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
474 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
475 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
476 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
477 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
478 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
479 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
480 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
481 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
482 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
483 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
484 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
485 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
486 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
487 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
488 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
489 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
490 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
491 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
492 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
493 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
494 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
495 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
496 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
497 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
498 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
499 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
500 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
501 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
506 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
507 X86MCInstLower MCInstLowering(Mang, *MF, *this);
508 switch (MI->getOpcode()) {
509 case TargetOpcode::DBG_VALUE:
510 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
512 raw_string_ostream OS(TmpStr);
513 PrintDebugValueComment(MI, OS);
514 OutStreamer.EmitRawText(StringRef(OS.str()));
520 case X86::TAILJMPd64:
521 // Lower these as normal, but add some comments.
522 OutStreamer.AddComment("TAILCALL");
525 case X86::MOVPC32r: {
527 // This is a pseudo op for a two instruction sequence with a label, which
534 MCSymbol *PICBase = MCInstLowering.GetPICBaseSymbol();
535 TmpInst.setOpcode(X86::CALLpcrel32);
536 // FIXME: We would like an efficient form for this, so we don't have to do a
537 // lot of extra uniquing.
538 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
540 OutStreamer.EmitInstruction(TmpInst);
543 OutStreamer.EmitLabel(PICBase);
546 TmpInst.setOpcode(X86::POP32r);
547 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
548 OutStreamer.EmitInstruction(TmpInst);
553 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
554 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
557 // Okay, we have something like:
558 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
560 // For this, we want to print something like:
561 // MYGLOBAL + (. - PICBASE)
562 // However, we can't generate a ".", so just emit a new label here and refer
564 MCSymbol *DotSym = OutContext.CreateTempSymbol();
565 OutStreamer.EmitLabel(DotSym);
567 // Now that we have emitted the label, lower the complex operand expression.
568 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
570 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
571 const MCExpr *PICBase =
572 MCSymbolRefExpr::Create(MCInstLowering.GetPICBaseSymbol(), OutContext);
573 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
575 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
576 DotExpr, OutContext);
579 TmpInst.setOpcode(X86::ADD32ri);
580 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
581 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
582 TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
583 OutStreamer.EmitInstruction(TmpInst);
589 MCInstLowering.Lower(MI, TmpInst);
590 OutStreamer.EmitInstruction(TmpInst);