1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
25 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Mangler.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCCodeEmitter.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCFixup.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/MC/MCInstBuilder.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/Support/TargetRegistry.h"
43 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
44 class X86MCInstLower {
46 const MachineFunction &MF;
47 const TargetMachine &TM;
49 X86AsmPrinter &AsmPrinter;
51 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
53 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
55 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
56 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
59 MachineModuleInfoMachO &getMachOMMI() const;
60 Mangler *getMang() const {
61 return AsmPrinter.Mang;
65 } // end anonymous namespace
67 // Emit a minimal sequence of nops spanning NumBytes bytes.
68 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
69 const MCSubtargetInfo &STI);
72 X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
73 : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
75 X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
78 X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
80 CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
81 *MF->getSubtarget().getInstrInfo(),
82 *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
85 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
86 const MCSubtargetInfo &STI) {
88 SmallString<256> Code;
89 SmallVector<MCFixup, 4> Fixups;
90 raw_svector_ostream VecOS(Code);
91 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
93 CurrentShadowSize += Code.size();
94 if (CurrentShadowSize >= RequiredShadowSize)
95 InShadow = false; // The shadow is big enough. Stop counting.
99 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
100 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
101 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
103 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
104 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
108 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
109 OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
110 SMShadowTracker.count(Inst, getSubtargetInfo());
112 } // end llvm namespace
114 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
115 X86AsmPrinter &asmprinter)
116 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
117 AsmPrinter(asmprinter) {}
119 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
120 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
124 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
125 /// operand to an MCSymbol.
126 MCSymbol *X86MCInstLower::
127 GetSymbolFromOperand(const MachineOperand &MO) const {
128 const DataLayout *DL = TM.getDataLayout();
129 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
131 SmallString<128> Name;
134 switch (MO.getTargetFlags()) {
135 case X86II::MO_DLLIMPORT:
136 // Handle dllimport linkage.
139 case X86II::MO_DARWIN_STUB:
142 case X86II::MO_DARWIN_NONLAZY:
143 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
144 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
145 Suffix = "$non_lazy_ptr";
150 Name += DL->getPrivateGlobalPrefix();
152 unsigned PrefixLen = Name.size();
155 const GlobalValue *GV = MO.getGlobal();
156 AsmPrinter.getNameWithPrefix(Name, GV);
157 } else if (MO.isSymbol()) {
158 if (MO.getTargetFlags() == X86II::MO_NOPREFIX)
159 Name += MO.getSymbolName();
161 getMang()->getNameWithPrefix(Name, MO.getSymbolName());
162 } else if (MO.isMBB()) {
163 Name += MO.getMBB()->getSymbol()->getName();
165 unsigned OrigLen = Name.size() - PrefixLen;
168 MCSymbol *Sym = Ctx.getOrCreateSymbol(Name);
170 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
172 // If the target flags on the operand changes the name of the symbol, do that
173 // before we return the symbol.
174 switch (MO.getTargetFlags()) {
176 case X86II::MO_DARWIN_NONLAZY:
177 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
178 MachineModuleInfoImpl::StubValueTy &StubSym =
179 getMachOMMI().getGVStubEntry(Sym);
180 if (!StubSym.getPointer()) {
181 assert(MO.isGlobal() && "Extern symbol not handled yet");
183 MachineModuleInfoImpl::
184 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
185 !MO.getGlobal()->hasInternalLinkage());
189 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
190 MachineModuleInfoImpl::StubValueTy &StubSym =
191 getMachOMMI().getHiddenGVStubEntry(Sym);
192 if (!StubSym.getPointer()) {
193 assert(MO.isGlobal() && "Extern symbol not handled yet");
195 MachineModuleInfoImpl::
196 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
197 !MO.getGlobal()->hasInternalLinkage());
201 case X86II::MO_DARWIN_STUB: {
202 MachineModuleInfoImpl::StubValueTy &StubSym =
203 getMachOMMI().getFnStubEntry(Sym);
204 if (StubSym.getPointer())
209 MachineModuleInfoImpl::
210 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
211 !MO.getGlobal()->hasInternalLinkage());
214 MachineModuleInfoImpl::
215 StubValueTy(Ctx.getOrCreateSymbol(OrigName), false);
224 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
225 MCSymbol *Sym) const {
226 // FIXME: We would like an efficient form for this, so we don't have to do a
227 // lot of extra uniquing.
228 const MCExpr *Expr = nullptr;
229 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
231 switch (MO.getTargetFlags()) {
232 default: llvm_unreachable("Unknown target flag on GV operand");
233 case X86II::MO_NO_FLAG: // No flag.
234 // These affect the name of the symbol, not any suffix.
235 case X86II::MO_DARWIN_NONLAZY:
236 case X86II::MO_DLLIMPORT:
237 case X86II::MO_DARWIN_STUB:
238 case X86II::MO_NOPREFIX:
241 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
242 case X86II::MO_TLVP_PIC_BASE:
243 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
244 // Subtract the pic base.
245 Expr = MCBinaryExpr::CreateSub(Expr,
246 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
250 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
251 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
252 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
253 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
254 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
255 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
256 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
257 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
258 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
259 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
260 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
261 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
262 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
263 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
264 case X86II::MO_PIC_BASE_OFFSET:
265 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
266 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
267 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
268 // Subtract the pic base.
269 Expr = MCBinaryExpr::CreateSub(Expr,
270 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
273 assert(MAI.doesSetDirectiveSuppressesReloc());
274 // If .set directive is supported, use it to reduce the number of
275 // relocations the assembler will generate for differences between
276 // local labels. This is only safe when the symbols are in the same
277 // section so we are restricting it to jumptable references.
278 MCSymbol *Label = Ctx.createTempSymbol();
279 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
280 Expr = MCSymbolRefExpr::Create(Label, Ctx);
286 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
288 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
289 Expr = MCBinaryExpr::CreateAdd(Expr,
290 MCConstantExpr::Create(MO.getOffset(), Ctx),
292 return MCOperand::createExpr(Expr);
296 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
297 /// a short fixed-register form.
298 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
299 unsigned ImmOp = Inst.getNumOperands() - 1;
300 assert(Inst.getOperand(0).isReg() &&
301 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
302 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
303 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
304 Inst.getNumOperands() == 2) && "Unexpected instruction!");
306 // Check whether the destination register can be fixed.
307 unsigned Reg = Inst.getOperand(0).getReg();
308 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
311 // If so, rewrite the instruction.
312 MCOperand Saved = Inst.getOperand(ImmOp);
314 Inst.setOpcode(Opcode);
315 Inst.addOperand(Saved);
318 /// \brief If a movsx instruction has a shorter encoding for the used register
319 /// simplify the instruction to use it instead.
320 static void SimplifyMOVSX(MCInst &Inst) {
321 unsigned NewOpcode = 0;
322 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
323 switch (Inst.getOpcode()) {
325 llvm_unreachable("Unexpected instruction!");
326 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
327 if (Op0 == X86::AX && Op1 == X86::AL)
328 NewOpcode = X86::CBW;
330 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
331 if (Op0 == X86::EAX && Op1 == X86::AX)
332 NewOpcode = X86::CWDE;
334 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
335 if (Op0 == X86::RAX && Op1 == X86::EAX)
336 NewOpcode = X86::CDQE;
340 if (NewOpcode != 0) {
342 Inst.setOpcode(NewOpcode);
346 /// \brief Simplify things like MOV32rm to MOV32o32a.
347 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
349 // Don't make these simplifications in 64-bit mode; other assemblers don't
350 // perform them because they make the code larger.
351 if (Printer.getSubtarget().is64Bit())
354 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
355 unsigned AddrBase = IsStore;
356 unsigned RegOp = IsStore ? 0 : 5;
357 unsigned AddrOp = AddrBase + 3;
358 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
359 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
360 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
361 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
362 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
363 (Inst.getOperand(AddrOp).isExpr() ||
364 Inst.getOperand(AddrOp).isImm()) &&
365 "Unexpected instruction!");
367 // Check whether the destination register can be fixed.
368 unsigned Reg = Inst.getOperand(RegOp).getReg();
369 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
372 // Check whether this is an absolute address.
373 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
375 bool Absolute = true;
376 if (Inst.getOperand(AddrOp).isExpr()) {
377 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
378 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
379 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
384 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
385 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
386 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
389 // If so, rewrite the instruction.
390 MCOperand Saved = Inst.getOperand(AddrOp);
391 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
393 Inst.setOpcode(Opcode);
394 Inst.addOperand(Saved);
395 Inst.addOperand(Seg);
398 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
399 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
402 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
403 OutMI.setOpcode(MI->getOpcode());
405 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
406 const MachineOperand &MO = MI->getOperand(i);
409 switch (MO.getType()) {
412 llvm_unreachable("unknown operand type");
413 case MachineOperand::MO_Register:
414 // Ignore all implicit register operands.
415 if (MO.isImplicit()) continue;
416 MCOp = MCOperand::createReg(MO.getReg());
418 case MachineOperand::MO_Immediate:
419 MCOp = MCOperand::createImm(MO.getImm());
421 case MachineOperand::MO_MachineBasicBlock:
422 case MachineOperand::MO_GlobalAddress:
423 case MachineOperand::MO_ExternalSymbol:
424 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
426 case MachineOperand::MO_JumpTableIndex:
427 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
429 case MachineOperand::MO_ConstantPoolIndex:
430 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
432 case MachineOperand::MO_BlockAddress:
433 MCOp = LowerSymbolOperand(MO,
434 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
436 case MachineOperand::MO_RegisterMask:
437 // Ignore call clobbers.
441 OutMI.addOperand(MCOp);
444 // Handle a few special cases to eliminate operand modifiers.
446 switch (OutMI.getOpcode()) {
451 // LEA should have a segment register, but it must be empty.
452 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
453 "Unexpected # of LEA operands");
454 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
455 "LEA has segment specified!");
459 OutMI.setOpcode(X86::MOV32ri);
462 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
463 // if one of the registers is extended, but other isn't.
465 case X86::VMOVAPDYrr:
467 case X86::VMOVAPSYrr:
469 case X86::VMOVDQAYrr:
471 case X86::VMOVDQUYrr:
473 case X86::VMOVUPDYrr:
475 case X86::VMOVUPSYrr: {
476 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
477 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
479 switch (OutMI.getOpcode()) {
480 default: llvm_unreachable("Invalid opcode");
481 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
482 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
483 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
484 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
485 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
486 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
487 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
488 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
489 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
490 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
491 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
492 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
494 OutMI.setOpcode(NewOpc);
499 case X86::VMOVSSrr: {
500 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
501 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
503 switch (OutMI.getOpcode()) {
504 default: llvm_unreachable("Invalid opcode");
505 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
506 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
508 OutMI.setOpcode(NewOpc);
513 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
514 // inputs modeled as normal uses instead of implicit uses. As such, truncate
515 // off all but the first operand (the callee). FIXME: Change isel.
516 case X86::TAILJMPr64:
517 case X86::TAILJMPr64_REX:
519 case X86::CALL64pcrel32: {
520 unsigned Opcode = OutMI.getOpcode();
521 MCOperand Saved = OutMI.getOperand(0);
523 OutMI.setOpcode(Opcode);
524 OutMI.addOperand(Saved);
529 case X86::EH_RETURN64: {
531 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
535 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
538 case X86::TAILJMPd64: {
540 switch (OutMI.getOpcode()) {
541 default: llvm_unreachable("Invalid opcode");
542 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
544 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
547 MCOperand Saved = OutMI.getOperand(0);
549 OutMI.setOpcode(Opcode);
550 OutMI.addOperand(Saved);
558 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
559 if (!AsmPrinter.getSubtarget().is64Bit()) {
561 switch (OutMI.getOpcode()) {
562 default: llvm_unreachable("Invalid opcode");
563 case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
564 case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
565 case X86::INC16r: Opcode = X86::INC16r_alt; break;
566 case X86::INC32r: Opcode = X86::INC32r_alt; break;
568 OutMI.setOpcode(Opcode);
572 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
573 // this with an ugly goto in case the resultant OR uses EAX and needs the
575 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
576 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
577 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
578 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
579 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
580 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
581 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
582 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
583 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
585 // Atomic load and store require a separate pseudo-inst because Acquire
586 // implies mayStore and Release implies mayLoad; fix these to regular MOV
588 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
589 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
590 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
591 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
592 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
593 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
594 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
595 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
596 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
597 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
598 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
599 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
600 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
601 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
602 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
603 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
604 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
605 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
606 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
607 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
608 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
609 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
610 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
611 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
612 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
613 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
614 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
615 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
616 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
617 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
618 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
619 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
621 // We don't currently select the correct instruction form for instructions
622 // which have a short %eax, etc. form. Handle this by custom lowering, for
625 // Note, we are currently not handling the following instructions:
626 // MOV64ao8, MOV64o8a
627 // XCHG16ar, XCHG32ar, XCHG64ar
628 case X86::MOV8mr_NOREX:
629 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
630 case X86::MOV8rm_NOREX:
631 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
632 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
633 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
634 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
635 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
637 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
638 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
639 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
640 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
641 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
642 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
643 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
644 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
645 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
646 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
647 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
648 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
649 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
650 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
651 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
652 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
653 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
654 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
655 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
656 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
657 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
658 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
659 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
660 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
661 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
662 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
663 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
664 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
665 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
666 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
667 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
668 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
669 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
670 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
671 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
672 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
674 // Try to shrink some forms of movsx.
675 case X86::MOVSX16rr8:
676 case X86::MOVSX32rr16:
677 case X86::MOVSX64rr32:
678 SimplifyMOVSX(OutMI);
683 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
684 const MachineInstr &MI) {
686 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
687 MI.getOpcode() == X86::TLS_base_addr64;
689 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
691 MCContext &context = OutStreamer->getContext();
694 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
696 MCSymbolRefExpr::VariantKind SRVK;
697 switch (MI.getOpcode()) {
698 case X86::TLS_addr32:
699 case X86::TLS_addr64:
700 SRVK = MCSymbolRefExpr::VK_TLSGD;
702 case X86::TLS_base_addr32:
703 SRVK = MCSymbolRefExpr::VK_TLSLDM;
705 case X86::TLS_base_addr64:
706 SRVK = MCSymbolRefExpr::VK_TLSLD;
709 llvm_unreachable("unexpected opcode");
712 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
713 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
717 LEA.setOpcode(X86::LEA64r);
718 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
719 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
720 LEA.addOperand(MCOperand::createImm(1)); // scale
721 LEA.addOperand(MCOperand::createReg(0)); // index
722 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
723 LEA.addOperand(MCOperand::createReg(0)); // seg
724 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
725 LEA.setOpcode(X86::LEA32r);
726 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
727 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
728 LEA.addOperand(MCOperand::createImm(1)); // scale
729 LEA.addOperand(MCOperand::createReg(0)); // index
730 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
731 LEA.addOperand(MCOperand::createReg(0)); // seg
733 LEA.setOpcode(X86::LEA32r);
734 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
735 LEA.addOperand(MCOperand::createReg(0)); // base
736 LEA.addOperand(MCOperand::createImm(1)); // scale
737 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
738 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
739 LEA.addOperand(MCOperand::createReg(0)); // seg
741 EmitAndCountInstruction(LEA);
744 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
745 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
746 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
749 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
750 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
751 const MCSymbolRefExpr *tlsRef =
752 MCSymbolRefExpr::Create(tlsGetAddr,
753 MCSymbolRefExpr::VK_PLT,
756 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
761 /// \brief Emit the optimal amount of multi-byte nops on X86.
762 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
763 // This works only for 64bit. For 32bit we have to do additional checking if
764 // the CPU supports multi-byte nops.
765 assert(Is64Bit && "EmitNops only supports X86-64");
767 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
768 Opc = IndexReg = Displacement = SegmentReg = 0;
769 BaseReg = X86::RAX; ScaleVal = 1;
771 case 0: llvm_unreachable("Zero nops?"); break;
772 case 1: NumBytes -= 1; Opc = X86::NOOP; break;
773 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
774 case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
775 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
776 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
777 IndexReg = X86::RAX; break;
778 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
779 IndexReg = X86::RAX; break;
780 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
781 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
782 IndexReg = X86::RAX; break;
783 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
784 IndexReg = X86::RAX; break;
785 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
786 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
789 unsigned NumPrefixes = std::min(NumBytes, 5U);
790 NumBytes -= NumPrefixes;
791 for (unsigned i = 0; i != NumPrefixes; ++i)
792 OS.EmitBytes("\x66");
795 default: llvm_unreachable("Unexpected opcode"); break;
797 OS.EmitInstruction(MCInstBuilder(Opc), STI);
800 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
804 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
805 .addImm(ScaleVal).addReg(IndexReg)
806 .addImm(Displacement).addReg(SegmentReg), STI);
809 } // while (NumBytes)
812 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
813 X86MCInstLower &MCIL) {
814 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
816 StatepointOpers SOpers(&MI);
817 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
818 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
821 // Lower call target and choose correct opcode
822 const MachineOperand &CallTarget = SOpers.getCallTarget();
823 MCOperand CallTargetMCOp;
825 switch (CallTarget.getType()) {
826 case MachineOperand::MO_GlobalAddress:
827 case MachineOperand::MO_ExternalSymbol:
828 CallTargetMCOp = MCIL.LowerSymbolOperand(
829 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
830 CallOpcode = X86::CALL64pcrel32;
831 // Currently, we only support relative addressing with statepoints.
832 // Otherwise, we'll need a scratch register to hold the target
833 // address. You'll fail asserts during load & relocation if this
834 // symbol is to far away. (TODO: support non-relative addressing)
836 case MachineOperand::MO_Immediate:
837 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
838 CallOpcode = X86::CALL64pcrel32;
839 // Currently, we only support relative addressing with statepoints.
840 // Otherwise, we'll need a scratch register to hold the target
841 // immediate. You'll fail asserts during load & relocation if this
842 // address is to far away. (TODO: support non-relative addressing)
844 case MachineOperand::MO_Register:
845 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
846 CallOpcode = X86::CALL64r;
849 llvm_unreachable("Unsupported operand type in statepoint call target");
855 CallInst.setOpcode(CallOpcode);
856 CallInst.addOperand(CallTargetMCOp);
857 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
860 // Record our statepoint node in the same section used by STACKMAP
862 SM.recordStatepoint(MI);
866 // Lower a stackmap of the form:
867 // <id>, <shadowBytes>, ...
868 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
869 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
870 SM.recordStackMap(MI);
871 unsigned NumShadowBytes = MI.getOperand(1).getImm();
872 SMShadowTracker.reset(NumShadowBytes);
875 // Lower a patchpoint of the form:
876 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
877 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
878 X86MCInstLower &MCIL) {
879 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
881 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
883 SM.recordPatchPoint(MI);
885 PatchPointOpers opers(&MI);
886 unsigned ScratchIdx = opers.getNextScratchIdx();
887 unsigned EncodedBytes = 0;
888 const MachineOperand &CalleeMO =
889 opers.getMetaOper(PatchPointOpers::TargetPos);
891 // Check for null target. If target is non-null (i.e. is non-zero or is
892 // symbolic) then emit a call.
893 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
894 MCOperand CalleeMCOp;
895 switch (CalleeMO.getType()) {
897 /// FIXME: Add a verifier check for bad callee types.
898 llvm_unreachable("Unrecognized callee operand type.");
899 case MachineOperand::MO_Immediate:
900 if (CalleeMO.getImm())
901 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
903 case MachineOperand::MO_ExternalSymbol:
904 case MachineOperand::MO_GlobalAddress:
906 MCIL.LowerSymbolOperand(CalleeMO,
907 MCIL.GetSymbolFromOperand(CalleeMO));
911 // Emit MOV to materialize the target address and the CALL to target.
912 // This is encoded with 12-13 bytes, depending on which register is used.
913 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
914 if (X86II::isX86_64ExtendedReg(ScratchReg))
919 EmitAndCountInstruction(
920 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
921 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
925 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
926 assert(NumBytes >= EncodedBytes &&
927 "Patchpoint can't request size less than the length of a call.");
929 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
933 // Returns instruction preceding MBBI in MachineFunction.
934 // If MBBI is the first instruction of the first basic block, returns null.
935 static MachineBasicBlock::const_iterator
936 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
937 const MachineBasicBlock *MBB = MBBI->getParent();
938 while (MBBI == MBB->begin()) {
939 if (MBB == MBB->getParent()->begin())
941 MBB = MBB->getPrevNode();
947 static const Constant *getConstantFromPool(const MachineInstr &MI,
948 const MachineOperand &Op) {
952 ArrayRef<MachineConstantPoolEntry> Constants =
953 MI.getParent()->getParent()->getConstantPool()->getConstants();
954 const MachineConstantPoolEntry &ConstantEntry =
955 Constants[Op.getIndex()];
957 // Bail if this is a machine constant pool entry, we won't be able to dig out
959 if (ConstantEntry.isMachineConstantPoolEntry())
962 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
963 assert((!C || ConstantEntry.getType() == C->getType()) &&
964 "Expected a constant of the same type!");
968 static std::string getShuffleComment(const MachineOperand &DstOp,
969 const MachineOperand &SrcOp,
970 ArrayRef<int> Mask) {
973 // Compute the name for a register. This is really goofy because we have
974 // multiple instruction printers that could (in theory) use different
975 // names. Fortunately most people use the ATT style (outside of Windows)
976 // and they actually agree on register naming here. Ultimately, this is
977 // a comment, and so its OK if it isn't perfect.
978 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
979 return X86ATTInstPrinter::getRegisterName(RegNum);
982 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
983 StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
985 raw_string_ostream CS(Comment);
986 CS << DstName << " = ";
987 bool NeedComma = false;
990 // Wrap up any prior entry...
991 if (M == SM_SentinelZero && InSrc) {
1000 // Print this shuffle...
1001 if (M == SM_SentinelZero) {
1006 CS << SrcName << "[";
1008 if (M == SM_SentinelUndef)
1021 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1022 X86MCInstLower MCInstLowering(*MF, *this);
1023 const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1025 switch (MI->getOpcode()) {
1026 case TargetOpcode::DBG_VALUE:
1027 llvm_unreachable("Should be handled target independently");
1029 // Emit nothing here but a comment if we can.
1030 case X86::Int_MemBarrier:
1031 OutStreamer->emitRawComment("MEMBARRIER");
1035 case X86::EH_RETURN:
1036 case X86::EH_RETURN64: {
1037 // Lower these as normal, but add some comments.
1038 unsigned Reg = MI->getOperand(0).getReg();
1039 OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1040 X86ATTInstPrinter::getRegisterName(Reg));
1046 case X86::TAILJMPr64:
1047 case X86::TAILJMPm64:
1048 case X86::TAILJMPd64:
1049 case X86::TAILJMPr64_REX:
1050 case X86::TAILJMPm64_REX:
1051 case X86::TAILJMPd64_REX:
1052 // Lower these as normal, but add some comments.
1053 OutStreamer->AddComment("TAILCALL");
1056 case X86::TLS_addr32:
1057 case X86::TLS_addr64:
1058 case X86::TLS_base_addr32:
1059 case X86::TLS_base_addr64:
1060 return LowerTlsAddr(MCInstLowering, *MI);
1062 case X86::MOVPC32r: {
1063 // This is a pseudo op for a two instruction sequence with a label, which
1070 MCSymbol *PICBase = MF->getPICBaseSymbol();
1071 // FIXME: We would like an efficient form for this, so we don't have to do a
1072 // lot of extra uniquing.
1073 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1074 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
1077 OutStreamer->EmitLabel(PICBase);
1080 EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1081 .addReg(MI->getOperand(0).getReg()));
1085 case X86::ADD32ri: {
1086 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1087 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1090 // Okay, we have something like:
1091 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1093 // For this, we want to print something like:
1094 // MYGLOBAL + (. - PICBASE)
1095 // However, we can't generate a ".", so just emit a new label here and refer
1097 MCSymbol *DotSym = OutContext.createTempSymbol();
1098 OutStreamer->EmitLabel(DotSym);
1100 // Now that we have emitted the label, lower the complex operand expression.
1101 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1103 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
1104 const MCExpr *PICBase =
1105 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
1106 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
1108 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
1109 DotExpr, OutContext);
1111 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1112 .addReg(MI->getOperand(0).getReg())
1113 .addReg(MI->getOperand(1).getReg())
1117 case TargetOpcode::STATEPOINT:
1118 return LowerSTATEPOINT(*MI, MCInstLowering);
1120 case TargetOpcode::STACKMAP:
1121 return LowerSTACKMAP(*MI);
1123 case TargetOpcode::PATCHPOINT:
1124 return LowerPATCHPOINT(*MI, MCInstLowering);
1126 case X86::MORESTACK_RET:
1127 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1130 case X86::MORESTACK_RET_RESTORE_R10:
1131 // Return, then restore R10.
1132 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1133 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1138 case X86::SEH_PushReg:
1139 OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1142 case X86::SEH_SaveReg:
1143 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1144 MI->getOperand(1).getImm());
1147 case X86::SEH_SaveXMM:
1148 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1149 MI->getOperand(1).getImm());
1152 case X86::SEH_StackAlloc:
1153 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1156 case X86::SEH_SetFrame:
1157 OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1158 MI->getOperand(1).getImm());
1161 case X86::SEH_PushFrame:
1162 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1165 case X86::SEH_EndPrologue:
1166 OutStreamer->EmitWinCFIEndProlog();
1169 case X86::SEH_Epilogue: {
1170 MachineBasicBlock::const_iterator MBBI(MI);
1171 // Check if preceded by a call and emit nop if so.
1172 for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1173 // Conservatively assume that pseudo instructions don't emit code and keep
1174 // looking for a call. We may emit an unnecessary nop in some cases.
1175 if (!MBBI->isPseudo()) {
1177 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1184 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1185 // a constant shuffle mask. We won't be able to do this at the MC layer
1186 // because the mask isn't an immediate.
1188 case X86::VPSHUFBrm:
1189 case X86::VPSHUFBYrm: {
1190 if (!OutStreamer->isVerboseAsm())
1192 assert(MI->getNumOperands() > 5 &&
1193 "We should always have at least 5 operands!");
1194 const MachineOperand &DstOp = MI->getOperand(0);
1195 const MachineOperand &SrcOp = MI->getOperand(1);
1196 const MachineOperand &MaskOp = MI->getOperand(5);
1198 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1199 SmallVector<int, 16> Mask;
1200 DecodePSHUFBMask(C, Mask);
1202 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1206 case X86::VPERMILPSrm:
1207 case X86::VPERMILPDrm:
1208 case X86::VPERMILPSYrm:
1209 case X86::VPERMILPDYrm: {
1210 if (!OutStreamer->isVerboseAsm())
1212 assert(MI->getNumOperands() > 5 &&
1213 "We should always have at least 5 operands!");
1214 const MachineOperand &DstOp = MI->getOperand(0);
1215 const MachineOperand &SrcOp = MI->getOperand(1);
1216 const MachineOperand &MaskOp = MI->getOperand(5);
1218 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1219 SmallVector<int, 16> Mask;
1220 DecodeVPERMILPMask(C, Mask);
1222 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1227 // For loads from a constant pool to a vector register, print the constant
1230 case X86::VMOVAPDrm:
1231 case X86::VMOVAPDYrm:
1233 case X86::VMOVUPDrm:
1234 case X86::VMOVUPDYrm:
1236 case X86::VMOVAPSrm:
1237 case X86::VMOVAPSYrm:
1239 case X86::VMOVUPSrm:
1240 case X86::VMOVUPSYrm:
1242 case X86::VMOVDQArm:
1243 case X86::VMOVDQAYrm:
1245 case X86::VMOVDQUrm:
1246 case X86::VMOVDQUYrm:
1247 if (!OutStreamer->isVerboseAsm())
1249 if (MI->getNumOperands() > 4)
1250 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1251 std::string Comment;
1252 raw_string_ostream CS(Comment);
1253 const MachineOperand &DstOp = MI->getOperand(0);
1254 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1255 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1257 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1260 if (CDS->getElementType()->isIntegerTy())
1261 CS << CDS->getElementAsInteger(i);
1262 else if (CDS->getElementType()->isFloatTy())
1263 CS << CDS->getElementAsFloat(i);
1264 else if (CDS->getElementType()->isDoubleTy())
1265 CS << CDS->getElementAsDouble(i);
1270 OutStreamer->AddComment(CS.str());
1271 } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1273 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1276 Constant *COp = CV->getOperand(i);
1277 if (isa<UndefValue>(COp)) {
1279 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1280 CS << CI->getZExtValue();
1281 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1282 SmallString<32> Str;
1283 CF->getValueAPF().toString(Str);
1290 OutStreamer->AddComment(CS.str());
1297 MCInstLowering.Lower(MI, TmpInst);
1299 // Stackmap shadows cannot include branch targets, so we can count the bytes
1300 // in a call towards the shadow, but must ensure that the no thread returns
1301 // in to the stackmap shadow. The only way to achieve this is if the call
1302 // is at the end of the shadow.
1304 // Count then size of the call towards the shadow
1305 SMShadowTracker.count(TmpInst, getSubtargetInfo());
1306 // Then flush the shadow so that we fill with nops before the call, not
1308 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1309 // Then emit the call
1310 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1314 EmitAndCountInstruction(TmpInst);