1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "InstPrinter/X86ATTInstPrinter.h"
17 #include "X86COFFMachineModuleInfo.h"
18 #include "llvm/ADT/SmallString.h"
19 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
20 #include "llvm/CodeGen/StackMaps.h"
21 #include "llvm/IR/Type.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstBuilder.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSymbol.h"
29 #include "llvm/Support/FormattedStream.h"
30 #include "llvm/Target/Mangler.h"
35 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
36 class X86MCInstLower {
38 const MachineFunction &MF;
39 const TargetMachine &TM;
41 X86AsmPrinter &AsmPrinter;
43 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
45 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
47 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
48 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
51 MachineModuleInfoMachO &getMachOMMI() const;
52 Mangler *getMang() const {
53 return AsmPrinter.Mang;
57 } // end anonymous namespace
59 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
60 X86AsmPrinter &asmprinter)
61 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
62 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
64 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
65 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
69 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
70 /// operand to an MCSymbol.
71 MCSymbol *X86MCInstLower::
72 GetSymbolFromOperand(const MachineOperand &MO) const {
73 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
75 SmallString<128> Name;
78 const GlobalValue *GV = MO.getGlobal();
79 bool isImplicitlyPrivate = false;
80 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
81 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
82 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
83 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
84 isImplicitlyPrivate = true;
86 getMang()->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
87 } else if (MO.isSymbol()) {
88 getMang()->getNameWithPrefix(Name, MO.getSymbolName());
89 } else if (MO.isMBB()) {
90 Name += MO.getMBB()->getSymbol()->getName();
93 // If the target flags on the operand changes the name of the symbol, do that
94 // before we return the symbol.
95 switch (MO.getTargetFlags()) {
97 case X86II::MO_DLLIMPORT: {
98 // Handle dllimport linkage.
99 const char *Prefix = "__imp_";
100 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
103 case X86II::MO_DARWIN_NONLAZY:
104 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
105 Name += "$non_lazy_ptr";
106 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
108 MachineModuleInfoImpl::StubValueTy &StubSym =
109 getMachOMMI().getGVStubEntry(Sym);
110 if (StubSym.getPointer() == 0) {
111 assert(MO.isGlobal() && "Extern symbol not handled yet");
113 MachineModuleInfoImpl::
114 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
115 !MO.getGlobal()->hasInternalLinkage());
119 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
120 Name += "$non_lazy_ptr";
121 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
122 MachineModuleInfoImpl::StubValueTy &StubSym =
123 getMachOMMI().getHiddenGVStubEntry(Sym);
124 if (StubSym.getPointer() == 0) {
125 assert(MO.isGlobal() && "Extern symbol not handled yet");
127 MachineModuleInfoImpl::
128 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
129 !MO.getGlobal()->hasInternalLinkage());
133 case X86II::MO_DARWIN_STUB: {
135 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
136 MachineModuleInfoImpl::StubValueTy &StubSym =
137 getMachOMMI().getFnStubEntry(Sym);
138 if (StubSym.getPointer())
143 MachineModuleInfoImpl::
144 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
145 !MO.getGlobal()->hasInternalLinkage());
147 Name.erase(Name.end()-5, Name.end());
149 MachineModuleInfoImpl::
150 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
156 return Ctx.GetOrCreateSymbol(Name.str());
159 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
160 MCSymbol *Sym) const {
161 // FIXME: We would like an efficient form for this, so we don't have to do a
162 // lot of extra uniquing.
163 const MCExpr *Expr = 0;
164 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
166 switch (MO.getTargetFlags()) {
167 default: llvm_unreachable("Unknown target flag on GV operand");
168 case X86II::MO_NO_FLAG: // No flag.
169 // These affect the name of the symbol, not any suffix.
170 case X86II::MO_DARWIN_NONLAZY:
171 case X86II::MO_DLLIMPORT:
172 case X86II::MO_DARWIN_STUB:
175 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
176 case X86II::MO_TLVP_PIC_BASE:
177 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
178 // Subtract the pic base.
179 Expr = MCBinaryExpr::CreateSub(Expr,
180 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
184 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
185 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
186 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
187 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
188 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
189 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
190 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
191 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
192 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
193 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
194 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
195 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
196 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
197 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
198 case X86II::MO_PIC_BASE_OFFSET:
199 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
200 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
201 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
202 // Subtract the pic base.
203 Expr = MCBinaryExpr::CreateSub(Expr,
204 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
206 if (MO.isJTI() && MAI.hasSetDirective()) {
207 // If .set directive is supported, use it to reduce the number of
208 // relocations the assembler will generate for differences between
209 // local labels. This is only safe when the symbols are in the same
210 // section so we are restricting it to jumptable references.
211 MCSymbol *Label = Ctx.CreateTempSymbol();
212 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
213 Expr = MCSymbolRefExpr::Create(Label, Ctx);
219 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
221 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
222 Expr = MCBinaryExpr::CreateAdd(Expr,
223 MCConstantExpr::Create(MO.getOffset(), Ctx),
225 return MCOperand::CreateExpr(Expr);
229 /// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
230 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
231 OutMI.setOpcode(NewOpc);
232 OutMI.addOperand(OutMI.getOperand(0));
233 OutMI.addOperand(OutMI.getOperand(0));
236 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
237 /// a short fixed-register form.
238 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
239 unsigned ImmOp = Inst.getNumOperands() - 1;
240 assert(Inst.getOperand(0).isReg() &&
241 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
242 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
243 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
244 Inst.getNumOperands() == 2) && "Unexpected instruction!");
246 // Check whether the destination register can be fixed.
247 unsigned Reg = Inst.getOperand(0).getReg();
248 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
251 // If so, rewrite the instruction.
252 MCOperand Saved = Inst.getOperand(ImmOp);
254 Inst.setOpcode(Opcode);
255 Inst.addOperand(Saved);
258 /// \brief If a movsx instruction has a shorter encoding for the used register
259 /// simplify the instruction to use it instead.
260 static void SimplifyMOVSX(MCInst &Inst) {
261 unsigned NewOpcode = 0;
262 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
263 switch (Inst.getOpcode()) {
265 llvm_unreachable("Unexpected instruction!");
266 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
267 if (Op0 == X86::AX && Op1 == X86::AL)
268 NewOpcode = X86::CBW;
270 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
271 if (Op0 == X86::EAX && Op1 == X86::AX)
272 NewOpcode = X86::CWDE;
274 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
275 if (Op0 == X86::RAX && Op1 == X86::EAX)
276 NewOpcode = X86::CDQE;
280 if (NewOpcode != 0) {
282 Inst.setOpcode(NewOpcode);
286 /// \brief Simplify things like MOV32rm to MOV32o32a.
287 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
289 // Don't make these simplifications in 64-bit mode; other assemblers don't
290 // perform them because they make the code larger.
291 if (Printer.getSubtarget().is64Bit())
294 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
295 unsigned AddrBase = IsStore;
296 unsigned RegOp = IsStore ? 0 : 5;
297 unsigned AddrOp = AddrBase + 3;
298 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
299 Inst.getOperand(AddrBase + 0).isReg() && // base
300 Inst.getOperand(AddrBase + 1).isImm() && // scale
301 Inst.getOperand(AddrBase + 2).isReg() && // index register
302 (Inst.getOperand(AddrOp).isExpr() || // address
303 Inst.getOperand(AddrOp).isImm())&&
304 Inst.getOperand(AddrBase + 4).isReg() && // segment
305 "Unexpected instruction!");
307 // Check whether the destination register can be fixed.
308 unsigned Reg = Inst.getOperand(RegOp).getReg();
309 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
312 // Check whether this is an absolute address.
313 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
315 bool Absolute = true;
316 if (Inst.getOperand(AddrOp).isExpr()) {
317 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
318 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
319 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
324 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
325 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
326 Inst.getOperand(AddrBase + 4).getReg() != 0 ||
327 Inst.getOperand(AddrBase + 1).getImm() != 1))
330 // If so, rewrite the instruction.
331 MCOperand Saved = Inst.getOperand(AddrOp);
333 Inst.setOpcode(Opcode);
334 Inst.addOperand(Saved);
337 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
338 OutMI.setOpcode(MI->getOpcode());
340 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
341 const MachineOperand &MO = MI->getOperand(i);
344 switch (MO.getType()) {
347 llvm_unreachable("unknown operand type");
348 case MachineOperand::MO_Register:
349 // Ignore all implicit register operands.
350 if (MO.isImplicit()) continue;
351 MCOp = MCOperand::CreateReg(MO.getReg());
353 case MachineOperand::MO_Immediate:
354 MCOp = MCOperand::CreateImm(MO.getImm());
356 case MachineOperand::MO_MachineBasicBlock:
357 case MachineOperand::MO_GlobalAddress:
358 case MachineOperand::MO_ExternalSymbol:
359 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
361 case MachineOperand::MO_JumpTableIndex:
362 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
364 case MachineOperand::MO_ConstantPoolIndex:
365 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
367 case MachineOperand::MO_BlockAddress:
368 MCOp = LowerSymbolOperand(MO,
369 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
371 case MachineOperand::MO_RegisterMask:
372 // Ignore call clobbers.
376 OutMI.addOperand(MCOp);
379 // Handle a few special cases to eliminate operand modifiers.
381 switch (OutMI.getOpcode()) {
386 // LEA should have a segment register, but it must be empty.
387 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
388 "Unexpected # of LEA operands");
389 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
390 "LEA has segment specified!");
392 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
395 OutMI.setOpcode(X86::MOV32ri);
398 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
399 // if one of the registers is extended, but other isn't.
401 case X86::VMOVAPDYrr:
403 case X86::VMOVAPSYrr:
405 case X86::VMOVDQAYrr:
407 case X86::VMOVDQUYrr:
409 case X86::VMOVUPDYrr:
411 case X86::VMOVUPSYrr: {
412 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
413 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
415 switch (OutMI.getOpcode()) {
416 default: llvm_unreachable("Invalid opcode");
417 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
418 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
419 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
420 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
421 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
422 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
423 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
424 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
425 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
426 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
427 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
428 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
430 OutMI.setOpcode(NewOpc);
435 case X86::VMOVSSrr: {
436 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
437 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
439 switch (OutMI.getOpcode()) {
440 default: llvm_unreachable("Invalid opcode");
441 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
442 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
444 OutMI.setOpcode(NewOpc);
449 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
450 // inputs modeled as normal uses instead of implicit uses. As such, truncate
451 // off all but the first operand (the callee). FIXME: Change isel.
452 case X86::TAILJMPr64:
454 case X86::CALL64pcrel32: {
455 unsigned Opcode = OutMI.getOpcode();
456 MCOperand Saved = OutMI.getOperand(0);
458 OutMI.setOpcode(Opcode);
459 OutMI.addOperand(Saved);
464 case X86::EH_RETURN64: {
466 OutMI.setOpcode(X86::RET);
470 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
473 case X86::TAILJMPd64: {
475 switch (OutMI.getOpcode()) {
476 default: llvm_unreachable("Invalid opcode");
477 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
479 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
482 MCOperand Saved = OutMI.getOperand(0);
484 OutMI.setOpcode(Opcode);
485 OutMI.addOperand(Saved);
489 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
490 // this with an ugly goto in case the resultant OR uses EAX and needs the
492 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
493 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
494 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
495 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
496 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
497 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
498 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
499 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
500 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
502 // The assembler backend wants to see branches in their small form and relax
503 // them to their large form. The JIT can only handle the large form because
504 // it does not do relaxation. For now, translate the large form to the
506 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
507 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
508 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
509 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
510 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
511 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
512 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
513 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
514 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
515 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
516 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
517 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
518 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
519 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
520 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
521 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
522 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
524 // Atomic load and store require a separate pseudo-inst because Acquire
525 // implies mayStore and Release implies mayLoad; fix these to regular MOV
527 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
528 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
529 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
530 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
531 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
532 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
533 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
534 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
536 // We don't currently select the correct instruction form for instructions
537 // which have a short %eax, etc. form. Handle this by custom lowering, for
540 // Note, we are currently not handling the following instructions:
541 // MOV64ao8, MOV64o8a
542 // XCHG16ar, XCHG32ar, XCHG64ar
543 case X86::MOV8mr_NOREX:
544 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
545 case X86::MOV8rm_NOREX:
546 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
547 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
548 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
549 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
550 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
552 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
553 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
554 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
555 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
556 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
557 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
558 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
559 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
560 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
561 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
562 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
563 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
564 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
565 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
566 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
567 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
568 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
569 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
570 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
571 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
572 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
573 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
574 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
575 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
576 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
577 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
578 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
579 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
580 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
581 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
582 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
583 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
584 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
585 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
586 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
587 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
589 // Try to shrink some forms of movsx.
590 case X86::MOVSX16rr8:
591 case X86::MOVSX32rr16:
592 case X86::MOVSX64rr32:
593 SimplifyMOVSX(OutMI);
598 static void LowerTlsAddr(MCStreamer &OutStreamer,
599 X86MCInstLower &MCInstLowering,
600 const MachineInstr &MI) {
602 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
603 MI.getOpcode() == X86::TLS_base_addr64;
605 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
607 MCContext &context = OutStreamer.getContext();
610 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
612 MCSymbolRefExpr::VariantKind SRVK;
613 switch (MI.getOpcode()) {
614 case X86::TLS_addr32:
615 case X86::TLS_addr64:
616 SRVK = MCSymbolRefExpr::VK_TLSGD;
618 case X86::TLS_base_addr32:
619 SRVK = MCSymbolRefExpr::VK_TLSLDM;
621 case X86::TLS_base_addr64:
622 SRVK = MCSymbolRefExpr::VK_TLSLD;
625 llvm_unreachable("unexpected opcode");
628 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
629 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
633 LEA.setOpcode(X86::LEA64r);
634 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
635 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
636 LEA.addOperand(MCOperand::CreateImm(1)); // scale
637 LEA.addOperand(MCOperand::CreateReg(0)); // index
638 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
639 LEA.addOperand(MCOperand::CreateReg(0)); // seg
640 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
641 LEA.setOpcode(X86::LEA32r);
642 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
643 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
644 LEA.addOperand(MCOperand::CreateImm(1)); // scale
645 LEA.addOperand(MCOperand::CreateReg(0)); // index
646 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
647 LEA.addOperand(MCOperand::CreateReg(0)); // seg
649 LEA.setOpcode(X86::LEA32r);
650 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
651 LEA.addOperand(MCOperand::CreateReg(0)); // base
652 LEA.addOperand(MCOperand::CreateImm(1)); // scale
653 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
654 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
655 LEA.addOperand(MCOperand::CreateReg(0)); // seg
657 OutStreamer.EmitInstruction(LEA);
660 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
661 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
662 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX));
665 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
666 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
667 const MCSymbolRefExpr *tlsRef =
668 MCSymbolRefExpr::Create(tlsGetAddr,
669 MCSymbolRefExpr::VK_PLT,
672 OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
677 static std::pair<StackMaps::Location, MachineInstr::const_mop_iterator>
678 parseMemoryOperand(StackMaps::Location::LocationType LocTy, unsigned Size,
679 MachineInstr::const_mop_iterator MOI,
680 MachineInstr::const_mop_iterator MOE) {
682 typedef StackMaps::Location Location;
684 assert(std::distance(MOI, MOE) >= 5 && "Too few operands to encode mem op.");
686 const MachineOperand &Base = *MOI;
687 const MachineOperand &Scale = *(++MOI);
688 const MachineOperand &Index = *(++MOI);
689 const MachineOperand &Disp = *(++MOI);
690 const MachineOperand &ZeroReg = *(++MOI);
692 // Sanity check for supported operand format.
693 assert(Base.isReg() &&
694 Scale.isImm() && Scale.getImm() == 1 &&
695 Index.isReg() && Index.getReg() == 0 &&
696 Disp.isImm() && ZeroReg.isReg() && (ZeroReg.getReg() == 0) &&
697 "Unsupported x86 memory operand sequence.");
702 return std::make_pair(
703 Location(LocTy, Size, Base.getReg(), Disp.getImm()), ++MOI);
706 std::pair<StackMaps::Location, MachineInstr::const_mop_iterator>
707 X86AsmPrinter::stackmapOperandParser(MachineInstr::const_mop_iterator MOI,
708 MachineInstr::const_mop_iterator MOE,
709 const TargetMachine &TM) {
711 typedef StackMaps::Location Location;
713 const MachineOperand &MOP = *MOI;
714 assert(!MOP.isRegMask() && (!MOP.isReg() || !MOP.isImplicit()) &&
715 "Register mask and implicit operands should not be processed.");
719 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
721 switch (MOP.getImm()) {
722 default: llvm_unreachable("Unrecognized operand type.");
723 case StackMaps::DirectMemRefOp: {
724 unsigned Size = TM.getDataLayout()->getPointerSizeInBits();
725 assert((Size % 8) == 0 && "Need pointer size in bytes.");
727 return parseMemoryOperand(StackMaps::Location::Direct, Size,
728 llvm::next(MOI), MOE);
730 case StackMaps::IndirectMemRefOp: {
732 int64_t Size = MOI->getImm();
733 assert(Size > 0 && "Need a valid size for indirect memory locations.");
734 return parseMemoryOperand(StackMaps::Location::Indirect, Size,
735 llvm::next(MOI), MOE);
737 case StackMaps::ConstantOp: {
739 assert(MOI->isImm() && "Expected constant operand.");
740 int64_t Imm = MOI->getImm();
741 return std::make_pair(
742 Location(Location::Constant, sizeof(int64_t), 0, Imm), ++MOI);
747 // Otherwise this is a reg operand. The physical register number will
748 // ultimately be encoded as a DWARF regno. The stack map also records the size
749 // of a spill slot that can hold the register content. (The runtime can
750 // track the actual size of the data type if it needs to.)
751 assert(MOP.isReg() && "Expected register operand here.");
752 assert(TargetRegisterInfo::isPhysicalRegister(MOP.getReg()) &&
753 "Virtreg operands should have been rewritten before now.");
754 const TargetRegisterClass *RC =
755 TM.getRegisterInfo()->getMinimalPhysRegClass(MOP.getReg());
756 assert(!MOP.getSubReg() && "Physical subreg still around.");
757 return std::make_pair(
758 Location(Location::Register, RC->getSize(), MOP.getReg(), 0), ++MOI);
761 // Lower a stackmap of the form:
762 // <id>, <shadowBytes>, ...
763 static void LowerSTACKMAP(MCStreamer &OutStreamer,
765 const MachineInstr &MI)
767 unsigned NumNOPBytes = MI.getOperand(1).getImm();
768 SM.recordStackMap(MI);
770 // FIXME: These nops ensure that the stackmap's shadow is covered by
771 // instructions from the same basic block, but the nops should not be
772 // necessary if instructions from the same block follow the stackmap.
773 for (unsigned i = 0; i < NumNOPBytes; ++i)
774 OutStreamer.EmitInstruction(MCInstBuilder(X86::NOOP));
777 // Lower a patchpoint of the form:
778 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
779 static void LowerPATCHPOINT(MCStreamer &OutStreamer,
781 const MachineInstr &MI) {
782 SM.recordPatchPoint(MI);
784 PatchPointOpers opers(&MI);
785 unsigned ScratchIdx = opers.getNextScratchIdx();
786 unsigned EncodedBytes = 0;
787 int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
789 // Emit MOV to materialize the target address and the CALL to target.
790 // This is encoded with 12-13 bytes, depending on which register is used.
791 // We conservatively assume that it is 12 bytes and emit in worst case one
794 OutStreamer.EmitInstruction(MCInstBuilder(X86::MOV64ri)
795 .addReg(MI.getOperand(ScratchIdx).getReg())
796 .addImm(CallTarget));
797 OutStreamer.EmitInstruction(MCInstBuilder(X86::CALL64r)
798 .addReg(MI.getOperand(ScratchIdx).getReg()));
801 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
802 assert(NumBytes >= EncodedBytes &&
803 "Patchpoint can't request size less than the length of a call.");
805 for (unsigned i = EncodedBytes; i < NumBytes; ++i)
806 OutStreamer.EmitInstruction(MCInstBuilder(X86::NOOP));
809 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
810 X86MCInstLower MCInstLowering(*MF, *this);
811 switch (MI->getOpcode()) {
812 case TargetOpcode::DBG_VALUE:
813 llvm_unreachable("Should be handled target independently");
815 // Emit nothing here but a comment if we can.
816 case X86::Int_MemBarrier:
817 if (OutStreamer.hasRawTextSupport())
818 OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
823 case X86::EH_RETURN64: {
824 // Lower these as normal, but add some comments.
825 unsigned Reg = MI->getOperand(0).getReg();
826 OutStreamer.AddComment(StringRef("eh_return, addr: %") +
827 X86ATTInstPrinter::getRegisterName(Reg));
832 case X86::TAILJMPd64:
833 // Lower these as normal, but add some comments.
834 OutStreamer.AddComment("TAILCALL");
837 case X86::TLS_addr32:
838 case X86::TLS_addr64:
839 case X86::TLS_base_addr32:
840 case X86::TLS_base_addr64:
841 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
843 case X86::MOVPC32r: {
844 // This is a pseudo op for a two instruction sequence with a label, which
851 MCSymbol *PICBase = MF->getPICBaseSymbol();
852 // FIXME: We would like an efficient form for this, so we don't have to do a
853 // lot of extra uniquing.
854 OutStreamer.EmitInstruction(MCInstBuilder(X86::CALLpcrel32)
855 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
858 OutStreamer.EmitLabel(PICBase);
861 OutStreamer.EmitInstruction(MCInstBuilder(X86::POP32r)
862 .addReg(MI->getOperand(0).getReg()));
867 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
868 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
871 // Okay, we have something like:
872 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
874 // For this, we want to print something like:
875 // MYGLOBAL + (. - PICBASE)
876 // However, we can't generate a ".", so just emit a new label here and refer
878 MCSymbol *DotSym = OutContext.CreateTempSymbol();
879 OutStreamer.EmitLabel(DotSym);
881 // Now that we have emitted the label, lower the complex operand expression.
882 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
884 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
885 const MCExpr *PICBase =
886 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
887 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
889 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
890 DotExpr, OutContext);
892 OutStreamer.EmitInstruction(MCInstBuilder(X86::ADD32ri)
893 .addReg(MI->getOperand(0).getReg())
894 .addReg(MI->getOperand(1).getReg())
899 case TargetOpcode::STACKMAP:
900 return LowerSTACKMAP(OutStreamer, SM, *MI);
902 case TargetOpcode::PATCHPOINT:
903 return LowerPATCHPOINT(OutStreamer, SM, *MI);
905 case X86::MORESTACK_RET:
906 OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
909 case X86::MORESTACK_RET_RESTORE_R10:
910 // Return, then restore R10.
911 OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
912 OutStreamer.EmitInstruction(MCInstBuilder(X86::MOV64rr)
919 MCInstLowering.Lower(MI, TmpInst);
920 OutStreamer.EmitInstruction(TmpInst);