1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "InstPrinter/X86ATTInstPrinter.h"
17 #include "X86COFFMachineModuleInfo.h"
18 #include "llvm/ADT/SmallString.h"
19 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
20 #include "llvm/CodeGen/StackMaps.h"
21 #include "llvm/IR/Type.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstBuilder.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSymbol.h"
29 #include "llvm/Support/FormattedStream.h"
30 #include "llvm/Target/Mangler.h"
35 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
36 class X86MCInstLower {
38 const MachineFunction &MF;
39 const TargetMachine &TM;
41 X86AsmPrinter &AsmPrinter;
43 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
45 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
47 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
48 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
51 MachineModuleInfoMachO &getMachOMMI() const;
52 Mangler *getMang() const {
53 return AsmPrinter.Mang;
57 } // end anonymous namespace
59 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
60 X86AsmPrinter &asmprinter)
61 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
62 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
64 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
65 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
69 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
70 /// operand to an MCSymbol.
71 MCSymbol *X86MCInstLower::
72 GetSymbolFromOperand(const MachineOperand &MO) const {
73 const DataLayout *DL = TM.getDataLayout();
74 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
76 SmallString<128> Name;
79 switch (MO.getTargetFlags()) {
80 case X86II::MO_DLLIMPORT:
81 // Handle dllimport linkage.
84 case X86II::MO_DARWIN_STUB:
87 case X86II::MO_DARWIN_NONLAZY:
88 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
89 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
90 Suffix = "$non_lazy_ptr";
95 Name += DL->getPrivateGlobalPrefix();
97 unsigned PrefixLen = Name.size();
100 const GlobalValue *GV = MO.getGlobal();
101 getMang()->getNameWithPrefix(Name, GV);
102 } else if (MO.isSymbol()) {
103 getMang()->getNameWithPrefix(Name, MO.getSymbolName());
104 } else if (MO.isMBB()) {
105 Name += MO.getMBB()->getSymbol()->getName();
107 unsigned OrigLen = Name.size() - PrefixLen;
110 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
112 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
114 // If the target flags on the operand changes the name of the symbol, do that
115 // before we return the symbol.
116 switch (MO.getTargetFlags()) {
118 case X86II::MO_DARWIN_NONLAZY:
119 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
120 MachineModuleInfoImpl::StubValueTy &StubSym =
121 getMachOMMI().getGVStubEntry(Sym);
122 if (StubSym.getPointer() == 0) {
123 assert(MO.isGlobal() && "Extern symbol not handled yet");
125 MachineModuleInfoImpl::
126 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
127 !MO.getGlobal()->hasInternalLinkage());
131 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
132 MachineModuleInfoImpl::StubValueTy &StubSym =
133 getMachOMMI().getHiddenGVStubEntry(Sym);
134 if (StubSym.getPointer() == 0) {
135 assert(MO.isGlobal() && "Extern symbol not handled yet");
137 MachineModuleInfoImpl::
138 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
139 !MO.getGlobal()->hasInternalLinkage());
143 case X86II::MO_DARWIN_STUB: {
144 MachineModuleInfoImpl::StubValueTy &StubSym =
145 getMachOMMI().getFnStubEntry(Sym);
146 if (StubSym.getPointer())
151 MachineModuleInfoImpl::
152 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
153 !MO.getGlobal()->hasInternalLinkage());
156 MachineModuleInfoImpl::
157 StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
166 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
167 MCSymbol *Sym) const {
168 // FIXME: We would like an efficient form for this, so we don't have to do a
169 // lot of extra uniquing.
170 const MCExpr *Expr = 0;
171 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
173 switch (MO.getTargetFlags()) {
174 default: llvm_unreachable("Unknown target flag on GV operand");
175 case X86II::MO_NO_FLAG: // No flag.
176 // These affect the name of the symbol, not any suffix.
177 case X86II::MO_DARWIN_NONLAZY:
178 case X86II::MO_DLLIMPORT:
179 case X86II::MO_DARWIN_STUB:
182 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
183 case X86II::MO_TLVP_PIC_BASE:
184 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
185 // Subtract the pic base.
186 Expr = MCBinaryExpr::CreateSub(Expr,
187 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
191 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
192 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
193 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
194 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
195 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
196 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
197 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
198 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
199 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
200 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
201 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
202 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
203 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
204 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
205 case X86II::MO_PIC_BASE_OFFSET:
206 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
207 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
208 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
209 // Subtract the pic base.
210 Expr = MCBinaryExpr::CreateSub(Expr,
211 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
213 if (MO.isJTI() && MAI.hasSetDirective()) {
214 // If .set directive is supported, use it to reduce the number of
215 // relocations the assembler will generate for differences between
216 // local labels. This is only safe when the symbols are in the same
217 // section so we are restricting it to jumptable references.
218 MCSymbol *Label = Ctx.CreateTempSymbol();
219 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
220 Expr = MCSymbolRefExpr::Create(Label, Ctx);
226 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
228 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
229 Expr = MCBinaryExpr::CreateAdd(Expr,
230 MCConstantExpr::Create(MO.getOffset(), Ctx),
232 return MCOperand::CreateExpr(Expr);
236 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
237 /// a short fixed-register form.
238 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
239 unsigned ImmOp = Inst.getNumOperands() - 1;
240 assert(Inst.getOperand(0).isReg() &&
241 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
242 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
243 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
244 Inst.getNumOperands() == 2) && "Unexpected instruction!");
246 // Check whether the destination register can be fixed.
247 unsigned Reg = Inst.getOperand(0).getReg();
248 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
251 // If so, rewrite the instruction.
252 MCOperand Saved = Inst.getOperand(ImmOp);
254 Inst.setOpcode(Opcode);
255 Inst.addOperand(Saved);
258 /// \brief If a movsx instruction has a shorter encoding for the used register
259 /// simplify the instruction to use it instead.
260 static void SimplifyMOVSX(MCInst &Inst) {
261 unsigned NewOpcode = 0;
262 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
263 switch (Inst.getOpcode()) {
265 llvm_unreachable("Unexpected instruction!");
266 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
267 if (Op0 == X86::AX && Op1 == X86::AL)
268 NewOpcode = X86::CBW;
270 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
271 if (Op0 == X86::EAX && Op1 == X86::AX)
272 NewOpcode = X86::CWDE;
274 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
275 if (Op0 == X86::RAX && Op1 == X86::EAX)
276 NewOpcode = X86::CDQE;
280 if (NewOpcode != 0) {
282 Inst.setOpcode(NewOpcode);
286 /// \brief Simplify things like MOV32rm to MOV32o32a.
287 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
289 // Don't make these simplifications in 64-bit mode; other assemblers don't
290 // perform them because they make the code larger.
291 if (Printer.getSubtarget().is64Bit())
294 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
295 unsigned AddrBase = IsStore;
296 unsigned RegOp = IsStore ? 0 : 5;
297 unsigned AddrOp = AddrBase + 3;
298 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
299 Inst.getOperand(AddrBase + 0).isReg() && // base
300 Inst.getOperand(AddrBase + 1).isImm() && // scale
301 Inst.getOperand(AddrBase + 2).isReg() && // index register
302 (Inst.getOperand(AddrOp).isExpr() || // address
303 Inst.getOperand(AddrOp).isImm())&&
304 Inst.getOperand(AddrBase + 4).isReg() && // segment
305 "Unexpected instruction!");
307 // Check whether the destination register can be fixed.
308 unsigned Reg = Inst.getOperand(RegOp).getReg();
309 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
312 // Check whether this is an absolute address.
313 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
315 bool Absolute = true;
316 if (Inst.getOperand(AddrOp).isExpr()) {
317 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
318 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
319 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
324 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
325 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
326 Inst.getOperand(AddrBase + 4).getReg() != 0 ||
327 Inst.getOperand(AddrBase + 1).getImm() != 1))
330 // If so, rewrite the instruction.
331 MCOperand Saved = Inst.getOperand(AddrOp);
333 Inst.setOpcode(Opcode);
334 Inst.addOperand(Saved);
337 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
338 OutMI.setOpcode(MI->getOpcode());
340 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
341 const MachineOperand &MO = MI->getOperand(i);
344 switch (MO.getType()) {
347 llvm_unreachable("unknown operand type");
348 case MachineOperand::MO_Register:
349 // Ignore all implicit register operands.
350 if (MO.isImplicit()) continue;
351 MCOp = MCOperand::CreateReg(MO.getReg());
353 case MachineOperand::MO_Immediate:
354 MCOp = MCOperand::CreateImm(MO.getImm());
356 case MachineOperand::MO_MachineBasicBlock:
357 case MachineOperand::MO_GlobalAddress:
358 case MachineOperand::MO_ExternalSymbol:
359 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
361 case MachineOperand::MO_JumpTableIndex:
362 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
364 case MachineOperand::MO_ConstantPoolIndex:
365 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
367 case MachineOperand::MO_BlockAddress:
368 MCOp = LowerSymbolOperand(MO,
369 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
371 case MachineOperand::MO_RegisterMask:
372 // Ignore call clobbers.
376 OutMI.addOperand(MCOp);
379 // Handle a few special cases to eliminate operand modifiers.
381 switch (OutMI.getOpcode()) {
386 // LEA should have a segment register, but it must be empty.
387 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
388 "Unexpected # of LEA operands");
389 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
390 "LEA has segment specified!");
394 OutMI.setOpcode(X86::MOV32ri);
397 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
398 // if one of the registers is extended, but other isn't.
400 case X86::VMOVAPDYrr:
402 case X86::VMOVAPSYrr:
404 case X86::VMOVDQAYrr:
406 case X86::VMOVDQUYrr:
408 case X86::VMOVUPDYrr:
410 case X86::VMOVUPSYrr: {
411 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
412 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
414 switch (OutMI.getOpcode()) {
415 default: llvm_unreachable("Invalid opcode");
416 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
417 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
418 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
419 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
420 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
421 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
422 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
423 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
424 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
425 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
426 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
427 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
429 OutMI.setOpcode(NewOpc);
434 case X86::VMOVSSrr: {
435 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
436 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
438 switch (OutMI.getOpcode()) {
439 default: llvm_unreachable("Invalid opcode");
440 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
441 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
443 OutMI.setOpcode(NewOpc);
448 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
449 // inputs modeled as normal uses instead of implicit uses. As such, truncate
450 // off all but the first operand (the callee). FIXME: Change isel.
451 case X86::TAILJMPr64:
453 case X86::CALL64pcrel32: {
454 unsigned Opcode = OutMI.getOpcode();
455 MCOperand Saved = OutMI.getOperand(0);
457 OutMI.setOpcode(Opcode);
458 OutMI.addOperand(Saved);
463 case X86::EH_RETURN64: {
465 OutMI.setOpcode(X86::RET);
469 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
472 case X86::TAILJMPd64: {
474 switch (OutMI.getOpcode()) {
475 default: llvm_unreachable("Invalid opcode");
476 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
478 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
481 MCOperand Saved = OutMI.getOperand(0);
483 OutMI.setOpcode(Opcode);
484 OutMI.addOperand(Saved);
488 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
489 // this with an ugly goto in case the resultant OR uses EAX and needs the
491 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
492 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
493 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
494 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
495 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
496 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
497 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
498 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
499 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
501 // The assembler backend wants to see branches in their small form and relax
502 // them to their large form. The JIT can only handle the large form because
503 // it does not do relaxation. For now, translate the large form to the
505 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
506 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
507 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
508 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
509 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
510 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
511 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
512 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
513 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
514 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
515 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
516 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
517 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
518 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
519 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
520 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
521 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
523 // Atomic load and store require a separate pseudo-inst because Acquire
524 // implies mayStore and Release implies mayLoad; fix these to regular MOV
526 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
527 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
528 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
529 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
530 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
531 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
532 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
533 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
535 // We don't currently select the correct instruction form for instructions
536 // which have a short %eax, etc. form. Handle this by custom lowering, for
539 // Note, we are currently not handling the following instructions:
540 // MOV64ao8, MOV64o8a
541 // XCHG16ar, XCHG32ar, XCHG64ar
542 case X86::MOV8mr_NOREX:
543 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
544 case X86::MOV8rm_NOREX:
545 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
546 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
547 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
548 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
549 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
551 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
552 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
553 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
554 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
555 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
556 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
557 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
558 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
559 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
560 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
561 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
562 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
563 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
564 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
565 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
566 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
567 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
568 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
569 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
570 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
571 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
572 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
573 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
574 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
575 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
576 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
577 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
578 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
579 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
580 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
581 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
582 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
583 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
584 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
585 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
586 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
588 // Try to shrink some forms of movsx.
589 case X86::MOVSX16rr8:
590 case X86::MOVSX32rr16:
591 case X86::MOVSX64rr32:
592 SimplifyMOVSX(OutMI);
597 static void LowerTlsAddr(MCStreamer &OutStreamer,
598 X86MCInstLower &MCInstLowering,
599 const MachineInstr &MI) {
601 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
602 MI.getOpcode() == X86::TLS_base_addr64;
604 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
606 MCContext &context = OutStreamer.getContext();
609 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
611 MCSymbolRefExpr::VariantKind SRVK;
612 switch (MI.getOpcode()) {
613 case X86::TLS_addr32:
614 case X86::TLS_addr64:
615 SRVK = MCSymbolRefExpr::VK_TLSGD;
617 case X86::TLS_base_addr32:
618 SRVK = MCSymbolRefExpr::VK_TLSLDM;
620 case X86::TLS_base_addr64:
621 SRVK = MCSymbolRefExpr::VK_TLSLD;
624 llvm_unreachable("unexpected opcode");
627 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
628 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
632 LEA.setOpcode(X86::LEA64r);
633 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
634 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
635 LEA.addOperand(MCOperand::CreateImm(1)); // scale
636 LEA.addOperand(MCOperand::CreateReg(0)); // index
637 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
638 LEA.addOperand(MCOperand::CreateReg(0)); // seg
639 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
640 LEA.setOpcode(X86::LEA32r);
641 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
642 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
643 LEA.addOperand(MCOperand::CreateImm(1)); // scale
644 LEA.addOperand(MCOperand::CreateReg(0)); // index
645 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
646 LEA.addOperand(MCOperand::CreateReg(0)); // seg
648 LEA.setOpcode(X86::LEA32r);
649 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
650 LEA.addOperand(MCOperand::CreateReg(0)); // base
651 LEA.addOperand(MCOperand::CreateImm(1)); // scale
652 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
653 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
654 LEA.addOperand(MCOperand::CreateReg(0)); // seg
656 OutStreamer.EmitInstruction(LEA);
659 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
660 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
661 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX));
664 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
665 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
666 const MCSymbolRefExpr *tlsRef =
667 MCSymbolRefExpr::Create(tlsGetAddr,
668 MCSymbolRefExpr::VK_PLT,
671 OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
676 /// \brief Emit the optimal amount of multi-byte nops on X86.
677 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit) {
678 // This works only for 64bit. For 32bit we have to do additional checking if
679 // the CPU supports multi-byte nops.
680 assert(Is64Bit && "EmitNops only supports X86-64");
682 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
683 Opc = IndexReg = Displacement = SegmentReg = 0;
684 BaseReg = X86::RAX; ScaleVal = 1;
686 case 0: llvm_unreachable("Zero nops?"); break;
687 case 1: NumBytes -= 1; Opc = X86::NOOP; break;
688 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
689 case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
690 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
691 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
692 IndexReg = X86::RAX; break;
693 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
694 IndexReg = X86::RAX; break;
695 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
696 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
697 IndexReg = X86::RAX; break;
698 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
699 IndexReg = X86::RAX; break;
700 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
701 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
704 unsigned NumPrefixes = std::min(NumBytes, 5U);
705 NumBytes -= NumPrefixes;
706 for (unsigned i = 0; i != NumPrefixes; ++i)
707 OS.EmitBytes("\x66");
710 default: llvm_unreachable("Unexpected opcode"); break;
712 OS.EmitInstruction(MCInstBuilder(Opc));
715 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX));
719 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal)
721 .addImm(Displacement)
722 .addReg(SegmentReg));
725 } // while (NumBytes)
728 // Lower a stackmap of the form:
729 // <id>, <shadowBytes>, ...
730 static void LowerSTACKMAP(MCStreamer &OS, StackMaps &SM,
731 const MachineInstr &MI, bool Is64Bit) {
732 unsigned NumBytes = MI.getOperand(1).getImm();
733 SM.recordStackMap(MI);
735 // FIXME: These nops ensure that the stackmap's shadow is covered by
736 // instructions from the same basic block, but the nops should not be
737 // necessary if instructions from the same block follow the stackmap.
738 EmitNops(OS, NumBytes, Is64Bit);
741 // Lower a patchpoint of the form:
742 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
743 static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM,
744 const MachineInstr &MI, bool Is64Bit) {
745 assert(Is64Bit && "Patchpoint currently only supports X86-64");
746 SM.recordPatchPoint(MI);
748 PatchPointOpers opers(&MI);
749 unsigned ScratchIdx = opers.getNextScratchIdx();
750 unsigned EncodedBytes = 0;
751 int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
753 // Emit MOV to materialize the target address and the CALL to target.
754 // This is encoded with 12-13 bytes, depending on which register is used.
755 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
756 if (X86II::isX86_64ExtendedReg(ScratchReg))
760 OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
761 .addImm(CallTarget));
762 OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
765 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
766 assert(NumBytes >= EncodedBytes &&
767 "Patchpoint can't request size less than the length of a call.");
769 EmitNops(OS, NumBytes - EncodedBytes, Is64Bit);
772 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
773 X86MCInstLower MCInstLowering(*MF, *this);
774 switch (MI->getOpcode()) {
775 case TargetOpcode::DBG_VALUE:
776 llvm_unreachable("Should be handled target independently");
778 // Emit nothing here but a comment if we can.
779 case X86::Int_MemBarrier:
780 if (OutStreamer.hasRawTextSupport())
781 OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
786 case X86::EH_RETURN64: {
787 // Lower these as normal, but add some comments.
788 unsigned Reg = MI->getOperand(0).getReg();
789 OutStreamer.AddComment(StringRef("eh_return, addr: %") +
790 X86ATTInstPrinter::getRegisterName(Reg));
795 case X86::TAILJMPd64:
796 // Lower these as normal, but add some comments.
797 OutStreamer.AddComment("TAILCALL");
800 case X86::TLS_addr32:
801 case X86::TLS_addr64:
802 case X86::TLS_base_addr32:
803 case X86::TLS_base_addr64:
804 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
806 case X86::MOVPC32r: {
807 // This is a pseudo op for a two instruction sequence with a label, which
814 MCSymbol *PICBase = MF->getPICBaseSymbol();
815 // FIXME: We would like an efficient form for this, so we don't have to do a
816 // lot of extra uniquing.
817 OutStreamer.EmitInstruction(MCInstBuilder(X86::CALLpcrel32)
818 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
821 OutStreamer.EmitLabel(PICBase);
824 OutStreamer.EmitInstruction(MCInstBuilder(X86::POP32r)
825 .addReg(MI->getOperand(0).getReg()));
830 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
831 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
834 // Okay, we have something like:
835 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
837 // For this, we want to print something like:
838 // MYGLOBAL + (. - PICBASE)
839 // However, we can't generate a ".", so just emit a new label here and refer
841 MCSymbol *DotSym = OutContext.CreateTempSymbol();
842 OutStreamer.EmitLabel(DotSym);
844 // Now that we have emitted the label, lower the complex operand expression.
845 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
847 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
848 const MCExpr *PICBase =
849 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
850 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
852 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
853 DotExpr, OutContext);
855 OutStreamer.EmitInstruction(MCInstBuilder(X86::ADD32ri)
856 .addReg(MI->getOperand(0).getReg())
857 .addReg(MI->getOperand(1).getReg())
862 case TargetOpcode::STACKMAP:
863 return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit());
865 case TargetOpcode::PATCHPOINT:
866 return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit());
868 case X86::MORESTACK_RET:
869 OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
872 case X86::MORESTACK_RET_RESTORE_R10:
873 // Return, then restore R10.
874 OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
875 OutStreamer.EmitInstruction(MCInstBuilder(X86::MOV64rr)
882 MCInstLowering.Lower(MI, TmpInst);
883 OutStreamer.EmitInstruction(TmpInst);