1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "X86COFFMachineModuleInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "llvm/Type.h"
19 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Target/Mangler.h"
27 #include "llvm/Support/FormattedStream.h"
28 #include "llvm/ADT/SmallString.h"
33 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
34 class X86MCInstLower {
37 const MachineFunction &MF;
38 const TargetMachine &TM;
40 X86AsmPrinter &AsmPrinter;
42 X86MCInstLower(Mangler *mang, const MachineFunction &MF,
43 X86AsmPrinter &asmprinter);
45 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
47 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
48 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
51 MachineModuleInfoMachO &getMachOMMI() const;
54 } // end anonymous namespace
56 X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf,
57 X86AsmPrinter &asmprinter)
58 : Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()),
59 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
61 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
62 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
66 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
67 /// operand to an MCSymbol.
68 MCSymbol *X86MCInstLower::
69 GetSymbolFromOperand(const MachineOperand &MO) const {
70 assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference");
72 SmallString<128> Name;
75 assert(MO.isSymbol());
76 Name += MAI.getGlobalPrefix();
77 Name += MO.getSymbolName();
79 const GlobalValue *GV = MO.getGlobal();
80 bool isImplicitlyPrivate = false;
81 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
82 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
83 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
84 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
85 isImplicitlyPrivate = true;
87 Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
90 // If the target flags on the operand changes the name of the symbol, do that
91 // before we return the symbol.
92 switch (MO.getTargetFlags()) {
94 case X86II::MO_DLLIMPORT: {
95 // Handle dllimport linkage.
96 const char *Prefix = "__imp_";
97 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
100 case X86II::MO_DARWIN_NONLAZY:
101 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
102 Name += "$non_lazy_ptr";
103 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
105 MachineModuleInfoImpl::StubValueTy &StubSym =
106 getMachOMMI().getGVStubEntry(Sym);
107 if (StubSym.getPointer() == 0) {
108 assert(MO.isGlobal() && "Extern symbol not handled yet");
110 MachineModuleInfoImpl::
111 StubValueTy(Mang->getSymbol(MO.getGlobal()),
112 !MO.getGlobal()->hasInternalLinkage());
116 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
117 Name += "$non_lazy_ptr";
118 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
119 MachineModuleInfoImpl::StubValueTy &StubSym =
120 getMachOMMI().getHiddenGVStubEntry(Sym);
121 if (StubSym.getPointer() == 0) {
122 assert(MO.isGlobal() && "Extern symbol not handled yet");
124 MachineModuleInfoImpl::
125 StubValueTy(Mang->getSymbol(MO.getGlobal()),
126 !MO.getGlobal()->hasInternalLinkage());
130 case X86II::MO_DARWIN_STUB: {
132 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
133 MachineModuleInfoImpl::StubValueTy &StubSym =
134 getMachOMMI().getFnStubEntry(Sym);
135 if (StubSym.getPointer())
140 MachineModuleInfoImpl::
141 StubValueTy(Mang->getSymbol(MO.getGlobal()),
142 !MO.getGlobal()->hasInternalLinkage());
144 Name.erase(Name.end()-5, Name.end());
146 MachineModuleInfoImpl::
147 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
153 return Ctx.GetOrCreateSymbol(Name.str());
156 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
157 MCSymbol *Sym) const {
158 // FIXME: We would like an efficient form for this, so we don't have to do a
159 // lot of extra uniquing.
160 const MCExpr *Expr = 0;
161 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
163 switch (MO.getTargetFlags()) {
164 default: llvm_unreachable("Unknown target flag on GV operand");
165 case X86II::MO_NO_FLAG: // No flag.
166 // These affect the name of the symbol, not any suffix.
167 case X86II::MO_DARWIN_NONLAZY:
168 case X86II::MO_DLLIMPORT:
169 case X86II::MO_DARWIN_STUB:
172 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
173 case X86II::MO_TLVP_PIC_BASE:
174 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
175 // Subtract the pic base.
176 Expr = MCBinaryExpr::CreateSub(Expr,
177 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
181 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
182 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
183 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
184 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
185 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
186 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
187 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
188 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
189 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
190 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
191 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
192 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
193 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
194 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
195 case X86II::MO_PIC_BASE_OFFSET:
196 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
197 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
198 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
199 // Subtract the pic base.
200 Expr = MCBinaryExpr::CreateSub(Expr,
201 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
203 if (MO.isJTI() && MAI.hasSetDirective()) {
204 // If .set directive is supported, use it to reduce the number of
205 // relocations the assembler will generate for differences between
206 // local labels. This is only safe when the symbols are in the same
207 // section so we are restricting it to jumptable references.
208 MCSymbol *Label = Ctx.CreateTempSymbol();
209 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
210 Expr = MCSymbolRefExpr::Create(Label, Ctx);
216 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
218 if (!MO.isJTI() && MO.getOffset())
219 Expr = MCBinaryExpr::CreateAdd(Expr,
220 MCConstantExpr::Create(MO.getOffset(), Ctx),
222 return MCOperand::CreateExpr(Expr);
227 static void lower_subreg32(MCInst *MI, unsigned OpNo) {
228 // Convert registers in the addr mode according to subreg32.
229 unsigned Reg = MI->getOperand(OpNo).getReg();
231 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
234 static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
235 // Convert registers in the addr mode according to subreg64.
236 for (unsigned i = 0; i != 4; ++i) {
237 if (!MI->getOperand(OpNo+i).isReg()) continue;
239 unsigned Reg = MI->getOperand(OpNo+i).getReg();
240 if (Reg == 0) continue;
242 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
246 /// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
247 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
248 OutMI.setOpcode(NewOpc);
249 lower_subreg32(&OutMI, 0);
251 /// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
252 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
253 OutMI.setOpcode(NewOpc);
254 OutMI.addOperand(OutMI.getOperand(0));
255 OutMI.addOperand(OutMI.getOperand(0));
258 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
259 /// a short fixed-register form.
260 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
261 unsigned ImmOp = Inst.getNumOperands() - 1;
262 assert(Inst.getOperand(0).isReg() &&
263 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
264 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
265 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
266 Inst.getNumOperands() == 2) && "Unexpected instruction!");
268 // Check whether the destination register can be fixed.
269 unsigned Reg = Inst.getOperand(0).getReg();
270 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
273 // If so, rewrite the instruction.
274 MCOperand Saved = Inst.getOperand(ImmOp);
276 Inst.setOpcode(Opcode);
277 Inst.addOperand(Saved);
280 /// \brief Simplify things like MOV32rm to MOV32o32a.
281 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
283 // Don't make these simplifications in 64-bit mode; other assemblers don't
284 // perform them because they make the code larger.
285 if (Printer.getSubtarget().is64Bit())
288 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
289 unsigned AddrBase = IsStore;
290 unsigned RegOp = IsStore ? 0 : 5;
291 unsigned AddrOp = AddrBase + 3;
292 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
293 Inst.getOperand(AddrBase + 0).isReg() && // base
294 Inst.getOperand(AddrBase + 1).isImm() && // scale
295 Inst.getOperand(AddrBase + 2).isReg() && // index register
296 (Inst.getOperand(AddrOp).isExpr() || // address
297 Inst.getOperand(AddrOp).isImm())&&
298 Inst.getOperand(AddrBase + 4).isReg() && // segment
299 "Unexpected instruction!");
301 // Check whether the destination register can be fixed.
302 unsigned Reg = Inst.getOperand(RegOp).getReg();
303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
306 // Check whether this is an absolute address.
307 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
309 bool Absolute = true;
310 if (Inst.getOperand(AddrOp).isExpr()) {
311 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
312 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
313 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
318 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
319 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
320 Inst.getOperand(AddrBase + 4).getReg() != 0 ||
321 Inst.getOperand(AddrBase + 1).getImm() != 1))
324 // If so, rewrite the instruction.
325 MCOperand Saved = Inst.getOperand(AddrOp);
327 Inst.setOpcode(Opcode);
328 Inst.addOperand(Saved);
331 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
332 OutMI.setOpcode(MI->getOpcode());
334 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
335 const MachineOperand &MO = MI->getOperand(i);
338 switch (MO.getType()) {
341 llvm_unreachable("unknown operand type");
342 case MachineOperand::MO_Register:
343 // Ignore all implicit register operands.
344 if (MO.isImplicit()) continue;
345 MCOp = MCOperand::CreateReg(MO.getReg());
347 case MachineOperand::MO_Immediate:
348 MCOp = MCOperand::CreateImm(MO.getImm());
350 case MachineOperand::MO_MachineBasicBlock:
351 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
352 MO.getMBB()->getSymbol(), Ctx));
354 case MachineOperand::MO_GlobalAddress:
355 case MachineOperand::MO_ExternalSymbol:
356 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
358 case MachineOperand::MO_JumpTableIndex:
359 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
361 case MachineOperand::MO_ConstantPoolIndex:
362 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
364 case MachineOperand::MO_BlockAddress:
365 MCOp = LowerSymbolOperand(MO,
366 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
368 case MachineOperand::MO_RegisterMask:
369 // Ignore call clobbers.
373 OutMI.addOperand(MCOp);
376 // Handle a few special cases to eliminate operand modifiers.
378 switch (OutMI.getOpcode()) {
379 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
380 lower_lea64_32mem(&OutMI, 1);
385 // LEA should have a segment register, but it must be empty.
386 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
387 "Unexpected # of LEA operands");
388 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
389 "LEA has segment specified!");
391 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
392 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
393 case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
394 case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
395 case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
396 case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
397 case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
398 case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
399 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
402 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
403 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
406 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
407 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
410 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
411 // inputs modeled as normal uses instead of implicit uses. As such, truncate
412 // off all but the first operand (the callee). FIXME: Change isel.
413 case X86::TAILJMPr64:
415 case X86::CALL64pcrel32: {
416 unsigned Opcode = OutMI.getOpcode();
417 MCOperand Saved = OutMI.getOperand(0);
419 OutMI.setOpcode(Opcode);
420 OutMI.addOperand(Saved);
425 case X86::EH_RETURN64: {
427 OutMI.setOpcode(X86::RET);
431 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
434 case X86::TAILJMPd64: {
436 switch (OutMI.getOpcode()) {
437 default: llvm_unreachable("Invalid opcode");
438 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
440 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
443 MCOperand Saved = OutMI.getOperand(0);
445 OutMI.setOpcode(Opcode);
446 OutMI.addOperand(Saved);
450 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
451 // this with an ugly goto in case the resultant OR uses EAX and needs the
453 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
454 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
455 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
456 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
457 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
458 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
459 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
460 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
461 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
463 // The assembler backend wants to see branches in their small form and relax
464 // them to their large form. The JIT can only handle the large form because
465 // it does not do relaxation. For now, translate the large form to the
467 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
468 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
469 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
470 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
471 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
472 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
473 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
474 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
475 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
476 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
477 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
478 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
479 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
480 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
481 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
482 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
483 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
485 // Atomic load and store require a separate pseudo-inst because Acquire
486 // implies mayStore and Release implies mayLoad; fix these to regular MOV
488 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
489 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
490 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
491 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
492 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
493 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
494 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
495 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
497 // We don't currently select the correct instruction form for instructions
498 // which have a short %eax, etc. form. Handle this by custom lowering, for
501 // Note, we are currently not handling the following instructions:
502 // MOV64ao8, MOV64o8a
503 // XCHG16ar, XCHG32ar, XCHG64ar
504 case X86::MOV8mr_NOREX:
505 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
506 case X86::MOV8rm_NOREX:
507 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
508 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
509 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
510 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
511 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
513 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
514 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
515 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
516 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
517 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
518 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
519 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
520 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
521 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
522 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
523 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
524 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
525 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
526 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
527 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
528 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
529 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
530 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
531 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
532 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
533 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
534 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
535 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
536 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
537 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
538 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
539 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
540 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
541 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
542 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
543 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
544 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
545 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
546 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
547 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
548 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
550 case X86::MORESTACK_RET:
551 OutMI.setOpcode(X86::RET);
554 case X86::MORESTACK_RET_RESTORE_R10: {
557 OutMI.setOpcode(X86::MOV64rr);
558 OutMI.addOperand(MCOperand::CreateReg(X86::R10));
559 OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
561 retInst.setOpcode(X86::RET);
562 AsmPrinter.OutStreamer.EmitInstruction(retInst);
568 static void LowerTlsAddr(MCStreamer &OutStreamer,
569 X86MCInstLower &MCInstLowering,
570 const MachineInstr &MI) {
572 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
573 MI.getOpcode() == X86::TLS_base_addr64;
575 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
577 MCContext &context = OutStreamer.getContext();
581 prefix.setOpcode(X86::DATA16_PREFIX);
582 OutStreamer.EmitInstruction(prefix);
585 MCSymbolRefExpr::VariantKind SRVK;
586 switch (MI.getOpcode()) {
587 case X86::TLS_addr32:
588 case X86::TLS_addr64:
589 SRVK = MCSymbolRefExpr::VK_TLSGD;
591 case X86::TLS_base_addr32:
592 SRVK = MCSymbolRefExpr::VK_TLSLDM;
594 case X86::TLS_base_addr64:
595 SRVK = MCSymbolRefExpr::VK_TLSLD;
598 llvm_unreachable("unexpected opcode");
601 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
602 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
606 LEA.setOpcode(X86::LEA64r);
607 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
608 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
609 LEA.addOperand(MCOperand::CreateImm(1)); // scale
610 LEA.addOperand(MCOperand::CreateReg(0)); // index
611 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
612 LEA.addOperand(MCOperand::CreateReg(0)); // seg
613 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
614 LEA.setOpcode(X86::LEA32r);
615 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
616 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
617 LEA.addOperand(MCOperand::CreateImm(1)); // scale
618 LEA.addOperand(MCOperand::CreateReg(0)); // index
619 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
620 LEA.addOperand(MCOperand::CreateReg(0)); // seg
622 LEA.setOpcode(X86::LEA32r);
623 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
624 LEA.addOperand(MCOperand::CreateReg(0)); // base
625 LEA.addOperand(MCOperand::CreateImm(1)); // scale
626 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
627 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
628 LEA.addOperand(MCOperand::CreateReg(0)); // seg
630 OutStreamer.EmitInstruction(LEA);
634 prefix.setOpcode(X86::DATA16_PREFIX);
635 OutStreamer.EmitInstruction(prefix);
636 prefix.setOpcode(X86::DATA16_PREFIX);
637 OutStreamer.EmitInstruction(prefix);
638 prefix.setOpcode(X86::REX64_PREFIX);
639 OutStreamer.EmitInstruction(prefix);
644 call.setOpcode(X86::CALL64pcrel32);
646 call.setOpcode(X86::CALLpcrel32);
647 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
648 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
649 const MCSymbolRefExpr *tlsRef =
650 MCSymbolRefExpr::Create(tlsGetAddr,
651 MCSymbolRefExpr::VK_PLT,
654 call.addOperand(MCOperand::CreateExpr(tlsRef));
655 OutStreamer.EmitInstruction(call);
658 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
659 X86MCInstLower MCInstLowering(Mang, *MF, *this);
660 switch (MI->getOpcode()) {
661 case TargetOpcode::DBG_VALUE:
662 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
664 raw_string_ostream OS(TmpStr);
665 PrintDebugValueComment(MI, OS);
666 OutStreamer.EmitRawText(StringRef(OS.str()));
670 // Emit nothing here but a comment if we can.
671 case X86::Int_MemBarrier:
672 if (OutStreamer.hasRawTextSupport())
673 OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
678 case X86::EH_RETURN64: {
679 // Lower these as normal, but add some comments.
680 unsigned Reg = MI->getOperand(0).getReg();
681 OutStreamer.AddComment(StringRef("eh_return, addr: %") +
682 X86ATTInstPrinter::getRegisterName(Reg));
687 case X86::TAILJMPd64:
688 // Lower these as normal, but add some comments.
689 OutStreamer.AddComment("TAILCALL");
692 case X86::TLS_addr32:
693 case X86::TLS_addr64:
694 case X86::TLS_base_addr32:
695 case X86::TLS_base_addr64:
696 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
698 case X86::MOVPC32r: {
700 // This is a pseudo op for a two instruction sequence with a label, which
707 MCSymbol *PICBase = MF->getPICBaseSymbol();
708 TmpInst.setOpcode(X86::CALLpcrel32);
709 // FIXME: We would like an efficient form for this, so we don't have to do a
710 // lot of extra uniquing.
711 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
713 OutStreamer.EmitInstruction(TmpInst);
716 OutStreamer.EmitLabel(PICBase);
719 TmpInst.setOpcode(X86::POP32r);
720 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
721 OutStreamer.EmitInstruction(TmpInst);
726 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
727 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
730 // Okay, we have something like:
731 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
733 // For this, we want to print something like:
734 // MYGLOBAL + (. - PICBASE)
735 // However, we can't generate a ".", so just emit a new label here and refer
737 MCSymbol *DotSym = OutContext.CreateTempSymbol();
738 OutStreamer.EmitLabel(DotSym);
740 // Now that we have emitted the label, lower the complex operand expression.
741 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
743 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
744 const MCExpr *PICBase =
745 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
746 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
748 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
749 DotExpr, OutContext);
752 TmpInst.setOpcode(X86::ADD32ri);
753 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
754 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
755 TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
756 OutStreamer.EmitInstruction(TmpInst);
762 MCInstLowering.Lower(MI, TmpInst);
763 OutStreamer.EmitInstruction(TmpInst);