1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/CommandLine.h"
45 ForceStackAlign("force-align-stack",
46 cl::desc("Force align the stack to the minimum alignment"
47 " needed for the function."),
48 cl::init(false), cl::Hidden);
50 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
51 const TargetInstrInfo &tii)
52 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
53 X86::ADJCALLSTACKDOWN64 :
54 X86::ADJCALLSTACKDOWN32,
55 tm.getSubtarget<X86Subtarget>().is64Bit() ?
56 X86::ADJCALLSTACKUP64 :
57 X86::ADJCALLSTACKUP32),
59 // Cache some information.
60 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
61 Is64Bit = Subtarget->is64Bit();
62 IsWin64 = Subtarget->isTargetWin64();
63 StackAlign = TM.getFrameInfo()->getStackAlignment();
76 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
77 /// specific numbering, used in debug info and exception tables.
78 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
79 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
80 unsigned Flavour = DWARFFlavour::X86_64;
82 if (!Subtarget->is64Bit()) {
83 if (Subtarget->isTargetDarwin()) {
85 Flavour = DWARFFlavour::X86_32_DarwinEH;
87 Flavour = DWARFFlavour::X86_32_Generic;
88 } else if (Subtarget->isTargetCygMing()) {
89 // Unsupported by now, just quick fallback
90 Flavour = DWARFFlavour::X86_32_Generic;
92 Flavour = DWARFFlavour::X86_32_Generic;
96 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
99 /// getX86RegNum - This function maps LLVM register identifiers to their X86
100 /// specific numbering, which is used in various places encoding instructions.
101 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
103 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
104 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
105 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
106 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
107 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
109 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
111 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
113 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
116 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
118 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
120 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
122 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
124 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
126 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
128 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
130 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
133 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
134 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
135 return RegNo-X86::ST0;
137 case X86::XMM0: case X86::XMM8:
138 case X86::YMM0: case X86::YMM8: case X86::MM0:
140 case X86::XMM1: case X86::XMM9:
141 case X86::YMM1: case X86::YMM9: case X86::MM1:
143 case X86::XMM2: case X86::XMM10:
144 case X86::YMM2: case X86::YMM10: case X86::MM2:
146 case X86::XMM3: case X86::XMM11:
147 case X86::YMM3: case X86::YMM11: case X86::MM3:
149 case X86::XMM4: case X86::XMM12:
150 case X86::YMM4: case X86::YMM12: case X86::MM4:
152 case X86::XMM5: case X86::XMM13:
153 case X86::YMM5: case X86::YMM13: case X86::MM5:
155 case X86::XMM6: case X86::XMM14:
156 case X86::YMM6: case X86::YMM14: case X86::MM6:
158 case X86::XMM7: case X86::XMM15:
159 case X86::YMM7: case X86::YMM15: case X86::MM7:
203 // Pseudo index registers are equivalent to a "none"
204 // scaled index (See Intel Manual 2A, table 2-3)
210 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
211 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
216 const TargetRegisterClass *
217 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
218 const TargetRegisterClass *B,
219 unsigned SubIdx) const {
223 if (B == &X86::GR8RegClass) {
224 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
226 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
227 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
228 A == &X86::GR64_NOREXRegClass ||
229 A == &X86::GR64_NOSPRegClass ||
230 A == &X86::GR64_NOREX_NOSPRegClass)
231 return &X86::GR64_ABCDRegClass;
232 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
233 A == &X86::GR32_NOREXRegClass ||
234 A == &X86::GR32_NOSPRegClass)
235 return &X86::GR32_ABCDRegClass;
236 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
237 A == &X86::GR16_NOREXRegClass)
238 return &X86::GR16_ABCDRegClass;
239 } else if (B == &X86::GR8_NOREXRegClass) {
240 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
241 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
242 return &X86::GR64_NOREXRegClass;
243 else if (A == &X86::GR64_ABCDRegClass)
244 return &X86::GR64_ABCDRegClass;
245 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
246 A == &X86::GR32_NOSPRegClass)
247 return &X86::GR32_NOREXRegClass;
248 else if (A == &X86::GR32_ABCDRegClass)
249 return &X86::GR32_ABCDRegClass;
250 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
251 return &X86::GR16_NOREXRegClass;
252 else if (A == &X86::GR16_ABCDRegClass)
253 return &X86::GR16_ABCDRegClass;
256 case X86::sub_8bit_hi:
257 if (B == &X86::GR8_ABCD_HRegClass) {
258 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
259 A == &X86::GR64_NOREXRegClass ||
260 A == &X86::GR64_NOSPRegClass ||
261 A == &X86::GR64_NOREX_NOSPRegClass)
262 return &X86::GR64_ABCDRegClass;
263 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
264 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
265 return &X86::GR32_ABCDRegClass;
266 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
267 A == &X86::GR16_NOREXRegClass)
268 return &X86::GR16_ABCDRegClass;
272 if (B == &X86::GR16RegClass) {
273 if (A->getSize() == 4 || A->getSize() == 8)
275 } else if (B == &X86::GR16_ABCDRegClass) {
276 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
277 A == &X86::GR64_NOREXRegClass ||
278 A == &X86::GR64_NOSPRegClass ||
279 A == &X86::GR64_NOREX_NOSPRegClass)
280 return &X86::GR64_ABCDRegClass;
281 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
282 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
283 return &X86::GR32_ABCDRegClass;
284 } else if (B == &X86::GR16_NOREXRegClass) {
285 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
286 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
287 return &X86::GR64_NOREXRegClass;
288 else if (A == &X86::GR64_ABCDRegClass)
289 return &X86::GR64_ABCDRegClass;
290 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
291 A == &X86::GR32_NOSPRegClass)
292 return &X86::GR32_NOREXRegClass;
293 else if (A == &X86::GR32_ABCDRegClass)
294 return &X86::GR64_ABCDRegClass;
298 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
299 if (A->getSize() == 8)
301 } else if (B == &X86::GR32_ABCDRegClass) {
302 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
303 A == &X86::GR64_NOREXRegClass ||
304 A == &X86::GR64_NOSPRegClass ||
305 A == &X86::GR64_NOREX_NOSPRegClass)
306 return &X86::GR64_ABCDRegClass;
307 } else if (B == &X86::GR32_NOREXRegClass) {
308 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
309 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
310 return &X86::GR64_NOREXRegClass;
311 else if (A == &X86::GR64_ABCDRegClass)
312 return &X86::GR64_ABCDRegClass;
316 if (B == &X86::FR32RegClass)
320 if (B == &X86::FR64RegClass)
324 if (B == &X86::VR128RegClass)
331 const TargetRegisterClass *
332 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
334 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
335 case 0: // Normal GPRs.
336 if (TM.getSubtarget<X86Subtarget>().is64Bit())
337 return &X86::GR64RegClass;
338 return &X86::GR32RegClass;
339 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
340 if (TM.getSubtarget<X86Subtarget>().is64Bit())
341 return &X86::GR64_NOSPRegClass;
342 return &X86::GR32_NOSPRegClass;
346 const TargetRegisterClass *
347 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
348 if (RC == &X86::CCRRegClass) {
350 return &X86::GR64RegClass;
352 return &X86::GR32RegClass;
358 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
359 bool callsEHReturn = false;
360 bool ghcCall = false;
363 callsEHReturn = MF->getMMI().callsEHReturn();
364 const Function *F = MF->getFunction();
365 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
368 static const unsigned GhcCalleeSavedRegs[] = {
372 static const unsigned CalleeSavedRegs32Bit[] = {
373 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
376 static const unsigned CalleeSavedRegs32EHRet[] = {
377 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
380 static const unsigned CalleeSavedRegs64Bit[] = {
381 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
384 static const unsigned CalleeSavedRegs64EHRet[] = {
385 X86::RAX, X86::RDX, X86::RBX, X86::R12,
386 X86::R13, X86::R14, X86::R15, X86::RBP, 0
389 static const unsigned CalleeSavedRegsWin64[] = {
390 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
391 X86::R12, X86::R13, X86::R14, X86::R15,
392 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
393 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
394 X86::XMM14, X86::XMM15, 0
398 return GhcCalleeSavedRegs;
399 } else if (Is64Bit) {
401 return CalleeSavedRegsWin64;
403 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
405 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
409 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
410 BitVector Reserved(getNumRegs());
411 // Set the stack-pointer register and its aliases as reserved.
412 Reserved.set(X86::RSP);
413 Reserved.set(X86::ESP);
414 Reserved.set(X86::SP);
415 Reserved.set(X86::SPL);
417 // Set the instruction pointer register and its aliases as reserved.
418 Reserved.set(X86::RIP);
419 Reserved.set(X86::EIP);
420 Reserved.set(X86::IP);
422 // Set the frame-pointer register and its aliases as reserved if needed.
424 Reserved.set(X86::RBP);
425 Reserved.set(X86::EBP);
426 Reserved.set(X86::BP);
427 Reserved.set(X86::BPL);
430 // Mark the x87 stack registers as reserved, since they don't behave normally
431 // with respect to liveness. We don't fully model the effects of x87 stack
432 // pushes and pops after stackification.
433 Reserved.set(X86::ST0);
434 Reserved.set(X86::ST1);
435 Reserved.set(X86::ST2);
436 Reserved.set(X86::ST3);
437 Reserved.set(X86::ST4);
438 Reserved.set(X86::ST5);
439 Reserved.set(X86::ST6);
440 Reserved.set(X86::ST7);
444 //===----------------------------------------------------------------------===//
445 // Stack Frame Processing methods
446 //===----------------------------------------------------------------------===//
448 /// hasFP - Return true if the specified function should have a dedicated frame
449 /// pointer register. This is true if the function has variable sized allocas
450 /// or if frame pointer elimination is disabled.
451 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
452 const MachineFrameInfo *MFI = MF.getFrameInfo();
453 const MachineModuleInfo &MMI = MF.getMMI();
455 return (DisableFramePointerElim(MF) ||
456 needsStackRealignment(MF) ||
457 MFI->hasVarSizedObjects() ||
458 MFI->isFrameAddressTaken() ||
459 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
460 MMI.callsUnwindInit());
463 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
464 const MachineFrameInfo *MFI = MF.getFrameInfo();
465 return (RealignStack &&
466 !MFI->hasVarSizedObjects());
469 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
470 const MachineFrameInfo *MFI = MF.getFrameInfo();
471 const Function *F = MF.getFunction();
472 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
473 F->hasFnAttr(Attribute::StackAlignment));
475 // FIXME: Currently we don't support stack realignment for functions with
476 // variable-sized allocas.
477 // FIXME: It's more complicated than this...
478 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
480 "Stack realignment in presense of dynamic allocas is not supported");
482 // If we've requested that we force align the stack do so now.
484 return canRealignStack(MF);
486 return requiresRealignment && canRealignStack(MF);
489 bool X86RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
490 return !MF.getFrameInfo()->hasVarSizedObjects();
493 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
494 unsigned Reg, int &FrameIdx) const {
495 if (Reg == FramePtr && hasFP(MF)) {
496 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
503 X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
504 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
505 const MachineFrameInfo *MFI = MF.getFrameInfo();
506 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
507 uint64_t StackSize = MFI->getStackSize();
509 if (needsStackRealignment(MF)) {
511 // Skip the saved EBP.
514 unsigned Align = MFI->getObjectAlignment(FI);
515 assert((-(Offset + StackSize)) % Align == 0);
517 return Offset + StackSize;
519 // FIXME: Support tail calls
522 return Offset + StackSize;
524 // Skip the saved EBP.
527 // Skip the RETADDR move area
528 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
529 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
530 if (TailCallReturnAddrDelta < 0)
531 Offset -= TailCallReturnAddrDelta;
537 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
540 return X86::SUB64ri8;
541 return X86::SUB64ri32;
544 return X86::SUB32ri8;
549 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
552 return X86::ADD64ri8;
553 return X86::ADD64ri32;
556 return X86::ADD32ri8;
561 void X86RegisterInfo::
562 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
563 MachineBasicBlock::iterator I) const {
564 if (!hasReservedCallFrame(MF)) {
565 // If the stack pointer can be changed after prologue, turn the
566 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
567 // adjcallstackdown instruction into 'add ESP, <amt>'
568 // TODO: consider using push / pop instead of sub + store / add
569 MachineInstr *Old = I;
570 uint64_t Amount = Old->getOperand(0).getImm();
572 // We need to keep the stack aligned properly. To do this, we round the
573 // amount of space needed for the outgoing arguments up to the next
574 // alignment boundary.
575 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
577 MachineInstr *New = 0;
578 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
579 New = BuildMI(MF, Old->getDebugLoc(),
580 TII.get(getSUBriOpcode(Is64Bit, Amount)),
585 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
587 // Factor out the amount the callee already popped.
588 uint64_t CalleeAmt = Old->getOperand(1).getImm();
592 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
593 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
600 // The EFLAGS implicit def is dead.
601 New->getOperand(3).setIsDead();
603 // Replace the pseudo instruction with a new instruction.
607 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
608 // If we are performing frame pointer elimination and if the callee pops
609 // something off the stack pointer, add it back. We do this until we have
610 // more advanced stack pointer tracking ability.
611 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
612 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
613 MachineInstr *Old = I;
615 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
620 // The EFLAGS implicit def is dead.
621 New->getOperand(3).setIsDead();
630 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
631 int SPAdj, RegScavenger *RS) const{
632 assert(SPAdj == 0 && "Unexpected");
635 MachineInstr &MI = *II;
636 MachineFunction &MF = *MI.getParent()->getParent();
638 while (!MI.getOperand(i).isFI()) {
640 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
643 int FrameIndex = MI.getOperand(i).getIndex();
646 unsigned Opc = MI.getOpcode();
647 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
648 if (needsStackRealignment(MF))
649 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
653 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
655 // This must be part of a four operand memory reference. Replace the
656 // FrameIndex with base register with EBP. Add an offset to the offset.
657 MI.getOperand(i).ChangeToRegister(BasePtr, false);
659 // Now add the frame object offset to the offset from EBP.
662 // Tail call jmp happens after FP is popped.
663 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
664 const MachineFrameInfo *MFI = MF.getFrameInfo();
665 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI.getOffsetOfLocalArea();
667 FIOffset = getFrameIndexOffset(MF, FrameIndex);
669 if (MI.getOperand(i+3).isImm()) {
670 // Offset is a 32-bit integer.
671 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
672 MI.getOperand(i + 3).ChangeToImmediate(Offset);
674 // Offset is symbolic. This is extremely rare.
675 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
676 MI.getOperand(i+3).setOffset(Offset);
681 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
682 RegScavenger *RS) const {
683 MachineFrameInfo *MFI = MF.getFrameInfo();
685 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
686 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
688 if (TailCallReturnAddrDelta < 0) {
689 // create RETURNADDR area
698 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
699 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
703 assert((TailCallReturnAddrDelta <= 0) &&
704 "The Delta should always be zero or negative");
705 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
707 // Create a frame entry for the EBP register that must be saved.
708 int FrameIdx = MFI->CreateFixedObject(SlotSize,
710 TFI.getOffsetOfLocalArea() +
711 TailCallReturnAddrDelta,
713 assert(FrameIdx == MFI->getObjectIndexBegin() &&
714 "Slot for EBP register must be last in order to be found!");
719 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
720 /// stack pointer by a constant value.
722 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
723 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
724 const TargetInstrInfo &TII) {
725 bool isSub = NumBytes < 0;
726 uint64_t Offset = isSub ? -NumBytes : NumBytes;
727 unsigned Opc = isSub ?
728 getSUBriOpcode(Is64Bit, Offset) :
729 getADDriOpcode(Is64Bit, Offset);
730 uint64_t Chunk = (1LL << 31) - 1;
731 DebugLoc DL = MBB.findDebugLoc(MBBI);
734 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
736 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
739 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
744 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
746 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
747 unsigned StackPtr, uint64_t *NumBytes = NULL) {
748 if (MBBI == MBB.begin()) return;
750 MachineBasicBlock::iterator PI = prior(MBBI);
751 unsigned Opc = PI->getOpcode();
752 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
753 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
754 PI->getOperand(0).getReg() == StackPtr) {
756 *NumBytes += PI->getOperand(2).getImm();
758 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
759 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
760 PI->getOperand(0).getReg() == StackPtr) {
762 *NumBytes -= PI->getOperand(2).getImm();
767 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
769 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
770 MachineBasicBlock::iterator &MBBI,
771 unsigned StackPtr, uint64_t *NumBytes = NULL) {
772 // FIXME: THIS ISN'T RUN!!!
775 if (MBBI == MBB.end()) return;
777 MachineBasicBlock::iterator NI = llvm::next(MBBI);
778 if (NI == MBB.end()) return;
780 unsigned Opc = NI->getOpcode();
781 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
782 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
783 NI->getOperand(0).getReg() == StackPtr) {
785 *NumBytes -= NI->getOperand(2).getImm();
788 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
789 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
790 NI->getOperand(0).getReg() == StackPtr) {
792 *NumBytes += NI->getOperand(2).getImm();
798 /// mergeSPUpdates - Checks the instruction before/after the passed
799 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
800 /// stack adjustment is returned as a positive value for ADD and a negative for
802 static int mergeSPUpdates(MachineBasicBlock &MBB,
803 MachineBasicBlock::iterator &MBBI,
805 bool doMergeWithPrevious) {
806 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
807 (!doMergeWithPrevious && MBBI == MBB.end()))
810 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
811 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
812 unsigned Opc = PI->getOpcode();
815 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
816 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
817 PI->getOperand(0).getReg() == StackPtr){
818 Offset += PI->getOperand(2).getImm();
820 if (!doMergeWithPrevious) MBBI = NI;
821 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
822 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
823 PI->getOperand(0).getReg() == StackPtr) {
824 Offset -= PI->getOperand(2).getImm();
826 if (!doMergeWithPrevious) MBBI = NI;
832 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
834 unsigned FramePtr) const {
835 MachineFrameInfo *MFI = MF.getFrameInfo();
836 MachineModuleInfo &MMI = MF.getMMI();
838 // Add callee saved registers to move list.
839 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
840 if (CSI.empty()) return;
842 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
843 const TargetData *TD = MF.getTarget().getTargetData();
844 bool HasFP = hasFP(MF);
846 // Calculate amount of bytes used for return address storing.
848 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
849 TargetFrameInfo::StackGrowsUp ?
850 TD->getPointerSize() : -TD->getPointerSize());
852 // FIXME: This is dirty hack. The code itself is pretty mess right now.
853 // It should be rewritten from scratch and generalized sometimes.
855 // Determine maximum offset (minumum due to stack growth).
856 int64_t MaxOffset = 0;
857 for (std::vector<CalleeSavedInfo>::const_iterator
858 I = CSI.begin(), E = CSI.end(); I != E; ++I)
859 MaxOffset = std::min(MaxOffset,
860 MFI->getObjectOffset(I->getFrameIdx()));
862 // Calculate offsets.
863 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
864 for (std::vector<CalleeSavedInfo>::const_iterator
865 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
866 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
867 unsigned Reg = I->getReg();
868 Offset = MaxOffset - Offset + saveAreaOffset;
870 // Don't output a new machine move if we're re-saving the frame
871 // pointer. This happens when the PrologEpilogInserter has inserted an extra
872 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
873 // generates one when frame pointers are used. If we generate a "machine
874 // move" for this extra "PUSH", the linker will lose track of the fact that
875 // the frame pointer should have the value of the first "PUSH" when it's
878 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
879 // another bug. I.e., one where we generate a prolog like this:
887 // The immediate re-push of EBP is unnecessary. At the least, it's an
888 // optimization bug. EBP can be used as a scratch register in certain
889 // cases, but probably not when we have a frame pointer.
890 if (HasFP && FramePtr == Reg)
893 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
894 MachineLocation CSSrc(Reg);
895 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
899 /// emitPrologue - Push callee-saved registers onto the stack, which
900 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
901 /// space for local variables. Also emit labels used by the exception handler to
902 /// generate the exception handling frames.
903 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
904 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
905 MachineBasicBlock::iterator MBBI = MBB.begin();
906 MachineFrameInfo *MFI = MF.getFrameInfo();
907 const Function *Fn = MF.getFunction();
908 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
909 MachineModuleInfo &MMI = MF.getMMI();
910 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
911 bool needsFrameMoves = MMI.hasDebugInfo() ||
912 !Fn->doesNotThrow() || UnwindTablesMandatory;
913 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
914 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
915 bool HasFP = hasFP(MF);
918 // If we're forcing a stack realignment we can't rely on just the frame
919 // info, we need to know the ABI stack alignment as well in case we
920 // have a call out. Otherwise just make sure we have some alignment - we'll
921 // go with the minimum SlotSize.
922 if (ForceStackAlign) {
924 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
925 else if (MaxAlign < SlotSize)
929 // Add RETADDR move area to callee saved frame size.
930 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
931 if (TailCallReturnAddrDelta < 0)
932 X86FI->setCalleeSavedFrameSize(
933 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
935 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
936 // function, and use up to 128 bytes of stack space, don't have a frame
937 // pointer, calls, or dynamic alloca then we do not need to adjust the
938 // stack pointer (we fit in the Red Zone).
939 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
940 !needsStackRealignment(MF) &&
941 !MFI->hasVarSizedObjects() && // No dynamic alloca.
942 !MFI->adjustsStack() && // No calls.
943 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
944 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
945 if (HasFP) MinSize += SlotSize;
946 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
947 MFI->setStackSize(StackSize);
948 } else if (Subtarget->isTargetWin64()) {
949 // We need to always allocate 32 bytes as register spill area.
950 // FIXME: We might reuse these 32 bytes for leaf functions.
952 MFI->setStackSize(StackSize);
955 // Insert stack pointer adjustment for later moving of return addr. Only
956 // applies to tail call optimized functions where the callee argument stack
957 // size is bigger than the callers.
958 if (TailCallReturnAddrDelta < 0) {
960 BuildMI(MBB, MBBI, DL,
961 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
964 .addImm(-TailCallReturnAddrDelta);
965 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
968 // Mapping for machine moves:
970 // DST: VirtualFP AND
971 // SRC: VirtualFP => DW_CFA_def_cfa_offset
972 // ELSE => DW_CFA_def_cfa
974 // SRC: VirtualFP AND
975 // DST: Register => DW_CFA_def_cfa_register
978 // OFFSET < 0 => DW_CFA_offset_extended_sf
979 // REG < 64 => DW_CFA_offset + Reg
980 // ELSE => DW_CFA_offset_extended
982 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
983 const TargetData *TD = MF.getTarget().getTargetData();
984 uint64_t NumBytes = 0;
985 int stackGrowth = -TD->getPointerSize();
988 // Calculate required stack adjustment.
989 uint64_t FrameSize = StackSize - SlotSize;
990 if (needsStackRealignment(MF))
991 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
993 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
995 // Get the offset of the stack slot for the EBP register, which is
996 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
997 // Update the frame offset adjustment.
998 MFI->setOffsetAdjustment(-NumBytes);
1000 // Save EBP/RBP into the appropriate stack slot.
1001 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1002 .addReg(FramePtr, RegState::Kill);
1004 if (needsFrameMoves) {
1005 // Mark the place where EBP/RBP was saved.
1006 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1007 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel);
1009 // Define the current CFA rule to use the provided offset.
1011 MachineLocation SPDst(MachineLocation::VirtualFP);
1012 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
1013 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
1015 // FIXME: Verify & implement for FP
1016 MachineLocation SPDst(StackPtr);
1017 MachineLocation SPSrc(StackPtr, stackGrowth);
1018 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
1021 // Change the rule for the FramePtr to be an "offset" rule.
1022 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
1023 MachineLocation FPSrc(FramePtr);
1024 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1027 // Update EBP with the new base value...
1028 BuildMI(MBB, MBBI, DL,
1029 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1032 if (needsFrameMoves) {
1033 // Mark effective beginning of when frame pointer becomes valid.
1034 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1035 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel);
1037 // Define the current CFA to use the EBP/RBP register.
1038 MachineLocation FPDst(FramePtr);
1039 MachineLocation FPSrc(MachineLocation::VirtualFP);
1040 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1043 // Mark the FramePtr as live-in in every block except the entry.
1044 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
1046 I->addLiveIn(FramePtr);
1049 if (needsStackRealignment(MF)) {
1051 BuildMI(MBB, MBBI, DL,
1052 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1053 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1055 // The EFLAGS implicit def is dead.
1056 MI->getOperand(3).setIsDead();
1059 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1062 // Skip the callee-saved push instructions.
1063 bool PushedRegs = false;
1064 int StackOffset = 2 * stackGrowth;
1066 while (MBBI != MBB.end() &&
1067 (MBBI->getOpcode() == X86::PUSH32r ||
1068 MBBI->getOpcode() == X86::PUSH64r)) {
1072 if (!HasFP && needsFrameMoves) {
1073 // Mark callee-saved push instruction.
1074 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1075 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
1077 // Define the current CFA rule to use the provided offset.
1078 unsigned Ptr = StackSize ?
1079 MachineLocation::VirtualFP : StackPtr;
1080 MachineLocation SPDst(Ptr);
1081 MachineLocation SPSrc(Ptr, StackOffset);
1082 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1083 StackOffset += stackGrowth;
1087 DL = MBB.findDebugLoc(MBBI);
1089 // Adjust stack pointer: ESP -= numbytes.
1090 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1091 // Check, whether EAX is livein for this function.
1092 bool isEAXAlive = false;
1093 for (MachineRegisterInfo::livein_iterator
1094 II = MF.getRegInfo().livein_begin(),
1095 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1096 unsigned Reg = II->first;
1097 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1098 Reg == X86::AH || Reg == X86::AL);
1101 // Function prologue calls _alloca to probe the stack when allocating more
1102 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1103 // to ensure that the guard pages used by the OS virtual memory manager are
1104 // allocated in correct sequence.
1106 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1108 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1109 .addExternalSymbol("_alloca")
1110 .addReg(StackPtr, RegState::Define | RegState::Implicit)
1111 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1114 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1115 .addReg(X86::EAX, RegState::Kill);
1117 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1118 // allocated bytes for EAX.
1119 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1120 .addImm(NumBytes - 4);
1121 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1122 .addExternalSymbol("_alloca")
1123 .addReg(StackPtr, RegState::Define | RegState::Implicit)
1124 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1127 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1129 StackPtr, false, NumBytes - 4);
1130 MBB.insert(MBBI, MI);
1132 } else if (NumBytes) {
1133 // If there is an SUB32ri of ESP immediately before this instruction, merge
1134 // the two. This can be the case when tail call elimination is enabled and
1135 // the callee has more arguments then the caller.
1136 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1138 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1139 // instruction, merge the two instructions.
1140 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1143 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1146 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1147 // Mark end of stack pointer adjustment.
1148 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1149 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
1151 if (!HasFP && NumBytes) {
1152 // Define the current CFA rule to use the provided offset.
1154 MachineLocation SPDst(MachineLocation::VirtualFP);
1155 MachineLocation SPSrc(MachineLocation::VirtualFP,
1156 -StackSize + stackGrowth);
1157 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1159 // FIXME: Verify & implement for FP
1160 MachineLocation SPDst(StackPtr);
1161 MachineLocation SPSrc(StackPtr, stackGrowth);
1162 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1166 // Emit DWARF info specifying the offsets of the callee-saved registers.
1168 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
1172 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1173 MachineBasicBlock &MBB) const {
1174 const MachineFrameInfo *MFI = MF.getFrameInfo();
1175 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1176 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1177 unsigned RetOpcode = MBBI->getOpcode();
1178 DebugLoc DL = MBBI->getDebugLoc();
1180 switch (RetOpcode) {
1182 llvm_unreachable("Can only insert epilog into returning blocks");
1185 case X86::TCRETURNdi:
1186 case X86::TCRETURNri:
1187 case X86::TCRETURNmi:
1188 case X86::TCRETURNdi64:
1189 case X86::TCRETURNri64:
1190 case X86::TCRETURNmi64:
1191 case X86::EH_RETURN:
1192 case X86::EH_RETURN64:
1193 break; // These are ok
1196 // Get the number of bytes to allocate from the FrameInfo.
1197 uint64_t StackSize = MFI->getStackSize();
1198 uint64_t MaxAlign = MFI->getMaxAlignment();
1199 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1200 uint64_t NumBytes = 0;
1202 // If we're forcing a stack realignment we can't rely on just the frame
1203 // info, we need to know the ABI stack alignment as well in case we
1204 // have a call out. Otherwise just make sure we have some alignment - we'll
1205 // go with the minimum.
1206 if (ForceStackAlign) {
1207 if (MFI->hasCalls())
1208 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1210 MaxAlign = MaxAlign ? MaxAlign : 4;
1214 // Calculate required stack adjustment.
1215 uint64_t FrameSize = StackSize - SlotSize;
1216 if (needsStackRealignment(MF))
1217 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1219 NumBytes = FrameSize - CSSize;
1222 BuildMI(MBB, MBBI, DL,
1223 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1225 NumBytes = StackSize - CSSize;
1228 // Skip the callee-saved pop instructions.
1229 MachineBasicBlock::iterator LastCSPop = MBBI;
1230 while (MBBI != MBB.begin()) {
1231 MachineBasicBlock::iterator PI = prior(MBBI);
1232 unsigned Opc = PI->getOpcode();
1234 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1235 !PI->getDesc().isTerminator())
1241 DL = MBBI->getDebugLoc();
1243 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1244 // instruction, merge the two instructions.
1245 if (NumBytes || MFI->hasVarSizedObjects())
1246 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1248 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1249 // slot before popping them off! Same applies for the case, when stack was
1251 if (needsStackRealignment(MF)) {
1252 // We cannot use LEA here, because stack pointer was realigned. We need to
1253 // deallocate local frame back.
1255 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1256 MBBI = prior(LastCSPop);
1259 BuildMI(MBB, MBBI, DL,
1260 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1261 StackPtr).addReg(FramePtr);
1262 } else if (MFI->hasVarSizedObjects()) {
1264 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1266 addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1267 FramePtr, false, -CSSize);
1268 MBB.insert(MBBI, MI);
1270 BuildMI(MBB, MBBI, DL,
1271 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1274 } else if (NumBytes) {
1275 // Adjust stack pointer back: ESP += numbytes.
1276 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1279 // We're returning from function via eh_return.
1280 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1281 MBBI = prior(MBB.end());
1282 MachineOperand &DestAddr = MBBI->getOperand(0);
1283 assert(DestAddr.isReg() && "Offset should be in register!");
1284 BuildMI(MBB, MBBI, DL,
1285 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1286 StackPtr).addReg(DestAddr.getReg());
1287 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1288 RetOpcode == X86::TCRETURNmi ||
1289 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1290 RetOpcode == X86::TCRETURNmi64) {
1291 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1292 // Tail call return: adjust the stack pointer and jump to callee.
1293 MBBI = prior(MBB.end());
1294 MachineOperand &JumpTarget = MBBI->getOperand(0);
1295 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1296 assert(StackAdjust.isImm() && "Expecting immediate value.");
1298 // Adjust stack pointer.
1299 int StackAdj = StackAdjust.getImm();
1300 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1302 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1304 // Incoporate the retaddr area.
1305 Offset = StackAdj-MaxTCDelta;
1306 assert(Offset >= 0 && "Offset should never be negative");
1309 // Check for possible merge with preceeding ADD instruction.
1310 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1311 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1314 // Jump to label or value in register.
1315 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1316 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1317 ? X86::TAILJMPd : X86::TAILJMPd64)).
1318 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1319 JumpTarget.getTargetFlags());
1320 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1321 MachineInstrBuilder MIB =
1322 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1323 ? X86::TAILJMPm : X86::TAILJMPm64));
1324 for (unsigned i = 0; i != 5; ++i)
1325 MIB.addOperand(MBBI->getOperand(i));
1326 } else if (RetOpcode == X86::TCRETURNri64) {
1327 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1328 addReg(JumpTarget.getReg(), RegState::Kill);
1330 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1331 addReg(JumpTarget.getReg(), RegState::Kill);
1334 MachineInstr *NewMI = prior(MBBI);
1335 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1336 NewMI->addOperand(MBBI->getOperand(i));
1338 // Delete the pseudo instruction TCRETURN.
1340 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1341 (X86FI->getTCReturnAddrDelta() < 0)) {
1342 // Add the return addr area delta back since we are not tail calling.
1343 int delta = -1*X86FI->getTCReturnAddrDelta();
1344 MBBI = prior(MBB.end());
1346 // Check for possible merge with preceeding ADD instruction.
1347 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1348 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1352 unsigned X86RegisterInfo::getRARegister() const {
1353 return Is64Bit ? X86::RIP // Should have dwarf #16.
1354 : X86::EIP; // Should have dwarf #8.
1357 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1358 return hasFP(MF) ? FramePtr : StackPtr;
1362 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1363 // Calculate amount of bytes used for return address storing
1364 int stackGrowth = (Is64Bit ? -8 : -4);
1366 // Initial state of the frame pointer is esp+stackGrowth.
1367 MachineLocation Dst(MachineLocation::VirtualFP);
1368 MachineLocation Src(StackPtr, stackGrowth);
1369 Moves.push_back(MachineMove(0, Dst, Src));
1371 // Add return address to move list
1372 MachineLocation CSDst(StackPtr, stackGrowth);
1373 MachineLocation CSSrc(getRARegister());
1374 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1377 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1378 llvm_unreachable("What is the exception register");
1382 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1383 llvm_unreachable("What is the exception handler register");
1388 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1389 switch (VT.getSimpleVT().SimpleTy) {
1390 default: return Reg;
1395 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1397 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1399 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1401 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1407 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1409 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1411 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1413 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1415 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1417 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1419 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1421 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1423 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1425 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1427 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1429 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1431 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1433 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1435 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1437 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1443 default: return Reg;
1444 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1446 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1448 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1450 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1452 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1454 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1456 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1458 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1460 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1462 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1464 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1466 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1468 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1470 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1472 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1474 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1479 default: return Reg;
1480 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1482 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1484 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1486 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1488 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1490 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1492 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1494 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1496 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1498 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1500 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1502 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1504 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1506 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1508 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1510 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1515 default: return Reg;
1516 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1518 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1520 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1522 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1524 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1526 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1528 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1530 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1532 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1534 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1536 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1538 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1540 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1542 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1544 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1546 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1555 #include "X86GenRegisterInfo.inc"
1558 struct MSAH : public MachineFunctionPass {
1560 MSAH() : MachineFunctionPass(ID) {}
1562 virtual bool runOnMachineFunction(MachineFunction &MF) {
1563 const X86TargetMachine *TM =
1564 static_cast<const X86TargetMachine *>(&MF.getTarget());
1565 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
1566 MachineRegisterInfo &RI = MF.getRegInfo();
1567 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1568 unsigned StackAlignment = X86RI->getStackAlignment();
1570 // Be over-conservative: scan over all vreg defs and find whether vector
1571 // registers are used. If yes, there is a possibility that vector register
1572 // will be spilled and thus require dynamic stack realignment.
1573 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1574 RegNum < RI.getLastVirtReg(); ++RegNum)
1575 if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) {
1576 FuncInfo->setReserveFP(true);
1584 virtual const char *getPassName() const {
1585 return "X86 Maximal Stack Alignment Check";
1588 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1589 AU.setPreservesCFG();
1590 MachineFunctionPass::getAnalysisUsage(AU);
1598 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }