1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/CommandLine.h"
45 ForceStackAlign("force-align-stack",
46 cl::desc("Force align the stack to the minimum alignment"
47 " needed for the function."),
48 cl::init(false), cl::Hidden);
50 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
51 const TargetInstrInfo &tii)
52 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
53 X86::ADJCALLSTACKDOWN64 :
54 X86::ADJCALLSTACKDOWN32,
55 tm.getSubtarget<X86Subtarget>().is64Bit() ?
56 X86::ADJCALLSTACKUP64 :
57 X86::ADJCALLSTACKUP32),
59 // Cache some information.
60 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
61 Is64Bit = Subtarget->is64Bit();
62 IsWin64 = Subtarget->isTargetWin64();
63 StackAlign = TM.getFrameInfo()->getStackAlignment();
76 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
77 /// specific numbering, used in debug info and exception tables.
78 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
79 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
80 unsigned Flavour = DWARFFlavour::X86_64;
82 if (!Subtarget->is64Bit()) {
83 if (Subtarget->isTargetDarwin()) {
85 Flavour = DWARFFlavour::X86_32_DarwinEH;
87 Flavour = DWARFFlavour::X86_32_Generic;
88 } else if (Subtarget->isTargetCygMing()) {
89 // Unsupported by now, just quick fallback
90 Flavour = DWARFFlavour::X86_32_Generic;
92 Flavour = DWARFFlavour::X86_32_Generic;
96 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
99 /// getX86RegNum - This function maps LLVM register identifiers to their X86
100 /// specific numbering, which is used in various places encoding instructions.
101 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
103 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
104 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
105 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
106 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
107 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
109 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
111 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
113 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
116 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
118 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
120 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
122 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
124 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
126 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
128 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
130 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
133 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
134 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
135 return RegNo-X86::ST0;
137 case X86::XMM0: case X86::XMM8:
138 case X86::YMM0: case X86::YMM8: case X86::MM0:
140 case X86::XMM1: case X86::XMM9:
141 case X86::YMM1: case X86::YMM9: case X86::MM1:
143 case X86::XMM2: case X86::XMM10:
144 case X86::YMM2: case X86::YMM10: case X86::MM2:
146 case X86::XMM3: case X86::XMM11:
147 case X86::YMM3: case X86::YMM11: case X86::MM3:
149 case X86::XMM4: case X86::XMM12:
150 case X86::YMM4: case X86::YMM12: case X86::MM4:
152 case X86::XMM5: case X86::XMM13:
153 case X86::YMM5: case X86::YMM13: case X86::MM5:
155 case X86::XMM6: case X86::XMM14:
156 case X86::YMM6: case X86::YMM14: case X86::MM6:
158 case X86::XMM7: case X86::XMM15:
159 case X86::YMM7: case X86::YMM15: case X86::MM7:
162 case X86::ES: return 0;
163 case X86::CS: return 1;
164 case X86::SS: return 2;
165 case X86::DS: return 3;
166 case X86::FS: return 4;
167 case X86::GS: return 5;
169 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
170 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
171 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
172 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
173 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
174 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
175 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
176 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
178 // Pseudo index registers are equivalent to a "none"
179 // scaled index (See Intel Manual 2A, table 2-3)
185 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
186 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
191 const TargetRegisterClass *
192 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
193 const TargetRegisterClass *B,
194 unsigned SubIdx) const {
198 if (B == &X86::GR8RegClass) {
199 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
201 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
202 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
203 A == &X86::GR64_NOREXRegClass ||
204 A == &X86::GR64_NOSPRegClass ||
205 A == &X86::GR64_NOREX_NOSPRegClass)
206 return &X86::GR64_ABCDRegClass;
207 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
208 A == &X86::GR32_NOREXRegClass ||
209 A == &X86::GR32_NOSPRegClass)
210 return &X86::GR32_ABCDRegClass;
211 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
212 A == &X86::GR16_NOREXRegClass)
213 return &X86::GR16_ABCDRegClass;
214 } else if (B == &X86::GR8_NOREXRegClass) {
215 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
216 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
217 return &X86::GR64_NOREXRegClass;
218 else if (A == &X86::GR64_ABCDRegClass)
219 return &X86::GR64_ABCDRegClass;
220 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
221 A == &X86::GR32_NOSPRegClass)
222 return &X86::GR32_NOREXRegClass;
223 else if (A == &X86::GR32_ABCDRegClass)
224 return &X86::GR32_ABCDRegClass;
225 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
226 return &X86::GR16_NOREXRegClass;
227 else if (A == &X86::GR16_ABCDRegClass)
228 return &X86::GR16_ABCDRegClass;
231 case X86::sub_8bit_hi:
232 if (B == &X86::GR8_ABCD_HRegClass) {
233 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
234 A == &X86::GR64_NOREXRegClass ||
235 A == &X86::GR64_NOSPRegClass ||
236 A == &X86::GR64_NOREX_NOSPRegClass)
237 return &X86::GR64_ABCDRegClass;
238 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
239 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
240 return &X86::GR32_ABCDRegClass;
241 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
242 A == &X86::GR16_NOREXRegClass)
243 return &X86::GR16_ABCDRegClass;
247 if (B == &X86::GR16RegClass) {
248 if (A->getSize() == 4 || A->getSize() == 8)
250 } else if (B == &X86::GR16_ABCDRegClass) {
251 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
252 A == &X86::GR64_NOREXRegClass ||
253 A == &X86::GR64_NOSPRegClass ||
254 A == &X86::GR64_NOREX_NOSPRegClass)
255 return &X86::GR64_ABCDRegClass;
256 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
257 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
258 return &X86::GR32_ABCDRegClass;
259 } else if (B == &X86::GR16_NOREXRegClass) {
260 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
261 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
262 return &X86::GR64_NOREXRegClass;
263 else if (A == &X86::GR64_ABCDRegClass)
264 return &X86::GR64_ABCDRegClass;
265 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
266 A == &X86::GR32_NOSPRegClass)
267 return &X86::GR32_NOREXRegClass;
268 else if (A == &X86::GR32_ABCDRegClass)
269 return &X86::GR64_ABCDRegClass;
273 if (B == &X86::GR32RegClass) {
274 if (A->getSize() == 8)
276 } else if (B == &X86::GR32_NOSPRegClass) {
277 if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
278 return &X86::GR64_NOSPRegClass;
279 if (A->getSize() == 8)
280 return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
281 } else if (B == &X86::GR32_ABCDRegClass) {
282 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
283 A == &X86::GR64_NOREXRegClass ||
284 A == &X86::GR64_NOSPRegClass ||
285 A == &X86::GR64_NOREX_NOSPRegClass)
286 return &X86::GR64_ABCDRegClass;
287 } else if (B == &X86::GR32_NOREXRegClass) {
288 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
289 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
290 return &X86::GR64_NOREXRegClass;
291 else if (A == &X86::GR64_ABCDRegClass)
292 return &X86::GR64_ABCDRegClass;
296 if (B == &X86::FR32RegClass)
300 if (B == &X86::FR64RegClass)
304 if (B == &X86::VR128RegClass)
311 const TargetRegisterClass *
312 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
314 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
315 case 0: // Normal GPRs.
316 if (TM.getSubtarget<X86Subtarget>().is64Bit())
317 return &X86::GR64RegClass;
318 return &X86::GR32RegClass;
319 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
320 if (TM.getSubtarget<X86Subtarget>().is64Bit())
321 return &X86::GR64_NOSPRegClass;
322 return &X86::GR32_NOSPRegClass;
326 const TargetRegisterClass *
327 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
328 if (RC == &X86::CCRRegClass) {
330 return &X86::GR64RegClass;
332 return &X86::GR32RegClass;
338 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
339 bool callsEHReturn = false;
340 bool ghcCall = false;
343 callsEHReturn = MF->getMMI().callsEHReturn();
344 const Function *F = MF->getFunction();
345 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
348 static const unsigned GhcCalleeSavedRegs[] = {
352 static const unsigned CalleeSavedRegs32Bit[] = {
353 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
356 static const unsigned CalleeSavedRegs32EHRet[] = {
357 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
360 static const unsigned CalleeSavedRegs64Bit[] = {
361 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
364 static const unsigned CalleeSavedRegs64EHRet[] = {
365 X86::RAX, X86::RDX, X86::RBX, X86::R12,
366 X86::R13, X86::R14, X86::R15, X86::RBP, 0
369 static const unsigned CalleeSavedRegsWin64[] = {
370 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
371 X86::R12, X86::R13, X86::R14, X86::R15,
372 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
373 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
374 X86::XMM14, X86::XMM15, 0
378 return GhcCalleeSavedRegs;
379 } else if (Is64Bit) {
381 return CalleeSavedRegsWin64;
383 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
385 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
389 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
390 BitVector Reserved(getNumRegs());
391 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
393 // Set the stack-pointer register and its aliases as reserved.
394 Reserved.set(X86::RSP);
395 Reserved.set(X86::ESP);
396 Reserved.set(X86::SP);
397 Reserved.set(X86::SPL);
399 // Set the instruction pointer register and its aliases as reserved.
400 Reserved.set(X86::RIP);
401 Reserved.set(X86::EIP);
402 Reserved.set(X86::IP);
404 // Set the frame-pointer register and its aliases as reserved if needed.
405 if (TFI->hasFP(MF)) {
406 Reserved.set(X86::RBP);
407 Reserved.set(X86::EBP);
408 Reserved.set(X86::BP);
409 Reserved.set(X86::BPL);
412 // Mark the x87 stack registers as reserved, since they don't behave normally
413 // with respect to liveness. We don't fully model the effects of x87 stack
414 // pushes and pops after stackification.
415 Reserved.set(X86::ST0);
416 Reserved.set(X86::ST1);
417 Reserved.set(X86::ST2);
418 Reserved.set(X86::ST3);
419 Reserved.set(X86::ST4);
420 Reserved.set(X86::ST5);
421 Reserved.set(X86::ST6);
422 Reserved.set(X86::ST7);
426 //===----------------------------------------------------------------------===//
427 // Stack Frame Processing methods
428 //===----------------------------------------------------------------------===//
430 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
431 const MachineFrameInfo *MFI = MF.getFrameInfo();
432 return (RealignStack &&
433 !MFI->hasVarSizedObjects());
436 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
437 const MachineFrameInfo *MFI = MF.getFrameInfo();
438 const Function *F = MF.getFunction();
439 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
440 F->hasFnAttr(Attribute::StackAlignment));
442 // FIXME: Currently we don't support stack realignment for functions with
443 // variable-sized allocas.
444 // FIXME: It's more complicated than this...
445 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
447 "Stack realignment in presense of dynamic allocas is not supported");
449 // If we've requested that we force align the stack do so now.
451 return canRealignStack(MF);
453 return requiresRealignment && canRealignStack(MF);
456 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
457 unsigned Reg, int &FrameIdx) const {
458 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
460 if (Reg == FramePtr && TFI->hasFP(MF)) {
461 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
467 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
470 return X86::SUB64ri8;
471 return X86::SUB64ri32;
474 return X86::SUB32ri8;
479 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
482 return X86::ADD64ri8;
483 return X86::ADD64ri32;
486 return X86::ADD32ri8;
491 void X86RegisterInfo::
492 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
493 MachineBasicBlock::iterator I) const {
494 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
496 if (!TFI->hasReservedCallFrame(MF)) {
497 // If the stack pointer can be changed after prologue, turn the
498 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
499 // adjcallstackdown instruction into 'add ESP, <amt>'
500 // TODO: consider using push / pop instead of sub + store / add
501 MachineInstr *Old = I;
502 uint64_t Amount = Old->getOperand(0).getImm();
504 // We need to keep the stack aligned properly. To do this, we round the
505 // amount of space needed for the outgoing arguments up to the next
506 // alignment boundary.
507 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
509 MachineInstr *New = 0;
510 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
511 New = BuildMI(MF, Old->getDebugLoc(),
512 TII.get(getSUBriOpcode(Is64Bit, Amount)),
517 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
519 // Factor out the amount the callee already popped.
520 uint64_t CalleeAmt = Old->getOperand(1).getImm();
524 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
525 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
532 // The EFLAGS implicit def is dead.
533 New->getOperand(3).setIsDead();
535 // Replace the pseudo instruction with a new instruction.
539 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
540 // If we are performing frame pointer elimination and if the callee pops
541 // something off the stack pointer, add it back. We do this until we have
542 // more advanced stack pointer tracking ability.
543 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
544 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
545 MachineInstr *Old = I;
547 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
552 // The EFLAGS implicit def is dead.
553 New->getOperand(3).setIsDead();
562 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
563 int SPAdj, RegScavenger *RS) const{
564 assert(SPAdj == 0 && "Unexpected");
567 MachineInstr &MI = *II;
568 MachineFunction &MF = *MI.getParent()->getParent();
569 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
571 while (!MI.getOperand(i).isFI()) {
573 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
576 int FrameIndex = MI.getOperand(i).getIndex();
579 unsigned Opc = MI.getOpcode();
580 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
581 if (needsStackRealignment(MF))
582 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
586 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
588 // This must be part of a four operand memory reference. Replace the
589 // FrameIndex with base register with EBP. Add an offset to the offset.
590 MI.getOperand(i).ChangeToRegister(BasePtr, false);
592 // Now add the frame object offset to the offset from EBP.
595 // Tail call jmp happens after FP is popped.
596 const MachineFrameInfo *MFI = MF.getFrameInfo();
597 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
599 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
601 if (MI.getOperand(i+3).isImm()) {
602 // Offset is a 32-bit integer.
603 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
604 MI.getOperand(i + 3).ChangeToImmediate(Offset);
606 // Offset is symbolic. This is extremely rare.
607 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
608 MI.getOperand(i+3).setOffset(Offset);
612 unsigned X86RegisterInfo::getRARegister() const {
613 return Is64Bit ? X86::RIP // Should have dwarf #16.
614 : X86::EIP; // Should have dwarf #8.
617 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
618 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
619 return TFI->hasFP(MF) ? FramePtr : StackPtr;
622 unsigned X86RegisterInfo::getEHExceptionRegister() const {
623 llvm_unreachable("What is the exception register");
627 unsigned X86RegisterInfo::getEHHandlerRegister() const {
628 llvm_unreachable("What is the exception handler register");
633 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
634 switch (VT.getSimpleVT().SimpleTy) {
640 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
642 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
644 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
646 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
652 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
654 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
656 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
658 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
660 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
662 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
664 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
666 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
668 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
670 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
672 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
674 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
676 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
678 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
680 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
682 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
689 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
691 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
693 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
695 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
697 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
699 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
701 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
703 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
705 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
707 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
709 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
711 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
713 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
715 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
717 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
719 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
725 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
727 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
729 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
731 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
733 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
735 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
737 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
739 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
741 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
743 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
745 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
747 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
749 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
751 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
753 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
755 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
761 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
763 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
765 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
767 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
769 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
771 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
773 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
775 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
777 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
779 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
781 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
783 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
785 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
787 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
789 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
791 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
800 #include "X86GenRegisterInfo.inc"
803 struct MSAH : public MachineFunctionPass {
805 MSAH() : MachineFunctionPass(ID) {}
807 virtual bool runOnMachineFunction(MachineFunction &MF) {
808 const X86TargetMachine *TM =
809 static_cast<const X86TargetMachine *>(&MF.getTarget());
810 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
811 MachineRegisterInfo &RI = MF.getRegInfo();
812 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
813 unsigned StackAlignment = X86RI->getStackAlignment();
815 // Be over-conservative: scan over all vreg defs and find whether vector
816 // registers are used. If yes, there is a possibility that vector register
817 // will be spilled and thus require dynamic stack realignment.
818 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
819 RegNum < RI.getLastVirtReg(); ++RegNum)
820 if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) {
821 FuncInfo->setReserveFP(true);
829 virtual const char *getPassName() const {
830 return "X86 Maximal Stack Alignment Check";
833 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
834 AU.setPreservesCFG();
835 MachineFunctionPass::getAnalysisUsage(AU);
843 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }