1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
41 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
42 const TargetInstrInfo &tii)
43 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
45 // Cache some information.
46 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
47 Is64Bit = Subtarget->is64Bit();
48 StackAlign = TM.getFrameInfo()->getStackAlignment();
60 // getDwarfRegNum - This function maps LLVM register identifiers to the
61 // Dwarf specific numbering, used in debug info and exception tables.
63 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
64 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
65 unsigned Flavour = DWARFFlavour::X86_64;
66 if (!Subtarget->is64Bit()) {
67 if (Subtarget->isTargetDarwin()) {
69 Flavour = DWARFFlavour::X86_32_DarwinEH;
71 Flavour = DWARFFlavour::X86_32_Generic;
72 } else if (Subtarget->isTargetCygMing()) {
73 // Unsupported by now, just quick fallback
74 Flavour = DWARFFlavour::X86_32_Generic;
76 Flavour = DWARFFlavour::X86_32_Generic;
80 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
83 // getX86RegNum - This function maps LLVM register identifiers to their X86
84 // specific numbering, which is used in various places encoding instructions.
86 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const {
88 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
89 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
90 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
91 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
92 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
94 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
96 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
98 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
101 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
103 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
105 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
107 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
109 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
111 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
113 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
115 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
118 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
119 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
120 return RegNo-X86::ST0;
122 case X86::XMM0: case X86::XMM8: case X86::MM0:
124 case X86::XMM1: case X86::XMM9: case X86::MM1:
126 case X86::XMM2: case X86::XMM10: case X86::MM2:
128 case X86::XMM3: case X86::XMM11: case X86::MM3:
130 case X86::XMM4: case X86::XMM12: case X86::MM4:
132 case X86::XMM5: case X86::XMM13: case X86::MM5:
134 case X86::XMM6: case X86::XMM14: case X86::MM6:
136 case X86::XMM7: case X86::XMM15: case X86::MM7:
140 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
141 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
146 const TargetRegisterClass *
147 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
148 if (RC == &X86::CCRRegClass)
150 return &X86::GR64RegClass;
152 return &X86::GR32RegClass;
156 void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
157 MachineBasicBlock::iterator I,
159 const MachineInstr *Orig) const {
160 // MOV32r0 etc. are implemented with xor which clobbers condition code.
161 // Re-materialize them as movri instructions to avoid side effects.
162 switch (Orig->getOpcode()) {
164 BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
167 BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
170 BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
173 BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
176 MachineInstr *MI = Orig->clone();
177 MI->getOperand(0).setReg(DestReg);
185 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
186 static const unsigned CalleeSavedRegs32Bit[] = {
187 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
190 static const unsigned CalleeSavedRegs32EHRet[] = {
191 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
194 static const unsigned CalleeSavedRegs64Bit[] = {
195 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
199 return CalleeSavedRegs64Bit;
202 MachineFrameInfo *MFI = MF->getFrameInfo();
203 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
204 if (MMI && MMI->callsEHReturn())
205 return CalleeSavedRegs32EHRet;
207 return CalleeSavedRegs32Bit;
211 const TargetRegisterClass* const*
212 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
213 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
214 &X86::GR32RegClass, &X86::GR32RegClass,
215 &X86::GR32RegClass, &X86::GR32RegClass, 0
217 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
218 &X86::GR32RegClass, &X86::GR32RegClass,
219 &X86::GR32RegClass, &X86::GR32RegClass,
220 &X86::GR32RegClass, &X86::GR32RegClass, 0
222 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
223 &X86::GR64RegClass, &X86::GR64RegClass,
224 &X86::GR64RegClass, &X86::GR64RegClass,
225 &X86::GR64RegClass, &X86::GR64RegClass, 0
229 return CalleeSavedRegClasses64Bit;
232 MachineFrameInfo *MFI = MF->getFrameInfo();
233 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
234 if (MMI && MMI->callsEHReturn())
235 return CalleeSavedRegClasses32EHRet;
237 return CalleeSavedRegClasses32Bit;
242 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
243 BitVector Reserved(getNumRegs());
244 Reserved.set(X86::RSP);
245 Reserved.set(X86::ESP);
246 Reserved.set(X86::SP);
247 Reserved.set(X86::SPL);
249 Reserved.set(X86::RBP);
250 Reserved.set(X86::EBP);
251 Reserved.set(X86::BP);
252 Reserved.set(X86::BPL);
257 //===----------------------------------------------------------------------===//
258 // Stack Frame Processing methods
259 //===----------------------------------------------------------------------===//
261 // hasFP - Return true if the specified function should have a dedicated frame
262 // pointer register. This is true if the function has variable sized allocas or
263 // if frame pointer elimination is disabled.
265 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
266 MachineFrameInfo *MFI = MF.getFrameInfo();
267 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
269 return (NoFramePointerElim ||
270 MFI->hasVarSizedObjects() ||
271 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
272 (MMI && MMI->callsUnwindInit()));
275 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
276 return !MF.getFrameInfo()->hasVarSizedObjects();
279 void X86RegisterInfo::
280 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
281 MachineBasicBlock::iterator I) const {
282 if (!hasReservedCallFrame(MF)) {
283 // If the stack pointer can be changed after prologue, turn the
284 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
285 // adjcallstackdown instruction into 'add ESP, <amt>'
286 // TODO: consider using push / pop instead of sub + store / add
287 MachineInstr *Old = I;
288 uint64_t Amount = Old->getOperand(0).getImm();
290 // We need to keep the stack aligned properly. To do this, we round the
291 // amount of space needed for the outgoing arguments up to the next
292 // alignment boundary.
293 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
295 MachineInstr *New = 0;
296 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
297 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
298 .addReg(StackPtr).addImm(Amount);
300 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
301 // factor out the amount the callee already popped.
302 uint64_t CalleeAmt = Old->getOperand(1).getImm();
305 unsigned Opc = (Amount < 128) ?
306 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
307 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
308 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
312 // Replace the pseudo instruction with a new instruction...
313 if (New) MBB.insert(I, New);
315 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
316 // If we are performing frame pointer elimination and if the callee pops
317 // something off the stack pointer, add it back. We do this until we have
318 // more advanced stack pointer tracking ability.
319 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
320 unsigned Opc = (CalleeAmt < 128) ?
321 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
322 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
324 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
332 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
333 int SPAdj, RegScavenger *RS) const{
334 assert(SPAdj == 0 && "Unexpected");
337 MachineInstr &MI = *II;
338 MachineFunction &MF = *MI.getParent()->getParent();
339 while (!MI.getOperand(i).isFrameIndex()) {
341 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
344 int FrameIndex = MI.getOperand(i).getIndex();
345 // This must be part of a four operand memory reference. Replace the
346 // FrameIndex with base register with EBP. Add an offset to the offset.
347 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
349 // Now add the frame object offset to the offset from EBP.
350 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
351 MI.getOperand(i+3).getImm()+SlotSize;
354 Offset += MF.getFrameInfo()->getStackSize();
356 Offset += SlotSize; // Skip the saved EBP
357 // Skip the RETADDR move area
358 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
359 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
360 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
363 MI.getOperand(i+3).ChangeToImmediate(Offset);
367 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
368 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
369 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
370 if (TailCallReturnAddrDelta < 0) {
371 // create RETURNADDR area
381 CreateFixedObject(-TailCallReturnAddrDelta,
382 (-1*SlotSize)+TailCallReturnAddrDelta);
385 assert((TailCallReturnAddrDelta <= 0) &&
386 "The Delta should always be zero or negative");
387 // Create a frame entry for the EBP register that must be saved.
388 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
390 TailCallReturnAddrDelta);
391 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
392 "Slot for EBP register must be last in order to be found!");
396 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
397 /// stack pointer by a constant value.
399 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
400 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
401 const TargetInstrInfo &TII) {
402 bool isSub = NumBytes < 0;
403 uint64_t Offset = isSub ? -NumBytes : NumBytes;
406 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
407 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
409 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
410 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
411 uint64_t Chunk = (1LL << 31) - 1;
414 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
415 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
420 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
422 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
423 unsigned StackPtr, uint64_t *NumBytes = NULL) {
424 if (MBBI == MBB.begin()) return;
426 MachineBasicBlock::iterator PI = prior(MBBI);
427 unsigned Opc = PI->getOpcode();
428 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
429 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
430 PI->getOperand(0).getReg() == StackPtr) {
432 *NumBytes += PI->getOperand(2).getImm();
434 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
435 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
436 PI->getOperand(0).getReg() == StackPtr) {
438 *NumBytes -= PI->getOperand(2).getImm();
443 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
445 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
446 MachineBasicBlock::iterator &MBBI,
447 unsigned StackPtr, uint64_t *NumBytes = NULL) {
450 if (MBBI == MBB.end()) return;
452 MachineBasicBlock::iterator NI = next(MBBI);
453 if (NI == MBB.end()) return;
455 unsigned Opc = NI->getOpcode();
456 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
457 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
458 NI->getOperand(0).getReg() == StackPtr) {
460 *NumBytes -= NI->getOperand(2).getImm();
463 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
464 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
465 NI->getOperand(0).getReg() == StackPtr) {
467 *NumBytes += NI->getOperand(2).getImm();
473 /// mergeSPUpdates - Checks the instruction before/after the passed
474 /// instruction. If it is an ADD/SUB instruction it is deleted
475 /// argument and the stack adjustment is returned as a positive value for ADD
476 /// and a negative for SUB.
477 static int mergeSPUpdates(MachineBasicBlock &MBB,
478 MachineBasicBlock::iterator &MBBI,
480 bool doMergeWithPrevious) {
482 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
483 (!doMergeWithPrevious && MBBI == MBB.end()))
488 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
489 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
490 unsigned Opc = PI->getOpcode();
491 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
492 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
493 PI->getOperand(0).getReg() == StackPtr){
494 Offset += PI->getOperand(2).getImm();
496 if (!doMergeWithPrevious) MBBI = NI;
497 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
498 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
499 PI->getOperand(0).getReg() == StackPtr) {
500 Offset -= PI->getOperand(2).getImm();
502 if (!doMergeWithPrevious) MBBI = NI;
508 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
509 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
510 MachineFrameInfo *MFI = MF.getFrameInfo();
511 const Function* Fn = MF.getFunction();
512 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
513 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
514 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
515 MachineBasicBlock::iterator MBBI = MBB.begin();
517 // Prepare for frame info.
518 unsigned FrameLabelId = 0;
520 // Get the number of bytes to allocate from the FrameInfo.
521 uint64_t StackSize = MFI->getStackSize();
522 // Add RETADDR move area to callee saved frame size.
523 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
524 if (TailCallReturnAddrDelta < 0)
525 X86FI->setCalleeSavedFrameSize(
526 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
527 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
529 // Insert stack pointer adjustment for later moving of return addr. Only
530 // applies to tail call optimized functions where the callee argument stack
531 // size is bigger than the callers.
532 if (TailCallReturnAddrDelta < 0) {
533 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
534 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
538 // Get the offset of the stack slot for the EBP register... which is
539 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
540 // Update the frame offset adjustment.
541 MFI->setOffsetAdjustment(SlotSize-NumBytes);
543 // Save EBP into the appropriate stack slot...
544 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
546 NumBytes -= SlotSize;
548 if (MMI && MMI->needsFrameInfo()) {
549 // Mark effective beginning of when frame pointer becomes valid.
550 FrameLabelId = MMI->NextLabelID();
551 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
554 // Update EBP with the new base value...
555 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
559 unsigned ReadyLabelId = 0;
560 if (MMI && MMI->needsFrameInfo()) {
561 // Mark effective beginning of when frame pointer is ready.
562 ReadyLabelId = MMI->NextLabelID();
563 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
566 // Skip the callee-saved push instructions.
567 while (MBBI != MBB.end() &&
568 (MBBI->getOpcode() == X86::PUSH32r ||
569 MBBI->getOpcode() == X86::PUSH64r))
572 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
573 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
574 // Check, whether EAX is livein for this function
575 bool isEAXAlive = false;
576 for (MachineRegisterInfo::livein_iterator
577 II = MF.getRegInfo().livein_begin(),
578 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
579 unsigned Reg = II->first;
580 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
581 Reg == X86::AH || Reg == X86::AL);
584 // Function prologue calls _alloca to probe the stack when allocating
585 // more than 4k bytes in one go. Touching the stack at 4K increments is
586 // necessary to ensure that the guard pages used by the OS virtual memory
587 // manager are allocated in correct sequence.
589 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
590 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
591 .addExternalSymbol("_alloca");
594 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
595 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
596 // allocated bytes for EAX.
597 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
598 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
599 .addExternalSymbol("_alloca");
601 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
602 StackPtr, NumBytes-4);
603 MBB.insert(MBBI, MI);
606 // If there is an SUB32ri of ESP immediately before this instruction,
607 // merge the two. This can be the case when tail call elimination is
608 // enabled and the callee has more arguments then the caller.
609 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
610 // If there is an ADD32ri or SUB32ri of ESP immediately after this
611 // instruction, merge the two instructions.
612 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
615 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
619 if (MMI && MMI->needsFrameInfo()) {
620 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
621 const TargetData *TD = MF.getTarget().getTargetData();
623 // Calculate amount of bytes used for return address storing
625 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
626 TargetFrameInfo::StackGrowsUp ?
627 TD->getPointerSize() : -TD->getPointerSize());
630 // Show update of SP.
633 MachineLocation SPDst(MachineLocation::VirtualFP);
634 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
635 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
637 MachineLocation SPDst(MachineLocation::VirtualFP);
638 MachineLocation SPSrc(MachineLocation::VirtualFP,
639 -StackSize+stackGrowth);
640 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
643 //FIXME: Verify & implement for FP
644 MachineLocation SPDst(StackPtr);
645 MachineLocation SPSrc(StackPtr, stackGrowth);
646 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
649 // Add callee saved registers to move list.
650 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
652 // FIXME: This is dirty hack. The code itself is pretty mess right now.
653 // It should be rewritten from scratch and generalized sometimes.
655 // Determine maximum offset (minumum due to stack growth)
656 int64_t MaxOffset = 0;
657 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
658 MaxOffset = std::min(MaxOffset,
659 MFI->getObjectOffset(CSI[I].getFrameIdx()));
662 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
663 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
664 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
665 unsigned Reg = CSI[I].getReg();
666 Offset = (MaxOffset-Offset+saveAreaOffset);
667 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
668 MachineLocation CSSrc(Reg);
669 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
674 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
675 MachineLocation FPSrc(FramePtr);
676 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
679 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
680 MachineLocation FPSrc(MachineLocation::VirtualFP);
681 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
684 // If it's main() on Cygwin\Mingw32 we should align stack as well
685 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
686 Subtarget->isTargetCygMing()) {
687 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
688 .addReg(X86::ESP).addImm(-StackAlign);
691 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
692 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
696 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
697 MachineBasicBlock &MBB) const {
698 const MachineFrameInfo *MFI = MF.getFrameInfo();
699 const Function* Fn = MF.getFunction();
700 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
701 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
702 MachineBasicBlock::iterator MBBI = prior(MBB.end());
703 unsigned RetOpcode = MBBI->getOpcode();
708 case X86::TCRETURNdi:
709 case X86::TCRETURNri:
710 case X86::TCRETURNri64:
711 case X86::TCRETURNdi64:
715 case X86::TAILJMPm: break; // These are ok
717 assert(0 && "Can only insert epilog into returning blocks");
720 // Get the number of bytes to allocate from the FrameInfo
721 uint64_t StackSize = MFI->getStackSize();
722 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
723 uint64_t NumBytes = StackSize - CSSize;
727 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
728 NumBytes -= SlotSize;
731 // Skip the callee-saved pop instructions.
732 while (MBBI != MBB.begin()) {
733 MachineBasicBlock::iterator PI = prior(MBBI);
734 unsigned Opc = PI->getOpcode();
735 if (Opc != X86::POP32r && Opc != X86::POP64r &&
736 !PI->getDesc().isTerminator())
741 // If there is an ADD32ri or SUB32ri of ESP immediately before this
742 // instruction, merge the two instructions.
743 if (NumBytes || MFI->hasVarSizedObjects())
744 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
746 // If dynamic alloca is used, then reset esp to point to the last callee-saved
747 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
748 // aligned stack in the prologue, - revert stack changes back. Note: we're
749 // assuming, that frame pointer was forced for main()
750 if (MFI->hasVarSizedObjects() ||
751 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
752 Subtarget->isTargetCygMing())) {
753 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
755 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
757 MBB.insert(MBBI, MI);
759 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
765 // adjust stack pointer back: ESP += numbytes
767 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
769 // We're returning from function via eh_return.
770 if (RetOpcode == X86::EH_RETURN) {
771 MBBI = prior(MBB.end());
772 MachineOperand &DestAddr = MBBI->getOperand(0);
773 assert(DestAddr.isRegister() && "Offset should be in register!");
774 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
775 addReg(DestAddr.getReg());
776 // Tail call return: adjust the stack pointer and jump to callee
777 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
778 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
779 MBBI = prior(MBB.end());
780 MachineOperand &JumpTarget = MBBI->getOperand(0);
781 MachineOperand &StackAdjust = MBBI->getOperand(1);
782 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
784 // Adjust stack pointer.
785 int StackAdj = StackAdjust.getImm();
786 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
788 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
789 // Incoporate the retaddr area.
790 Offset = StackAdj-MaxTCDelta;
791 assert(Offset >= 0 && "Offset should never be negative");
793 // Check for possible merge with preceeding ADD instruction.
794 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
795 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
797 // Jump to label or value in register.
798 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
799 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
800 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
801 else if (RetOpcode== X86::TCRETURNri64) {
802 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
804 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
805 // Delete the pseudo instruction TCRETURN.
807 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
808 (X86FI->getTCReturnAddrDelta() < 0)) {
809 // Add the return addr area delta back since we are not tail calling.
810 int delta = -1*X86FI->getTCReturnAddrDelta();
811 MBBI = prior(MBB.end());
812 // Check for possible merge with preceeding ADD instruction.
813 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
814 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
818 unsigned X86RegisterInfo::getRARegister() const {
820 return X86::RIP; // Should have dwarf #16
822 return X86::EIP; // Should have dwarf #8
825 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
826 return hasFP(MF) ? FramePtr : StackPtr;
830 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
831 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
833 return Offset + MF.getFrameInfo()->getStackSize();
835 Offset += SlotSize; // Skip the saved EBP
836 // Skip the RETADDR move area
837 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
838 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
839 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
843 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
845 // Calculate amount of bytes used for return address storing
846 int stackGrowth = (Is64Bit ? -8 : -4);
848 // Initial state of the frame pointer is esp+4.
849 MachineLocation Dst(MachineLocation::VirtualFP);
850 MachineLocation Src(StackPtr, stackGrowth);
851 Moves.push_back(MachineMove(0, Dst, Src));
853 // Add return address to move list
854 MachineLocation CSDst(StackPtr, stackGrowth);
855 MachineLocation CSSrc(getRARegister());
856 Moves.push_back(MachineMove(0, CSDst, CSSrc));
859 unsigned X86RegisterInfo::getEHExceptionRegister() const {
860 assert(0 && "What is the exception register");
864 unsigned X86RegisterInfo::getEHHandlerRegister() const {
865 assert(0 && "What is the exception handler register");
870 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
877 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
879 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
881 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
883 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
889 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
891 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
893 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
895 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
897 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
899 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
901 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
903 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
905 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
907 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
909 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
911 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
913 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
915 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
917 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
919 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
926 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
928 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
930 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
932 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
934 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
936 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
938 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
940 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
942 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
944 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
946 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
948 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
950 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
952 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
954 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
956 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
962 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
964 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
966 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
968 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
970 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
972 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
974 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
976 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
978 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
980 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
982 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
984 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
986 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
988 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
990 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
992 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
998 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1000 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1002 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1004 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1006 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1008 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1010 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1012 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1014 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1016 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1018 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1020 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1022 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1024 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1026 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1028 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1037 #include "X86GenRegisterInfo.inc"