1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
48 ForceStackAlign("force-align-stack",
49 cl::desc("Force align the stack to the minimum alignment"
50 " needed for the function."),
51 cl::init(false), cl::Hidden);
53 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
54 const TargetInstrInfo &tii)
55 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
56 ? X86::RIP : X86::EIP,
57 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
58 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
60 X86_MC::InitLLVM2SEHRegisterMapping(this);
62 // Cache some information.
63 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
64 Is64Bit = Subtarget->is64Bit();
65 IsWin64 = Subtarget->isTargetWin64();
78 /// getCompactUnwindRegNum - This function maps the register to the number for
79 /// compact unwind encoding. Return -1 if the register isn't valid.
80 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
81 switch (getLLVMRegNum(RegNum, isEH)) {
82 case X86::EBX: case X86::RBX: return 1;
83 case X86::ECX: case X86::R12: return 2;
84 case X86::EDX: case X86::R13: return 3;
85 case X86::EDI: case X86::R14: return 4;
86 case X86::ESI: case X86::R15: return 5;
87 case X86::EBP: case X86::RBP: return 6;
94 X86RegisterInfo::getSEHRegNum(unsigned i) const {
95 int reg = X86_MC::getX86RegNum(i);
97 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
98 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
99 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
100 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
101 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
102 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
103 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
104 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
105 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
106 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
107 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
108 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
114 const TargetRegisterClass *
115 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
116 unsigned Idx) const {
117 // The sub_8bit sub-register index is more constrained in 32-bit mode.
118 // It behaves just like the sub_8bit_hi index.
119 if (!Is64Bit && Idx == X86::sub_8bit)
120 Idx = X86::sub_8bit_hi;
122 // Forward to TableGen's default version.
123 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
126 const TargetRegisterClass *
127 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
128 const TargetRegisterClass *B,
129 unsigned SubIdx) const {
130 // The sub_8bit sub-register index is more constrained in 32-bit mode.
131 if (!Is64Bit && SubIdx == X86::sub_8bit) {
132 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
136 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
139 const TargetRegisterClass*
140 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
141 // Don't allow super-classes of GR8_NOREX. This class is only used after
142 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
143 // to the full GR8 register class in 64-bit mode, so we cannot allow the
144 // reigster class inflation.
146 // The GR8_NOREX class is always used in a way that won't be constrained to a
147 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
149 if (RC == X86::GR8_NOREXRegisterClass)
152 const TargetRegisterClass *Super = RC;
153 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
155 switch (Super->getID()) {
156 case X86::GR8RegClassID:
157 case X86::GR16RegClassID:
158 case X86::GR32RegClassID:
159 case X86::GR64RegClassID:
160 case X86::FR32RegClassID:
161 case X86::FR64RegClassID:
162 case X86::RFP32RegClassID:
163 case X86::RFP64RegClassID:
164 case X86::RFP80RegClassID:
165 case X86::VR128RegClassID:
166 case X86::VR256RegClassID:
167 // Don't return a super-class that would shrink the spill size.
168 // That can happen with the vector and float classes.
169 if (Super->getSize() == RC->getSize())
177 const TargetRegisterClass *
178 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
180 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
181 case 0: // Normal GPRs.
182 if (TM.getSubtarget<X86Subtarget>().is64Bit())
183 return &X86::GR64RegClass;
184 return &X86::GR32RegClass;
185 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
186 if (TM.getSubtarget<X86Subtarget>().is64Bit())
187 return &X86::GR64_NOSPRegClass;
188 return &X86::GR32_NOSPRegClass;
189 case 2: // Available for tailcall (not callee-saved GPRs).
190 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
191 return &X86::GR64_TCW64RegClass;
192 if (TM.getSubtarget<X86Subtarget>().is64Bit())
193 return &X86::GR64_TCRegClass;
194 return &X86::GR32_TCRegClass;
198 const TargetRegisterClass *
199 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
200 if (RC == &X86::CCRRegClass) {
202 return &X86::GR64RegClass;
204 return &X86::GR32RegClass;
210 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
211 MachineFunction &MF) const {
212 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
214 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
215 switch (RC->getID()) {
218 case X86::GR32RegClassID:
220 case X86::GR64RegClassID:
222 case X86::VR128RegClassID:
223 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
224 case X86::VR64RegClassID:
230 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
231 bool callsEHReturn = false;
232 bool ghcCall = false;
235 callsEHReturn = MF->getMMI().callsEHReturn();
236 const Function *F = MF->getFunction();
237 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
241 return CSR_Ghc_SaveList;
244 return CSR_Win64_SaveList;
246 return CSR_64EHRet_SaveList;
247 return CSR_64_SaveList;
250 return CSR_32EHRet_SaveList;
251 return CSR_32_SaveList;
255 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
256 if (CC == CallingConv::GHC)
257 return CSR_Ghc_RegMask;
259 return CSR_32_RegMask;
261 return CSR_Win64_RegMask;
262 return CSR_64_RegMask;
265 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
266 BitVector Reserved(getNumRegs());
267 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
269 // Set the stack-pointer register and its aliases as reserved.
270 Reserved.set(X86::RSP);
271 Reserved.set(X86::ESP);
272 Reserved.set(X86::SP);
273 Reserved.set(X86::SPL);
275 // Set the instruction pointer register and its aliases as reserved.
276 Reserved.set(X86::RIP);
277 Reserved.set(X86::EIP);
278 Reserved.set(X86::IP);
280 // Set the frame-pointer register and its aliases as reserved if needed.
281 if (TFI->hasFP(MF)) {
282 Reserved.set(X86::RBP);
283 Reserved.set(X86::EBP);
284 Reserved.set(X86::BP);
285 Reserved.set(X86::BPL);
288 // Mark the segment registers as reserved.
289 Reserved.set(X86::CS);
290 Reserved.set(X86::SS);
291 Reserved.set(X86::DS);
292 Reserved.set(X86::ES);
293 Reserved.set(X86::FS);
294 Reserved.set(X86::GS);
296 // Reserve the registers that only exist in 64-bit mode.
298 // These 8-bit registers are part of the x86-64 extension even though their
299 // super-registers are old 32-bits.
300 Reserved.set(X86::SIL);
301 Reserved.set(X86::DIL);
302 Reserved.set(X86::BPL);
303 Reserved.set(X86::SPL);
305 for (unsigned n = 0; n != 8; ++n) {
307 const unsigned GPR64[] = {
308 X86::R8, X86::R9, X86::R10, X86::R11,
309 X86::R12, X86::R13, X86::R14, X86::R15
311 for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
315 assert(X86::XMM15 == X86::XMM8+7);
316 for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
325 //===----------------------------------------------------------------------===//
326 // Stack Frame Processing methods
327 //===----------------------------------------------------------------------===//
329 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
330 const MachineFrameInfo *MFI = MF.getFrameInfo();
331 return (MF.getTarget().Options.RealignStack &&
332 !MFI->hasVarSizedObjects());
335 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
336 const MachineFrameInfo *MFI = MF.getFrameInfo();
337 const Function *F = MF.getFunction();
338 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
339 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
340 F->hasFnAttr(Attribute::StackAlignment));
342 // FIXME: Currently we don't support stack realignment for functions with
343 // variable-sized allocas.
344 // FIXME: It's more complicated than this...
345 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
347 "Stack realignment in presence of dynamic allocas is not supported");
349 // If we've requested that we force align the stack do so now.
351 return canRealignStack(MF);
353 return requiresRealignment && canRealignStack(MF);
356 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
357 unsigned Reg, int &FrameIdx) const {
358 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
360 if (Reg == FramePtr && TFI->hasFP(MF)) {
361 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
367 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
370 return X86::SUB64ri8;
371 return X86::SUB64ri32;
374 return X86::SUB32ri8;
379 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
382 return X86::ADD64ri8;
383 return X86::ADD64ri32;
386 return X86::ADD32ri8;
391 void X86RegisterInfo::
392 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator I) const {
394 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
395 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
396 int Opcode = I->getOpcode();
397 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
398 DebugLoc DL = I->getDebugLoc();
399 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
400 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
403 if (!reseveCallFrame) {
404 // If the stack pointer can be changed after prologue, turn the
405 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
406 // adjcallstackdown instruction into 'add ESP, <amt>'
407 // TODO: consider using push / pop instead of sub + store / add
411 // We need to keep the stack aligned properly. To do this, we round the
412 // amount of space needed for the outgoing arguments up to the next
413 // alignment boundary.
414 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
415 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
417 MachineInstr *New = 0;
418 if (Opcode == TII.getCallFrameSetupOpcode()) {
419 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
424 assert(Opcode == TII.getCallFrameDestroyOpcode());
426 // Factor out the amount the callee already popped.
430 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
431 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
432 .addReg(StackPtr).addImm(Amount);
437 // The EFLAGS implicit def is dead.
438 New->getOperand(3).setIsDead();
440 // Replace the pseudo instruction with a new instruction.
447 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
448 // If we are performing frame pointer elimination and if the callee pops
449 // something off the stack pointer, add it back. We do this until we have
450 // more advanced stack pointer tracking ability.
451 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
452 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
453 .addReg(StackPtr).addImm(CalleeAmt);
455 // The EFLAGS implicit def is dead.
456 New->getOperand(3).setIsDead();
458 // We are not tracking the stack pointer adjustment by the callee, so make
459 // sure we restore the stack pointer immediately after the call, there may
460 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
461 MachineBasicBlock::iterator B = MBB.begin();
462 while (I != B && !llvm::prior(I)->isCall())
469 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
470 int SPAdj, RegScavenger *RS) const{
471 assert(SPAdj == 0 && "Unexpected");
474 MachineInstr &MI = *II;
475 MachineFunction &MF = *MI.getParent()->getParent();
476 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
478 while (!MI.getOperand(i).isFI()) {
480 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
483 int FrameIndex = MI.getOperand(i).getIndex();
486 unsigned Opc = MI.getOpcode();
487 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
488 if (needsStackRealignment(MF))
489 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
493 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
495 // This must be part of a four operand memory reference. Replace the
496 // FrameIndex with base register with EBP. Add an offset to the offset.
497 MI.getOperand(i).ChangeToRegister(BasePtr, false);
499 // Now add the frame object offset to the offset from EBP.
502 // Tail call jmp happens after FP is popped.
503 const MachineFrameInfo *MFI = MF.getFrameInfo();
504 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
506 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
508 if (MI.getOperand(i+3).isImm()) {
509 // Offset is a 32-bit integer.
510 int Imm = (int)(MI.getOperand(i + 3).getImm());
511 int Offset = FIOffset + Imm;
512 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
513 "Requesting 64-bit offset in 32-bit immediate!");
514 MI.getOperand(i + 3).ChangeToImmediate(Offset);
516 // Offset is symbolic. This is extremely rare.
517 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
518 MI.getOperand(i+3).setOffset(Offset);
522 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
523 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
524 return TFI->hasFP(MF) ? FramePtr : StackPtr;
527 unsigned X86RegisterInfo::getEHExceptionRegister() const {
528 llvm_unreachable("What is the exception register");
532 unsigned X86RegisterInfo::getEHHandlerRegister() const {
533 llvm_unreachable("What is the exception handler register");
538 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
539 switch (VT.getSimpleVT().SimpleTy) {
544 default: return getX86SubSuperRegister(Reg, MVT::i64, High);
545 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
547 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
549 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
551 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
557 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
559 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
561 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
563 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
565 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
567 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
569 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
571 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
573 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
575 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
577 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
579 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
581 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
583 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
585 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
587 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
594 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
596 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
598 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
600 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
602 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
604 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
606 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
608 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
610 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
612 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
614 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
616 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
618 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
620 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
622 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
624 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
630 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
632 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
634 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
636 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
638 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
640 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
642 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
644 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
646 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
648 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
650 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
652 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
654 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
656 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
658 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
660 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
664 // For 64-bit mode if we've requested a "high" register and the
665 // Q or r constraints we want one of these high registers or
666 // just the register name otherwise.
669 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
671 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
673 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
675 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
682 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
684 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
686 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
688 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
690 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
692 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
694 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
696 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
698 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
700 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
702 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
704 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
706 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
708 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
710 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
712 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
722 struct MSAH : public MachineFunctionPass {
724 MSAH() : MachineFunctionPass(ID) {}
726 virtual bool runOnMachineFunction(MachineFunction &MF) {
727 const X86TargetMachine *TM =
728 static_cast<const X86TargetMachine *>(&MF.getTarget());
729 const TargetFrameLowering *TFI = TM->getFrameLowering();
730 MachineRegisterInfo &RI = MF.getRegInfo();
731 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
732 unsigned StackAlignment = TFI->getStackAlignment();
734 // Be over-conservative: scan over all vreg defs and find whether vector
735 // registers are used. If yes, there is a possibility that vector register
736 // will be spilled and thus require dynamic stack realignment.
737 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
738 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
739 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
740 FuncInfo->setForceFramePointer(true);
748 virtual const char *getPassName() const {
749 return "X86 Maximal Stack Alignment Check";
752 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
753 AU.setPreservesCFG();
754 MachineFunctionPass::getAnalysisUsage(AU);
762 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }