1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/MachineValueType.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
47 ForceStackAlign("force-align-stack",
48 cl::desc("Force align the stack to the minimum alignment"
49 " needed for the function."),
50 cl::init(false), cl::Hidden);
53 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
56 X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI)
58 (STI.is64Bit() ? X86::RIP : X86::EIP),
59 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false),
60 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true),
61 (STI.is64Bit() ? X86::RIP : X86::EIP)),
63 X86_MC::InitLLVM2SEHRegisterMapping(this);
65 // Cache some information.
66 Is64Bit = Subtarget.is64Bit();
67 IsWin64 = Subtarget.isTargetWin64();
78 // Use a callee-saved register as the base pointer. These registers must
79 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
80 // requires GOT in the EBX register before function calls via PLT GOT pointer.
81 BasePtr = Is64Bit ? X86::RBX : X86::ESI;
84 /// getCompactUnwindRegNum - This function maps the register to the number for
85 /// compact unwind encoding. Return -1 if the register isn't valid.
86 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
87 switch (getLLVMRegNum(RegNum, isEH)) {
88 case X86::EBX: case X86::RBX: return 1;
89 case X86::ECX: case X86::R12: return 2;
90 case X86::EDX: case X86::R13: return 3;
91 case X86::EDI: case X86::R14: return 4;
92 case X86::ESI: case X86::R15: return 5;
93 case X86::EBP: case X86::RBP: return 6;
100 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
101 // ExeDepsFixer and PostRAScheduler require liveness.
106 X86RegisterInfo::getSEHRegNum(unsigned i) const {
107 return getEncodingValue(i);
110 const TargetRegisterClass *
111 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
112 unsigned Idx) const {
113 // The sub_8bit sub-register index is more constrained in 32-bit mode.
114 // It behaves just like the sub_8bit_hi index.
115 if (!Is64Bit && Idx == X86::sub_8bit)
116 Idx = X86::sub_8bit_hi;
118 // Forward to TableGen's default version.
119 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
122 const TargetRegisterClass *
123 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
124 const TargetRegisterClass *B,
125 unsigned SubIdx) const {
126 // The sub_8bit sub-register index is more constrained in 32-bit mode.
127 if (!Is64Bit && SubIdx == X86::sub_8bit) {
128 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
132 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
135 const TargetRegisterClass*
136 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
137 // Don't allow super-classes of GR8_NOREX. This class is only used after
138 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
139 // to the full GR8 register class in 64-bit mode, so we cannot allow the
140 // reigster class inflation.
142 // The GR8_NOREX class is always used in a way that won't be constrained to a
143 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
145 if (RC == &X86::GR8_NOREXRegClass)
148 const TargetRegisterClass *Super = RC;
149 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
151 switch (Super->getID()) {
152 case X86::GR8RegClassID:
153 case X86::GR16RegClassID:
154 case X86::GR32RegClassID:
155 case X86::GR64RegClassID:
156 case X86::FR32RegClassID:
157 case X86::FR64RegClassID:
158 case X86::RFP32RegClassID:
159 case X86::RFP64RegClassID:
160 case X86::RFP80RegClassID:
161 case X86::VR128RegClassID:
162 case X86::VR256RegClassID:
163 // Don't return a super-class that would shrink the spill size.
164 // That can happen with the vector and float classes.
165 if (Super->getSize() == RC->getSize())
173 const TargetRegisterClass *
174 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
175 unsigned Kind) const {
177 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
178 case 0: // Normal GPRs.
179 if (Subtarget.isTarget64BitLP64())
180 return &X86::GR64RegClass;
181 return &X86::GR32RegClass;
182 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
183 if (Subtarget.isTarget64BitLP64())
184 return &X86::GR64_NOSPRegClass;
185 return &X86::GR32_NOSPRegClass;
186 case 2: // Available for tailcall (not callee-saved GPRs).
187 if (Subtarget.isTargetWin64())
188 return &X86::GR64_TCW64RegClass;
189 else if (Subtarget.is64Bit())
190 return &X86::GR64_TCRegClass;
192 const Function *F = MF.getFunction();
193 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
195 return &X86::GR32RegClass;
196 return &X86::GR32_TCRegClass;
200 const TargetRegisterClass *
201 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
202 if (RC == &X86::CCRRegClass) {
204 return &X86::GR64RegClass;
206 return &X86::GR32RegClass;
212 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
213 MachineFunction &MF) const {
214 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
216 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
217 switch (RC->getID()) {
220 case X86::GR32RegClassID:
222 case X86::GR64RegClassID:
224 case X86::VR128RegClassID:
225 return Subtarget.is64Bit() ? 10 : 4;
226 case X86::VR64RegClassID:
232 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
233 bool HasAVX = Subtarget.hasAVX();
234 bool HasAVX512 = Subtarget.hasAVX512();
236 assert(MF && "MachineFunction required");
237 switch (MF->getFunction()->getCallingConv()) {
238 case CallingConv::GHC:
239 case CallingConv::HiPE:
240 return CSR_NoRegs_SaveList;
241 case CallingConv::AnyReg:
243 return CSR_64_AllRegs_AVX_SaveList;
244 return CSR_64_AllRegs_SaveList;
245 case CallingConv::PreserveMost:
246 return CSR_64_RT_MostRegs_SaveList;
247 case CallingConv::PreserveAll:
249 return CSR_64_RT_AllRegs_AVX_SaveList;
250 return CSR_64_RT_AllRegs_SaveList;
251 case CallingConv::Intel_OCL_BI: {
252 if (HasAVX512 && IsWin64)
253 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
254 if (HasAVX512 && Is64Bit)
255 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
256 if (HasAVX && IsWin64)
257 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
258 if (HasAVX && Is64Bit)
259 return CSR_64_Intel_OCL_BI_AVX_SaveList;
260 if (!HasAVX && !IsWin64 && Is64Bit)
261 return CSR_64_Intel_OCL_BI_SaveList;
264 case CallingConv::Cold:
266 return CSR_64_MostRegs_SaveList;
272 bool CallsEHReturn = MF->getMMI().callsEHReturn();
275 return CSR_Win64_SaveList;
277 return CSR_64EHRet_SaveList;
278 return CSR_64_SaveList;
281 return CSR_32EHRet_SaveList;
282 return CSR_32_SaveList;
286 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
287 bool HasAVX = Subtarget.hasAVX();
288 bool HasAVX512 = Subtarget.hasAVX512();
291 case CallingConv::GHC:
292 case CallingConv::HiPE:
293 return CSR_NoRegs_RegMask;
294 case CallingConv::AnyReg:
296 return CSR_64_AllRegs_AVX_RegMask;
297 return CSR_64_AllRegs_RegMask;
298 case CallingConv::PreserveMost:
299 return CSR_64_RT_MostRegs_RegMask;
300 case CallingConv::PreserveAll:
302 return CSR_64_RT_AllRegs_AVX_RegMask;
303 return CSR_64_RT_AllRegs_RegMask;
304 case CallingConv::Intel_OCL_BI: {
305 if (HasAVX512 && IsWin64)
306 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
307 if (HasAVX512 && Is64Bit)
308 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
309 if (HasAVX && IsWin64)
310 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
311 if (HasAVX && Is64Bit)
312 return CSR_64_Intel_OCL_BI_AVX_RegMask;
313 if (!HasAVX && !IsWin64 && Is64Bit)
314 return CSR_64_Intel_OCL_BI_RegMask;
317 case CallingConv::Cold:
319 return CSR_64_MostRegs_RegMask;
325 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
329 return CSR_Win64_RegMask;
330 return CSR_64_RegMask;
332 return CSR_32_RegMask;
336 X86RegisterInfo::getNoPreservedMask() const {
337 return CSR_NoRegs_RegMask;
340 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
341 BitVector Reserved(getNumRegs());
342 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
344 // Set the stack-pointer register and its aliases as reserved.
345 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
349 // Set the instruction pointer register and its aliases as reserved.
350 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
354 // Set the frame-pointer register and its aliases as reserved if needed.
355 if (TFI->hasFP(MF)) {
356 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
361 // Set the base-pointer register and its aliases as reserved if needed.
362 if (hasBasePointer(MF)) {
363 CallingConv::ID CC = MF.getFunction()->getCallingConv();
364 const uint32_t* RegMask = getCallPreservedMask(CC);
365 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
367 "Stack realignment in presence of dynamic allocas is not supported with"
368 "this calling convention.");
370 for (MCSubRegIterator I(getBaseRegister(), this, /*IncludeSelf=*/true);
375 // Mark the segment registers as reserved.
376 Reserved.set(X86::CS);
377 Reserved.set(X86::SS);
378 Reserved.set(X86::DS);
379 Reserved.set(X86::ES);
380 Reserved.set(X86::FS);
381 Reserved.set(X86::GS);
383 // Mark the floating point stack registers as reserved.
384 for (unsigned n = 0; n != 8; ++n)
385 Reserved.set(X86::ST0 + n);
387 // Reserve the registers that only exist in 64-bit mode.
389 // These 8-bit registers are part of the x86-64 extension even though their
390 // super-registers are old 32-bits.
391 Reserved.set(X86::SIL);
392 Reserved.set(X86::DIL);
393 Reserved.set(X86::BPL);
394 Reserved.set(X86::SPL);
396 for (unsigned n = 0; n != 8; ++n) {
398 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
402 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
406 if (!Is64Bit || !Subtarget.hasAVX512()) {
407 for (unsigned n = 16; n != 32; ++n) {
408 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
416 //===----------------------------------------------------------------------===//
417 // Stack Frame Processing methods
418 //===----------------------------------------------------------------------===//
420 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
421 const MachineFrameInfo *MFI = MF.getFrameInfo();
423 if (!EnableBasePointer)
426 // When we need stack realignment, we can't address the stack from the frame
427 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
428 // can't address variables from the stack pointer. MS inline asm can
429 // reference locals while also adjusting the stack pointer. When we can't
430 // use both the SP and the FP, we need a separate base pointer register.
431 bool CantUseFP = needsStackRealignment(MF);
433 MFI->hasVarSizedObjects() || MFI->hasInlineAsmWithSPAdjust();
434 return CantUseFP && CantUseSP;
437 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
438 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
441 const MachineFrameInfo *MFI = MF.getFrameInfo();
442 const MachineRegisterInfo *MRI = &MF.getRegInfo();
444 // Stack realignment requires a frame pointer. If we already started
445 // register allocation with frame pointer elimination, it is too late now.
446 if (!MRI->canReserveReg(FramePtr))
449 // If a base pointer is necessary. Check that it isn't too late to reserve
451 if (MFI->hasVarSizedObjects())
452 return MRI->canReserveReg(BasePtr);
456 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
457 const MachineFrameInfo *MFI = MF.getFrameInfo();
458 const Function *F = MF.getFunction();
459 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
460 bool requiresRealignment =
461 ((MFI->getMaxAlignment() > StackAlign) ||
462 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
463 Attribute::StackAlignment));
465 // If we've requested that we force align the stack do so now.
467 return canRealignStack(MF);
469 return requiresRealignment && canRealignStack(MF);
472 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
473 unsigned Reg, int &FrameIdx) const {
474 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
476 if (Reg == FramePtr && TFI->hasFP(MF)) {
477 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
484 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
485 int SPAdj, unsigned FIOperandNum,
486 RegScavenger *RS) const {
487 assert(SPAdj == 0 && "Unexpected");
489 MachineInstr &MI = *II;
490 MachineFunction &MF = *MI.getParent()->getParent();
491 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
492 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
495 unsigned Opc = MI.getOpcode();
496 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
497 if (hasBasePointer(MF))
498 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
499 else if (needsStackRealignment(MF))
500 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
504 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
506 // This must be part of a four operand memory reference. Replace the
507 // FrameIndex with base register with EBP. Add an offset to the offset.
508 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
510 // Now add the frame object offset to the offset from EBP.
513 // Tail call jmp happens after FP is popped.
514 const MachineFrameInfo *MFI = MF.getFrameInfo();
515 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
517 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
519 // The frame index format for stackmaps and patchpoints is different from the
520 // X86 format. It only has a FI and an offset.
521 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
522 assert(BasePtr == FramePtr && "Expected the FP as base register");
523 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
524 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
528 if (MI.getOperand(FIOperandNum+3).isImm()) {
529 // Offset is a 32-bit integer.
530 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
531 int Offset = FIOffset + Imm;
532 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
533 "Requesting 64-bit offset in 32-bit immediate!");
534 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
536 // Offset is symbolic. This is extremely rare.
537 uint64_t Offset = FIOffset +
538 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
539 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
543 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
544 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
545 return TFI->hasFP(MF) ? FramePtr : StackPtr;
549 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
552 default: llvm_unreachable("Unexpected VT");
556 default: return getX86SubSuperRegister(Reg, MVT::i64);
557 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
559 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
561 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
563 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
565 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
567 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
569 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
571 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
576 default: llvm_unreachable("Unexpected register");
577 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
579 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
581 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
583 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
585 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
587 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
589 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
591 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
593 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
595 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
597 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
599 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
601 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
603 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
605 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
607 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
613 default: llvm_unreachable("Unexpected register");
614 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
616 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
618 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
620 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
622 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
624 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
626 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
628 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
630 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
632 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
634 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
636 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
638 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
640 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
642 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
644 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
649 default: llvm_unreachable("Unexpected register");
650 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
652 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
654 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
656 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
658 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
660 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
662 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
664 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
666 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
668 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
670 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
672 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
674 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
676 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
678 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
680 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
685 default: llvm_unreachable("Unexpected register");
686 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
688 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
690 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
692 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
694 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
696 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
698 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
700 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
702 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
704 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
706 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
708 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
710 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
712 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
714 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
716 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
722 unsigned get512BitSuperRegister(unsigned Reg) {
723 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
724 return X86::ZMM0 + (Reg - X86::XMM0);
725 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
726 return X86::ZMM0 + (Reg - X86::YMM0);
727 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
729 llvm_unreachable("Unexpected SIMD register");