1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/ErrorHandling.h"
45 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
46 const TargetInstrInfo &tii)
47 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
48 X86::ADJCALLSTACKDOWN64 :
49 X86::ADJCALLSTACKDOWN32,
50 tm.getSubtarget<X86Subtarget>().is64Bit() ?
51 X86::ADJCALLSTACKUP64 :
52 X86::ADJCALLSTACKUP32),
54 // Cache some information.
55 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
56 Is64Bit = Subtarget->is64Bit();
57 IsWin64 = Subtarget->isTargetWin64();
58 StackAlign = TM.getFrameInfo()->getStackAlignment();
71 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
72 /// specific numbering, used in debug info and exception tables.
73 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
74 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
75 unsigned Flavour = DWARFFlavour::X86_64;
77 if (!Subtarget->is64Bit()) {
78 if (Subtarget->isTargetDarwin()) {
80 Flavour = DWARFFlavour::X86_32_DarwinEH;
82 Flavour = DWARFFlavour::X86_32_Generic;
83 } else if (Subtarget->isTargetCygMing()) {
84 // Unsupported by now, just quick fallback
85 Flavour = DWARFFlavour::X86_32_Generic;
87 Flavour = DWARFFlavour::X86_32_Generic;
91 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
94 /// getX86RegNum - This function maps LLVM register identifiers to their X86
95 /// specific numbering, which is used in various places encoding instructions.
96 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
98 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
99 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
100 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
101 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
102 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
104 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
106 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
108 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
111 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
113 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
115 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
117 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
119 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
121 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
123 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
125 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
128 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
129 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
130 return RegNo-X86::ST0;
132 case X86::XMM0: case X86::XMM8: case X86::MM0:
134 case X86::XMM1: case X86::XMM9: case X86::MM1:
136 case X86::XMM2: case X86::XMM10: case X86::MM2:
138 case X86::XMM3: case X86::XMM11: case X86::MM3:
140 case X86::XMM4: case X86::XMM12: case X86::MM4:
142 case X86::XMM5: case X86::XMM13: case X86::MM5:
144 case X86::XMM6: case X86::XMM14: case X86::MM6:
146 case X86::XMM7: case X86::XMM15: case X86::MM7:
150 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
151 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
156 const TargetRegisterClass *
157 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
158 const TargetRegisterClass *B,
159 unsigned SubIdx) const {
164 if (B == &X86::GR8RegClass) {
165 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
167 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
168 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
169 A == &X86::GR64_NOREXRegClass ||
170 A == &X86::GR64_NOSPRegClass ||
171 A == &X86::GR64_NOREX_NOSPRegClass)
172 return &X86::GR64_ABCDRegClass;
173 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
174 A == &X86::GR32_NOREXRegClass ||
175 A == &X86::GR32_NOSPRegClass)
176 return &X86::GR32_ABCDRegClass;
177 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
178 A == &X86::GR16_NOREXRegClass)
179 return &X86::GR16_ABCDRegClass;
180 } else if (B == &X86::GR8_NOREXRegClass) {
181 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
182 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
183 return &X86::GR64_NOREXRegClass;
184 else if (A == &X86::GR64_ABCDRegClass)
185 return &X86::GR64_ABCDRegClass;
186 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
187 A == &X86::GR32_NOSPRegClass)
188 return &X86::GR32_NOREXRegClass;
189 else if (A == &X86::GR32_ABCDRegClass)
190 return &X86::GR32_ABCDRegClass;
191 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
192 return &X86::GR16_NOREXRegClass;
193 else if (A == &X86::GR16_ABCDRegClass)
194 return &X86::GR16_ABCDRegClass;
199 if (B == &X86::GR8_ABCD_HRegClass) {
200 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
201 A == &X86::GR64_NOREXRegClass ||
202 A == &X86::GR64_NOSPRegClass ||
203 A == &X86::GR64_NOREX_NOSPRegClass)
204 return &X86::GR64_ABCDRegClass;
205 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
206 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
207 return &X86::GR32_ABCDRegClass;
208 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
209 A == &X86::GR16_NOREXRegClass)
210 return &X86::GR16_ABCDRegClass;
215 if (B == &X86::GR16RegClass) {
216 if (A->getSize() == 4 || A->getSize() == 8)
218 } else if (B == &X86::GR16_ABCDRegClass) {
219 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
220 A == &X86::GR64_NOREXRegClass ||
221 A == &X86::GR64_NOSPRegClass ||
222 A == &X86::GR64_NOREX_NOSPRegClass)
223 return &X86::GR64_ABCDRegClass;
224 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
225 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
226 return &X86::GR32_ABCDRegClass;
227 } else if (B == &X86::GR16_NOREXRegClass) {
228 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
229 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
230 return &X86::GR64_NOREXRegClass;
231 else if (A == &X86::GR64_ABCDRegClass)
232 return &X86::GR64_ABCDRegClass;
233 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
234 A == &X86::GR32_NOSPRegClass)
235 return &X86::GR32_NOREXRegClass;
236 else if (A == &X86::GR32_ABCDRegClass)
237 return &X86::GR64_ABCDRegClass;
242 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
243 if (A->getSize() == 8)
245 } else if (B == &X86::GR32_ABCDRegClass) {
246 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
247 A == &X86::GR64_NOREXRegClass ||
248 A == &X86::GR64_NOSPRegClass ||
249 A == &X86::GR64_NOREX_NOSPRegClass)
250 return &X86::GR64_ABCDRegClass;
251 } else if (B == &X86::GR32_NOREXRegClass) {
252 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
253 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
254 return &X86::GR64_NOREXRegClass;
255 else if (A == &X86::GR64_ABCDRegClass)
256 return &X86::GR64_ABCDRegClass;
263 const TargetRegisterClass *
264 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
266 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
267 case 0: // Normal GPRs.
268 if (TM.getSubtarget<X86Subtarget>().is64Bit())
269 return &X86::GR64RegClass;
270 return &X86::GR32RegClass;
271 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
272 if (TM.getSubtarget<X86Subtarget>().is64Bit())
273 return &X86::GR64_NOSPRegClass;
274 return &X86::GR32_NOSPRegClass;
278 const TargetRegisterClass *
279 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
280 if (RC == &X86::CCRRegClass) {
282 return &X86::GR64RegClass;
284 return &X86::GR32RegClass;
290 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
291 bool callsEHReturn = false;
294 const MachineFrameInfo *MFI = MF->getFrameInfo();
295 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
296 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
299 static const unsigned CalleeSavedRegs32Bit[] = {
300 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
303 static const unsigned CalleeSavedRegs32EHRet[] = {
304 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
307 static const unsigned CalleeSavedRegs64Bit[] = {
308 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
311 static const unsigned CalleeSavedRegs64EHRet[] = {
312 X86::RAX, X86::RDX, X86::RBX, X86::R12,
313 X86::R13, X86::R14, X86::R15, X86::RBP, 0
316 static const unsigned CalleeSavedRegsWin64[] = {
317 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
318 X86::R12, X86::R13, X86::R14, X86::R15,
319 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
320 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
321 X86::XMM14, X86::XMM15, 0
326 return CalleeSavedRegsWin64;
328 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
330 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
334 const TargetRegisterClass* const*
335 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
336 bool callsEHReturn = false;
339 const MachineFrameInfo *MFI = MF->getFrameInfo();
340 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
341 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
344 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
345 &X86::GR32RegClass, &X86::GR32RegClass,
346 &X86::GR32RegClass, &X86::GR32RegClass, 0
348 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
349 &X86::GR32RegClass, &X86::GR32RegClass,
350 &X86::GR32RegClass, &X86::GR32RegClass,
351 &X86::GR32RegClass, &X86::GR32RegClass, 0
353 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
354 &X86::GR64RegClass, &X86::GR64RegClass,
355 &X86::GR64RegClass, &X86::GR64RegClass,
356 &X86::GR64RegClass, &X86::GR64RegClass, 0
358 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
359 &X86::GR64RegClass, &X86::GR64RegClass,
360 &X86::GR64RegClass, &X86::GR64RegClass,
361 &X86::GR64RegClass, &X86::GR64RegClass,
362 &X86::GR64RegClass, &X86::GR64RegClass, 0
364 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
365 &X86::GR64RegClass, &X86::GR64RegClass,
366 &X86::GR64RegClass, &X86::GR64RegClass,
367 &X86::GR64RegClass, &X86::GR64RegClass,
368 &X86::GR64RegClass, &X86::GR64RegClass,
369 &X86::VR128RegClass, &X86::VR128RegClass,
370 &X86::VR128RegClass, &X86::VR128RegClass,
371 &X86::VR128RegClass, &X86::VR128RegClass,
372 &X86::VR128RegClass, &X86::VR128RegClass,
373 &X86::VR128RegClass, &X86::VR128RegClass, 0
378 return CalleeSavedRegClassesWin64;
380 return (callsEHReturn ?
381 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
383 return (callsEHReturn ?
384 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
388 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
389 BitVector Reserved(getNumRegs());
390 // Set the stack-pointer register and its aliases as reserved.
391 Reserved.set(X86::RSP);
392 Reserved.set(X86::ESP);
393 Reserved.set(X86::SP);
394 Reserved.set(X86::SPL);
396 // Set the frame-pointer register and its aliases as reserved if needed.
398 Reserved.set(X86::RBP);
399 Reserved.set(X86::EBP);
400 Reserved.set(X86::BP);
401 Reserved.set(X86::BPL);
404 // Mark the x87 stack registers as reserved, since they don't behave normally
405 // with respect to liveness. We don't fully model the effects of x87 stack
406 // pushes and pops after stackification.
407 Reserved.set(X86::ST0);
408 Reserved.set(X86::ST1);
409 Reserved.set(X86::ST2);
410 Reserved.set(X86::ST3);
411 Reserved.set(X86::ST4);
412 Reserved.set(X86::ST5);
413 Reserved.set(X86::ST6);
414 Reserved.set(X86::ST7);
418 //===----------------------------------------------------------------------===//
419 // Stack Frame Processing methods
420 //===----------------------------------------------------------------------===//
422 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
423 unsigned MaxAlign = 0;
425 for (int i = FFI->getObjectIndexBegin(),
426 e = FFI->getObjectIndexEnd(); i != e; ++i) {
427 if (FFI->isDeadObjectIndex(i))
430 unsigned Align = FFI->getObjectAlignment(i);
431 MaxAlign = std::max(MaxAlign, Align);
437 /// hasFP - Return true if the specified function should have a dedicated frame
438 /// pointer register. This is true if the function has variable sized allocas
439 /// or if frame pointer elimination is disabled.
440 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
441 const MachineFrameInfo *MFI = MF.getFrameInfo();
442 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
444 return (NoFramePointerElim ||
445 needsStackRealignment(MF) ||
446 MFI->hasVarSizedObjects() ||
447 MFI->isFrameAddressTaken() ||
448 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
449 (MMI && MMI->callsUnwindInit()));
452 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
453 const MachineFrameInfo *MFI = MF.getFrameInfo();
455 // FIXME: Currently we don't support stack realignment for functions with
456 // variable-sized allocas
457 return (RealignStack &&
458 (MFI->getMaxAlignment() > StackAlign &&
459 !MFI->hasVarSizedObjects()));
462 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
463 return !MF.getFrameInfo()->hasVarSizedObjects();
466 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
467 int &FrameIdx) const {
468 if (Reg == FramePtr && hasFP(MF)) {
469 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
476 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
477 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
478 MachineFrameInfo *MFI = MF.getFrameInfo();
479 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
480 uint64_t StackSize = MFI->getStackSize();
482 if (needsStackRealignment(MF)) {
484 // Skip the saved EBP.
487 unsigned Align = MFI->getObjectAlignment(FI);
488 assert( (-(Offset + StackSize)) % Align == 0);
490 return Offset + StackSize;
492 // FIXME: Support tail calls
495 return Offset + StackSize;
497 // Skip the saved EBP.
500 // Skip the RETADDR move area
501 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
502 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
503 if (TailCallReturnAddrDelta < 0)
504 Offset -= TailCallReturnAddrDelta;
510 void X86RegisterInfo::
511 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
512 MachineBasicBlock::iterator I) const {
513 if (!hasReservedCallFrame(MF)) {
514 // If the stack pointer can be changed after prologue, turn the
515 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
516 // adjcallstackdown instruction into 'add ESP, <amt>'
517 // TODO: consider using push / pop instead of sub + store / add
518 MachineInstr *Old = I;
519 uint64_t Amount = Old->getOperand(0).getImm();
521 // We need to keep the stack aligned properly. To do this, we round the
522 // amount of space needed for the outgoing arguments up to the next
523 // alignment boundary.
524 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
526 MachineInstr *New = 0;
527 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
528 New = BuildMI(MF, Old->getDebugLoc(),
529 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
534 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
536 // Factor out the amount the callee already popped.
537 uint64_t CalleeAmt = Old->getOperand(1).getImm();
541 unsigned Opc = (Amount < 128) ?
542 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
543 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
544 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
551 // The EFLAGS implicit def is dead.
552 New->getOperand(3).setIsDead();
554 // Replace the pseudo instruction with a new instruction.
558 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
559 // If we are performing frame pointer elimination and if the callee pops
560 // something off the stack pointer, add it back. We do this until we have
561 // more advanced stack pointer tracking ability.
562 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
563 unsigned Opc = (CalleeAmt < 128) ?
564 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
565 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
566 MachineInstr *Old = I;
568 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
573 // The EFLAGS implicit def is dead.
574 New->getOperand(3).setIsDead();
583 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
584 int SPAdj, int *Value,
585 RegScavenger *RS) const{
586 assert(SPAdj == 0 && "Unexpected");
589 MachineInstr &MI = *II;
590 MachineFunction &MF = *MI.getParent()->getParent();
592 while (!MI.getOperand(i).isFI()) {
594 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
597 int FrameIndex = MI.getOperand(i).getIndex();
600 if (needsStackRealignment(MF))
601 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
603 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
605 // This must be part of a four operand memory reference. Replace the
606 // FrameIndex with base register with EBP. Add an offset to the offset.
607 MI.getOperand(i).ChangeToRegister(BasePtr, false);
609 // Now add the frame object offset to the offset from EBP.
610 if (MI.getOperand(i+3).isImm()) {
611 // Offset is a 32-bit integer.
612 int Offset = getFrameIndexOffset(MF, FrameIndex) +
613 (int)(MI.getOperand(i + 3).getImm());
615 MI.getOperand(i + 3).ChangeToImmediate(Offset);
617 // Offset is symbolic. This is extremely rare.
618 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
619 (uint64_t)MI.getOperand(i+3).getOffset();
620 MI.getOperand(i+3).setOffset(Offset);
626 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
627 RegScavenger *RS) const {
628 MachineFrameInfo *MFI = MF.getFrameInfo();
630 // Calculate and set max stack object alignment early, so we can decide
631 // whether we will need stack realignment (and thus FP).
632 unsigned MaxAlign = std::max(MFI->getMaxAlignment(),
633 calculateMaxStackAlignment(MFI));
635 MFI->setMaxAlignment(MaxAlign);
637 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
638 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
640 if (TailCallReturnAddrDelta < 0) {
641 // create RETURNADDR area
650 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
651 (-1U*SlotSize)+TailCallReturnAddrDelta);
655 assert((TailCallReturnAddrDelta <= 0) &&
656 "The Delta should always be zero or negative");
657 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
659 // Create a frame entry for the EBP register that must be saved.
660 int FrameIdx = MFI->CreateFixedObject(SlotSize,
662 TFI.getOffsetOfLocalArea() +
663 TailCallReturnAddrDelta);
664 assert(FrameIdx == MFI->getObjectIndexBegin() &&
665 "Slot for EBP register must be last in order to be found!");
670 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
671 /// stack pointer by a constant value.
673 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
674 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
675 const TargetInstrInfo &TII) {
676 bool isSub = NumBytes < 0;
677 uint64_t Offset = isSub ? -NumBytes : NumBytes;
680 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
681 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
683 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
684 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
685 uint64_t Chunk = (1LL << 31) - 1;
686 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
687 DebugLoc::getUnknownLoc());
690 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
692 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
695 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
700 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
702 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
703 unsigned StackPtr, uint64_t *NumBytes = NULL) {
704 if (MBBI == MBB.begin()) return;
706 MachineBasicBlock::iterator PI = prior(MBBI);
707 unsigned Opc = PI->getOpcode();
708 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
709 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
710 PI->getOperand(0).getReg() == StackPtr) {
712 *NumBytes += PI->getOperand(2).getImm();
714 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
715 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
716 PI->getOperand(0).getReg() == StackPtr) {
718 *NumBytes -= PI->getOperand(2).getImm();
723 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
725 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
726 MachineBasicBlock::iterator &MBBI,
727 unsigned StackPtr, uint64_t *NumBytes = NULL) {
728 // FIXME: THIS ISN'T RUN!!!
731 if (MBBI == MBB.end()) return;
733 MachineBasicBlock::iterator NI = next(MBBI);
734 if (NI == MBB.end()) return;
736 unsigned Opc = NI->getOpcode();
737 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
738 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
739 NI->getOperand(0).getReg() == StackPtr) {
741 *NumBytes -= NI->getOperand(2).getImm();
744 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
745 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
746 NI->getOperand(0).getReg() == StackPtr) {
748 *NumBytes += NI->getOperand(2).getImm();
754 /// mergeSPUpdates - Checks the instruction before/after the passed
755 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
756 /// stack adjustment is returned as a positive value for ADD and a negative for
758 static int mergeSPUpdates(MachineBasicBlock &MBB,
759 MachineBasicBlock::iterator &MBBI,
761 bool doMergeWithPrevious) {
762 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
763 (!doMergeWithPrevious && MBBI == MBB.end()))
766 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
767 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
768 unsigned Opc = PI->getOpcode();
771 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
772 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
773 PI->getOperand(0).getReg() == StackPtr){
774 Offset += PI->getOperand(2).getImm();
776 if (!doMergeWithPrevious) MBBI = NI;
777 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
778 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
779 PI->getOperand(0).getReg() == StackPtr) {
780 Offset -= PI->getOperand(2).getImm();
782 if (!doMergeWithPrevious) MBBI = NI;
788 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
790 unsigned FramePtr) const {
791 MachineFrameInfo *MFI = MF.getFrameInfo();
792 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
795 // Add callee saved registers to move list.
796 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
797 if (CSI.empty()) return;
799 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
800 const TargetData *TD = MF.getTarget().getTargetData();
801 bool HasFP = hasFP(MF);
803 // Calculate amount of bytes used for return address storing.
805 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
806 TargetFrameInfo::StackGrowsUp ?
807 TD->getPointerSize() : -TD->getPointerSize());
809 // FIXME: This is dirty hack. The code itself is pretty mess right now.
810 // It should be rewritten from scratch and generalized sometimes.
812 // Determine maximum offset (minumum due to stack growth).
813 int64_t MaxOffset = 0;
814 for (std::vector<CalleeSavedInfo>::const_iterator
815 I = CSI.begin(), E = CSI.end(); I != E; ++I)
816 MaxOffset = std::min(MaxOffset,
817 MFI->getObjectOffset(I->getFrameIdx()));
819 // Calculate offsets.
820 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
821 for (std::vector<CalleeSavedInfo>::const_iterator
822 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
823 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
824 unsigned Reg = I->getReg();
825 Offset = MaxOffset - Offset + saveAreaOffset;
827 // Don't output a new machine move if we're re-saving the frame
828 // pointer. This happens when the PrologEpilogInserter has inserted an extra
829 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
830 // generates one when frame pointers are used. If we generate a "machine
831 // move" for this extra "PUSH", the linker will lose track of the fact that
832 // the frame pointer should have the value of the first "PUSH" when it's
835 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
836 // another bug. I.e., one where we generate a prolog like this:
844 // The immediate re-push of EBP is unnecessary. At the least, it's an
845 // optimization bug. EBP can be used as a scratch register in certain
846 // cases, but probably not when we have a frame pointer.
847 if (HasFP && FramePtr == Reg)
850 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
851 MachineLocation CSSrc(Reg);
852 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
856 /// emitPrologue - Push callee-saved registers onto the stack, which
857 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
858 /// space for local variables. Also emit labels used by the exception handler to
859 /// generate the exception handling frames.
860 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
861 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
862 MachineBasicBlock::iterator MBBI = MBB.begin();
863 MachineFrameInfo *MFI = MF.getFrameInfo();
864 const Function *Fn = MF.getFunction();
865 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
866 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
867 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
868 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
869 !Fn->doesNotThrow() || UnwindTablesMandatory;
870 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
871 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
872 bool HasFP = hasFP(MF);
875 // Add RETADDR move area to callee saved frame size.
876 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
877 if (TailCallReturnAddrDelta < 0)
878 X86FI->setCalleeSavedFrameSize(
879 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
881 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
882 // function, and use up to 128 bytes of stack space, don't have a frame
883 // pointer, calls, or dynamic alloca then we do not need to adjust the
884 // stack pointer (we fit in the Red Zone).
885 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
886 !needsStackRealignment(MF) &&
887 !MFI->hasVarSizedObjects() && // No dynamic alloca.
888 !MFI->hasCalls() && // No calls.
889 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
890 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
891 if (HasFP) MinSize += SlotSize;
892 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
893 MFI->setStackSize(StackSize);
894 } else if (Subtarget->isTargetWin64()) {
895 // We need to always allocate 32 bytes as register spill area.
896 // FIXME: We might reuse these 32 bytes for leaf functions.
898 MFI->setStackSize(StackSize);
901 // Insert stack pointer adjustment for later moving of return addr. Only
902 // applies to tail call optimized functions where the callee argument stack
903 // size is bigger than the callers.
904 if (TailCallReturnAddrDelta < 0) {
906 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
909 .addImm(-TailCallReturnAddrDelta);
910 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
913 // Mapping for machine moves:
915 // DST: VirtualFP AND
916 // SRC: VirtualFP => DW_CFA_def_cfa_offset
917 // ELSE => DW_CFA_def_cfa
919 // SRC: VirtualFP AND
920 // DST: Register => DW_CFA_def_cfa_register
923 // OFFSET < 0 => DW_CFA_offset_extended_sf
924 // REG < 64 => DW_CFA_offset + Reg
925 // ELSE => DW_CFA_offset_extended
927 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
928 const TargetData *TD = MF.getTarget().getTargetData();
929 uint64_t NumBytes = 0;
931 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
932 TargetFrameInfo::StackGrowsUp ?
933 TD->getPointerSize() : -TD->getPointerSize());
936 // Calculate required stack adjustment.
937 uint64_t FrameSize = StackSize - SlotSize;
938 if (needsStackRealignment(MF))
939 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
941 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
943 // Get the offset of the stack slot for the EBP register, which is
944 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
945 // Update the frame offset adjustment.
946 MFI->setOffsetAdjustment(-NumBytes);
948 // Save EBP/RBP into the appropriate stack slot.
949 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
950 .addReg(FramePtr, RegState::Kill);
952 if (needsFrameMoves) {
953 // Mark the place where EBP/RBP was saved.
954 unsigned FrameLabelId = MMI->NextLabelID();
955 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
957 // Define the current CFA rule to use the provided offset.
959 MachineLocation SPDst(MachineLocation::VirtualFP);
960 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
961 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
963 // FIXME: Verify & implement for FP
964 MachineLocation SPDst(StackPtr);
965 MachineLocation SPSrc(StackPtr, stackGrowth);
966 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
969 // Change the rule for the FramePtr to be an "offset" rule.
970 MachineLocation FPDst(MachineLocation::VirtualFP,
972 MachineLocation FPSrc(FramePtr);
973 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
976 // Update EBP with the new base value...
977 BuildMI(MBB, MBBI, DL,
978 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
981 if (needsFrameMoves) {
982 // Mark effective beginning of when frame pointer becomes valid.
983 unsigned FrameLabelId = MMI->NextLabelID();
984 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
986 // Define the current CFA to use the EBP/RBP register.
987 MachineLocation FPDst(FramePtr);
988 MachineLocation FPSrc(MachineLocation::VirtualFP);
989 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
992 // Mark the FramePtr as live-in in every block except the entry.
993 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
995 I->addLiveIn(FramePtr);
998 if (needsStackRealignment(MF)) {
1000 BuildMI(MBB, MBBI, DL,
1001 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1002 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1004 // The EFLAGS implicit def is dead.
1005 MI->getOperand(3).setIsDead();
1008 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1011 // Skip the callee-saved push instructions.
1012 bool PushedRegs = false;
1013 int StackOffset = 2 * stackGrowth;
1015 while (MBBI != MBB.end() &&
1016 (MBBI->getOpcode() == X86::PUSH32r ||
1017 MBBI->getOpcode() == X86::PUSH64r)) {
1021 if (!HasFP && needsFrameMoves) {
1022 // Mark callee-saved push instruction.
1023 unsigned LabelId = MMI->NextLabelID();
1024 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1026 // Define the current CFA rule to use the provided offset.
1027 unsigned Ptr = StackSize ?
1028 MachineLocation::VirtualFP : StackPtr;
1029 MachineLocation SPDst(Ptr);
1030 MachineLocation SPSrc(Ptr, StackOffset);
1031 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1032 StackOffset += stackGrowth;
1036 if (MBBI != MBB.end())
1037 DL = MBBI->getDebugLoc();
1039 // Adjust stack pointer: ESP -= numbytes.
1040 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1041 // Check, whether EAX is livein for this function.
1042 bool isEAXAlive = false;
1043 for (MachineRegisterInfo::livein_iterator
1044 II = MF.getRegInfo().livein_begin(),
1045 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1046 unsigned Reg = II->first;
1047 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1048 Reg == X86::AH || Reg == X86::AL);
1051 // Function prologue calls _alloca to probe the stack when allocating more
1052 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1053 // to ensure that the guard pages used by the OS virtual memory manager are
1054 // allocated in correct sequence.
1056 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1058 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1059 .addExternalSymbol("_alloca");
1062 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1063 .addReg(X86::EAX, RegState::Kill);
1065 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1066 // allocated bytes for EAX.
1067 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1068 .addImm(NumBytes - 4);
1069 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1070 .addExternalSymbol("_alloca");
1073 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1075 StackPtr, false, NumBytes - 4);
1076 MBB.insert(MBBI, MI);
1078 } else if (NumBytes) {
1079 // If there is an SUB32ri of ESP immediately before this instruction, merge
1080 // the two. This can be the case when tail call elimination is enabled and
1081 // the callee has more arguments then the caller.
1082 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1084 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1085 // instruction, merge the two instructions.
1086 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1089 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1092 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1093 // Mark end of stack pointer adjustment.
1094 unsigned LabelId = MMI->NextLabelID();
1095 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1097 if (!HasFP && NumBytes) {
1098 // Define the current CFA rule to use the provided offset.
1100 MachineLocation SPDst(MachineLocation::VirtualFP);
1101 MachineLocation SPSrc(MachineLocation::VirtualFP,
1102 -StackSize + stackGrowth);
1103 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1105 // FIXME: Verify & implement for FP
1106 MachineLocation SPDst(StackPtr);
1107 MachineLocation SPSrc(StackPtr, stackGrowth);
1108 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1112 // Emit DWARF info specifying the offsets of the callee-saved registers.
1114 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1118 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1119 MachineBasicBlock &MBB) const {
1120 const MachineFrameInfo *MFI = MF.getFrameInfo();
1121 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1122 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1123 unsigned RetOpcode = MBBI->getOpcode();
1124 DebugLoc DL = MBBI->getDebugLoc();
1126 switch (RetOpcode) {
1128 llvm_unreachable("Can only insert epilog into returning blocks");
1131 case X86::TCRETURNdi:
1132 case X86::TCRETURNri:
1133 case X86::TCRETURNri64:
1134 case X86::TCRETURNdi64:
1135 case X86::EH_RETURN:
1136 case X86::EH_RETURN64:
1140 break; // These are ok
1143 // Get the number of bytes to allocate from the FrameInfo.
1144 uint64_t StackSize = MFI->getStackSize();
1145 uint64_t MaxAlign = MFI->getMaxAlignment();
1146 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1147 uint64_t NumBytes = 0;
1150 // Calculate required stack adjustment.
1151 uint64_t FrameSize = StackSize - SlotSize;
1152 if (needsStackRealignment(MF))
1153 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1155 NumBytes = FrameSize - CSSize;
1158 BuildMI(MBB, MBBI, DL,
1159 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1161 NumBytes = StackSize - CSSize;
1164 // Skip the callee-saved pop instructions.
1165 MachineBasicBlock::iterator LastCSPop = MBBI;
1166 while (MBBI != MBB.begin()) {
1167 MachineBasicBlock::iterator PI = prior(MBBI);
1168 unsigned Opc = PI->getOpcode();
1170 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1171 !PI->getDesc().isTerminator())
1177 DL = MBBI->getDebugLoc();
1179 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1180 // instruction, merge the two instructions.
1181 if (NumBytes || MFI->hasVarSizedObjects())
1182 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1184 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1185 // slot before popping them off! Same applies for the case, when stack was
1187 if (needsStackRealignment(MF)) {
1188 // We cannot use LEA here, because stack pointer was realigned. We need to
1189 // deallocate local frame back.
1191 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1192 MBBI = prior(LastCSPop);
1195 BuildMI(MBB, MBBI, DL,
1196 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1197 StackPtr).addReg(FramePtr);
1198 } else if (MFI->hasVarSizedObjects()) {
1200 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1202 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1203 FramePtr, false, -CSSize);
1204 MBB.insert(MBBI, MI);
1206 BuildMI(MBB, MBBI, DL,
1207 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1210 } else if (NumBytes) {
1211 // Adjust stack pointer back: ESP += numbytes.
1212 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1215 // We're returning from function via eh_return.
1216 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1217 MBBI = prior(MBB.end());
1218 MachineOperand &DestAddr = MBBI->getOperand(0);
1219 assert(DestAddr.isReg() && "Offset should be in register!");
1220 BuildMI(MBB, MBBI, DL,
1221 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1222 StackPtr).addReg(DestAddr.getReg());
1223 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1224 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1225 // Tail call return: adjust the stack pointer and jump to callee.
1226 MBBI = prior(MBB.end());
1227 MachineOperand &JumpTarget = MBBI->getOperand(0);
1228 MachineOperand &StackAdjust = MBBI->getOperand(1);
1229 assert(StackAdjust.isImm() && "Expecting immediate value.");
1231 // Adjust stack pointer.
1232 int StackAdj = StackAdjust.getImm();
1233 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1235 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1237 // Incoporate the retaddr area.
1238 Offset = StackAdj-MaxTCDelta;
1239 assert(Offset >= 0 && "Offset should never be negative");
1242 // Check for possible merge with preceeding ADD instruction.
1243 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1244 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1247 // Jump to label or value in register.
1248 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1249 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1250 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1251 else if (RetOpcode== X86::TCRETURNri64)
1252 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1254 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1256 // Delete the pseudo instruction TCRETURN.
1258 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1259 (X86FI->getTCReturnAddrDelta() < 0)) {
1260 // Add the return addr area delta back since we are not tail calling.
1261 int delta = -1*X86FI->getTCReturnAddrDelta();
1262 MBBI = prior(MBB.end());
1264 // Check for possible merge with preceeding ADD instruction.
1265 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1266 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1270 unsigned X86RegisterInfo::getRARegister() const {
1271 return Is64Bit ? X86::RIP // Should have dwarf #16.
1272 : X86::EIP; // Should have dwarf #8.
1275 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1276 return hasFP(MF) ? FramePtr : StackPtr;
1280 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1281 // Calculate amount of bytes used for return address storing
1282 int stackGrowth = (Is64Bit ? -8 : -4);
1284 // Initial state of the frame pointer is esp+4.
1285 MachineLocation Dst(MachineLocation::VirtualFP);
1286 MachineLocation Src(StackPtr, stackGrowth);
1287 Moves.push_back(MachineMove(0, Dst, Src));
1289 // Add return address to move list
1290 MachineLocation CSDst(StackPtr, stackGrowth);
1291 MachineLocation CSSrc(getRARegister());
1292 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1295 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1296 llvm_unreachable("What is the exception register");
1300 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1301 llvm_unreachable("What is the exception handler register");
1306 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1307 switch (VT.getSimpleVT().SimpleTy) {
1308 default: return Reg;
1313 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1315 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1317 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1319 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1325 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1327 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1329 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1331 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1333 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1335 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1337 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1339 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1341 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1343 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1345 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1347 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1349 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1351 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1353 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1355 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1361 default: return Reg;
1362 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1364 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1366 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1368 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1370 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1372 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1374 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1376 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1378 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1380 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1382 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1384 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1386 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1388 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1390 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1392 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1397 default: return Reg;
1398 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1400 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1402 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1404 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1406 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1408 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1410 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1412 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1414 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1416 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1418 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1420 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1422 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1424 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1426 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1428 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1433 default: return Reg;
1434 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1436 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1438 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1440 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1442 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1444 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1446 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1448 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1450 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1452 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1454 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1456 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1458 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1460 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1462 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1464 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1473 #include "X86GenRegisterInfo.inc"
1476 struct MSAC : public MachineFunctionPass {
1478 MSAC() : MachineFunctionPass(&ID) {}
1480 virtual bool runOnMachineFunction(MachineFunction &MF) {
1481 MachineFrameInfo *FFI = MF.getFrameInfo();
1482 MachineRegisterInfo &RI = MF.getRegInfo();
1484 // Calculate max stack alignment of all already allocated stack objects.
1485 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1487 // Be over-conservative: scan over all vreg defs and find, whether vector
1488 // registers are used. If yes - there is probability, that vector register
1489 // will be spilled and thus stack needs to be aligned properly.
1490 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1491 RegNum < RI.getLastVirtReg(); ++RegNum)
1492 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1494 if (FFI->getMaxAlignment() == MaxAlign)
1497 FFI->setMaxAlignment(MaxAlign);
1501 virtual const char *getPassName() const {
1502 return "X86 Maximal Stack Alignment Calculator";
1505 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1506 AU.setPreservesCFG();
1507 MachineFunctionPass::getAnalysisUsage(AU);
1515 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }