1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45 const TargetInstrInfo &tii)
46 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47 X86::ADJCALLSTACKDOWN64 :
48 X86::ADJCALLSTACKDOWN32,
49 tm.getSubtarget<X86Subtarget>().is64Bit() ?
50 X86::ADJCALLSTACKUP64 :
51 X86::ADJCALLSTACKUP32),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
56 IsWin64 = Subtarget->isTargetWin64();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
70 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
71 /// specific numbering, used in debug info and exception tables.
72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74 unsigned Flavour = DWARFFlavour::X86_64;
76 if (!Subtarget->is64Bit()) {
77 if (Subtarget->isTargetDarwin()) {
79 Flavour = DWARFFlavour::X86_32_DarwinEH;
81 Flavour = DWARFFlavour::X86_32_Generic;
82 } else if (Subtarget->isTargetCygMing()) {
83 // Unsupported by now, just quick fallback
84 Flavour = DWARFFlavour::X86_32_Generic;
86 Flavour = DWARFFlavour::X86_32_Generic;
90 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
93 /// getX86RegNum - This function maps LLVM register identifiers to their X86
94 /// specific numbering, which is used in various places encoding instructions.
95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
97 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
103 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
105 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
107 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
114 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
116 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
120 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
122 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
124 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129 return RegNo-X86::ST0;
131 case X86::XMM0: case X86::XMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9: case X86::MM1:
135 case X86::XMM2: case X86::XMM10: case X86::MM2:
137 case X86::XMM3: case X86::XMM11: case X86::MM3:
139 case X86::XMM4: case X86::XMM12: case X86::MM4:
141 case X86::XMM5: case X86::XMM13: case X86::MM5:
143 case X86::XMM6: case X86::XMM14: case X86::MM6:
145 case X86::XMM7: case X86::XMM15: case X86::MM7:
149 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
155 const TargetRegisterClass *
156 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157 const TargetRegisterClass *B,
158 unsigned SubIdx) const {
163 if (B == &X86::GR8RegClass) {
164 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
166 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168 A == &X86::GR64_NOREXRegClass ||
169 A == &X86::GR64_NOSPRegClass ||
170 A == &X86::GR64_NOREX_NOSPRegClass)
171 return &X86::GR64_ABCDRegClass;
172 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
173 A == &X86::GR32_NOREXRegClass ||
174 A == &X86::GR32_NOSPRegClass)
175 return &X86::GR32_ABCDRegClass;
176 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
177 A == &X86::GR16_NOREXRegClass)
178 return &X86::GR16_ABCDRegClass;
179 } else if (B == &X86::GR8_NOREXRegClass) {
180 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
181 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
182 return &X86::GR64_NOREXRegClass;
183 else if (A == &X86::GR64_ABCDRegClass)
184 return &X86::GR64_ABCDRegClass;
185 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
186 A == &X86::GR32_NOSPRegClass)
187 return &X86::GR32_NOREXRegClass;
188 else if (A == &X86::GR32_ABCDRegClass)
189 return &X86::GR32_ABCDRegClass;
190 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
191 return &X86::GR16_NOREXRegClass;
192 else if (A == &X86::GR16_ABCDRegClass)
193 return &X86::GR16_ABCDRegClass;
194 } else if (B == &X86::FR32RegClass) {
200 if (B == &X86::GR8_ABCD_HRegClass) {
201 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
202 A == &X86::GR64_NOREXRegClass ||
203 A == &X86::GR64_NOSPRegClass ||
204 A == &X86::GR64_NOREX_NOSPRegClass)
205 return &X86::GR64_ABCDRegClass;
206 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
207 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
208 return &X86::GR32_ABCDRegClass;
209 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
210 A == &X86::GR16_NOREXRegClass)
211 return &X86::GR16_ABCDRegClass;
212 } else if (B == &X86::FR64RegClass) {
218 if (B == &X86::GR16RegClass) {
219 if (A->getSize() == 4 || A->getSize() == 8)
221 } else if (B == &X86::GR16_ABCDRegClass) {
222 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
223 A == &X86::GR64_NOREXRegClass ||
224 A == &X86::GR64_NOSPRegClass ||
225 A == &X86::GR64_NOREX_NOSPRegClass)
226 return &X86::GR64_ABCDRegClass;
227 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
228 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
229 return &X86::GR32_ABCDRegClass;
230 } else if (B == &X86::GR16_NOREXRegClass) {
231 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
232 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
233 return &X86::GR64_NOREXRegClass;
234 else if (A == &X86::GR64_ABCDRegClass)
235 return &X86::GR64_ABCDRegClass;
236 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
237 A == &X86::GR32_NOSPRegClass)
238 return &X86::GR32_NOREXRegClass;
239 else if (A == &X86::GR32_ABCDRegClass)
240 return &X86::GR64_ABCDRegClass;
241 } else if (B == &X86::VR128RegClass) {
247 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
248 if (A->getSize() == 8)
250 } else if (B == &X86::GR32_ABCDRegClass) {
251 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
252 A == &X86::GR64_NOREXRegClass ||
253 A == &X86::GR64_NOSPRegClass ||
254 A == &X86::GR64_NOREX_NOSPRegClass)
255 return &X86::GR64_ABCDRegClass;
256 } else if (B == &X86::GR32_NOREXRegClass) {
257 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
258 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
259 return &X86::GR64_NOREXRegClass;
260 else if (A == &X86::GR64_ABCDRegClass)
261 return &X86::GR64_ABCDRegClass;
268 const TargetRegisterClass *
269 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
271 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
272 case 0: // Normal GPRs.
273 if (TM.getSubtarget<X86Subtarget>().is64Bit())
274 return &X86::GR64RegClass;
275 return &X86::GR32RegClass;
276 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
277 if (TM.getSubtarget<X86Subtarget>().is64Bit())
278 return &X86::GR64_NOSPRegClass;
279 return &X86::GR32_NOSPRegClass;
283 const TargetRegisterClass *
284 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
285 if (RC == &X86::CCRRegClass) {
287 return &X86::GR64RegClass;
289 return &X86::GR32RegClass;
295 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
296 bool callsEHReturn = false;
297 bool ghcCall = false;
300 const MachineFrameInfo *MFI = MF->getFrameInfo();
301 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
302 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
303 const Function *F = MF->getFunction();
304 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
307 static const unsigned GhcCalleeSavedRegs[] = {
311 static const unsigned CalleeSavedRegs32Bit[] = {
312 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
315 static const unsigned CalleeSavedRegs32EHRet[] = {
316 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
319 static const unsigned CalleeSavedRegs64Bit[] = {
320 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
323 static const unsigned CalleeSavedRegs64EHRet[] = {
324 X86::RAX, X86::RDX, X86::RBX, X86::R12,
325 X86::R13, X86::R14, X86::R15, X86::RBP, 0
328 static const unsigned CalleeSavedRegsWin64[] = {
329 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
330 X86::R12, X86::R13, X86::R14, X86::R15,
331 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
332 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
333 X86::XMM14, X86::XMM15, 0
337 return GhcCalleeSavedRegs;
338 } else if (Is64Bit) {
340 return CalleeSavedRegsWin64;
342 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
344 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
348 const TargetRegisterClass* const*
349 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
350 bool callsEHReturn = false;
353 const MachineFrameInfo *MFI = MF->getFrameInfo();
354 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
355 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
358 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
359 &X86::GR32RegClass, &X86::GR32RegClass,
360 &X86::GR32RegClass, &X86::GR32RegClass, 0
362 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
363 &X86::GR32RegClass, &X86::GR32RegClass,
364 &X86::GR32RegClass, &X86::GR32RegClass,
365 &X86::GR32RegClass, &X86::GR32RegClass, 0
367 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
368 &X86::GR64RegClass, &X86::GR64RegClass,
369 &X86::GR64RegClass, &X86::GR64RegClass,
370 &X86::GR64RegClass, &X86::GR64RegClass, 0
372 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
373 &X86::GR64RegClass, &X86::GR64RegClass,
374 &X86::GR64RegClass, &X86::GR64RegClass,
375 &X86::GR64RegClass, &X86::GR64RegClass,
376 &X86::GR64RegClass, &X86::GR64RegClass, 0
378 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
379 &X86::GR64RegClass, &X86::GR64RegClass,
380 &X86::GR64RegClass, &X86::GR64RegClass,
381 &X86::GR64RegClass, &X86::GR64RegClass,
382 &X86::GR64RegClass, &X86::GR64RegClass,
383 &X86::VR128RegClass, &X86::VR128RegClass,
384 &X86::VR128RegClass, &X86::VR128RegClass,
385 &X86::VR128RegClass, &X86::VR128RegClass,
386 &X86::VR128RegClass, &X86::VR128RegClass,
387 &X86::VR128RegClass, &X86::VR128RegClass, 0
392 return CalleeSavedRegClassesWin64;
394 return (callsEHReturn ?
395 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
397 return (callsEHReturn ?
398 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
402 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
403 BitVector Reserved(getNumRegs());
404 // Set the stack-pointer register and its aliases as reserved.
405 Reserved.set(X86::RSP);
406 Reserved.set(X86::ESP);
407 Reserved.set(X86::SP);
408 Reserved.set(X86::SPL);
410 // Set the instruction pointer register and its aliases as reserved.
411 Reserved.set(X86::RIP);
412 Reserved.set(X86::EIP);
413 Reserved.set(X86::IP);
415 // Set the frame-pointer register and its aliases as reserved if needed.
417 Reserved.set(X86::RBP);
418 Reserved.set(X86::EBP);
419 Reserved.set(X86::BP);
420 Reserved.set(X86::BPL);
423 // Mark the x87 stack registers as reserved, since they don't behave normally
424 // with respect to liveness. We don't fully model the effects of x87 stack
425 // pushes and pops after stackification.
426 Reserved.set(X86::ST0);
427 Reserved.set(X86::ST1);
428 Reserved.set(X86::ST2);
429 Reserved.set(X86::ST3);
430 Reserved.set(X86::ST4);
431 Reserved.set(X86::ST5);
432 Reserved.set(X86::ST6);
433 Reserved.set(X86::ST7);
437 //===----------------------------------------------------------------------===//
438 // Stack Frame Processing methods
439 //===----------------------------------------------------------------------===//
441 /// hasFP - Return true if the specified function should have a dedicated frame
442 /// pointer register. This is true if the function has variable sized allocas
443 /// or if frame pointer elimination is disabled.
444 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
445 const MachineFrameInfo *MFI = MF.getFrameInfo();
446 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
448 return (NoFramePointerElim ||
449 needsStackRealignment(MF) ||
450 MFI->hasVarSizedObjects() ||
451 MFI->isFrameAddressTaken() ||
452 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
453 (MMI && MMI->callsUnwindInit()));
456 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
457 const MachineFrameInfo *MFI = MF.getFrameInfo();
458 return (RealignStack &&
459 !MFI->hasVarSizedObjects());
462 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
463 const MachineFrameInfo *MFI = MF.getFrameInfo();
464 const Function *F = MF.getFunction();
465 bool requiresRealignment =
466 RealignStack && ((MFI->getMaxAlignment() > StackAlign) ||
467 F->hasFnAttr(Attribute::StackAlignment));
469 // FIXME: Currently we don't support stack realignment for functions with
470 // variable-sized allocas.
471 // FIXME: Temporary disable the error - it seems to be too conservative.
472 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
474 "Stack realignment in presense of dynamic allocas is not supported");
476 return (requiresRealignment && !MFI->hasVarSizedObjects());
479 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
480 return !MF.getFrameInfo()->hasVarSizedObjects();
483 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
484 int &FrameIdx) const {
485 if (Reg == FramePtr && hasFP(MF)) {
486 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
493 X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
494 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
495 const MachineFrameInfo *MFI = MF.getFrameInfo();
496 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
497 uint64_t StackSize = MFI->getStackSize();
499 if (needsStackRealignment(MF)) {
501 // Skip the saved EBP.
504 unsigned Align = MFI->getObjectAlignment(FI);
505 assert((-(Offset + StackSize)) % Align == 0);
507 return Offset + StackSize;
509 // FIXME: Support tail calls
512 return Offset + StackSize;
514 // Skip the saved EBP.
517 // Skip the RETADDR move area
518 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
519 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
520 if (TailCallReturnAddrDelta < 0)
521 Offset -= TailCallReturnAddrDelta;
527 void X86RegisterInfo::
528 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
529 MachineBasicBlock::iterator I) const {
530 if (!hasReservedCallFrame(MF)) {
531 // If the stack pointer can be changed after prologue, turn the
532 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
533 // adjcallstackdown instruction into 'add ESP, <amt>'
534 // TODO: consider using push / pop instead of sub + store / add
535 MachineInstr *Old = I;
536 uint64_t Amount = Old->getOperand(0).getImm();
538 // We need to keep the stack aligned properly. To do this, we round the
539 // amount of space needed for the outgoing arguments up to the next
540 // alignment boundary.
541 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
543 MachineInstr *New = 0;
544 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
545 New = BuildMI(MF, Old->getDebugLoc(),
546 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
551 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
553 // Factor out the amount the callee already popped.
554 uint64_t CalleeAmt = Old->getOperand(1).getImm();
558 unsigned Opc = (Amount < 128) ?
559 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
560 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
561 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
568 // The EFLAGS implicit def is dead.
569 New->getOperand(3).setIsDead();
571 // Replace the pseudo instruction with a new instruction.
575 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
576 // If we are performing frame pointer elimination and if the callee pops
577 // something off the stack pointer, add it back. We do this until we have
578 // more advanced stack pointer tracking ability.
579 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
580 unsigned Opc = (CalleeAmt < 128) ?
581 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
582 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
583 MachineInstr *Old = I;
585 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
590 // The EFLAGS implicit def is dead.
591 New->getOperand(3).setIsDead();
600 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
601 int SPAdj, FrameIndexValue *Value,
602 RegScavenger *RS) const{
603 assert(SPAdj == 0 && "Unexpected");
606 MachineInstr &MI = *II;
607 MachineFunction &MF = *MI.getParent()->getParent();
609 while (!MI.getOperand(i).isFI()) {
611 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
614 int FrameIndex = MI.getOperand(i).getIndex();
617 if (needsStackRealignment(MF))
618 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
620 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
622 // This must be part of a four operand memory reference. Replace the
623 // FrameIndex with base register with EBP. Add an offset to the offset.
624 MI.getOperand(i).ChangeToRegister(BasePtr, false);
626 // Now add the frame object offset to the offset from EBP.
627 if (MI.getOperand(i+3).isImm()) {
628 // Offset is a 32-bit integer.
629 int Offset = getFrameIndexOffset(MF, FrameIndex) +
630 (int)(MI.getOperand(i + 3).getImm());
632 MI.getOperand(i + 3).ChangeToImmediate(Offset);
634 // Offset is symbolic. This is extremely rare.
635 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
636 (uint64_t)MI.getOperand(i+3).getOffset();
637 MI.getOperand(i+3).setOffset(Offset);
643 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
644 RegScavenger *RS) const {
645 MachineFrameInfo *MFI = MF.getFrameInfo();
647 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
648 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
650 if (TailCallReturnAddrDelta < 0) {
651 // create RETURNADDR area
660 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
661 (-1U*SlotSize)+TailCallReturnAddrDelta,
666 assert((TailCallReturnAddrDelta <= 0) &&
667 "The Delta should always be zero or negative");
668 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
670 // Create a frame entry for the EBP register that must be saved.
671 int FrameIdx = MFI->CreateFixedObject(SlotSize,
673 TFI.getOffsetOfLocalArea() +
674 TailCallReturnAddrDelta,
676 assert(FrameIdx == MFI->getObjectIndexBegin() &&
677 "Slot for EBP register must be last in order to be found!");
682 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
683 /// stack pointer by a constant value.
685 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
686 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
687 const TargetInstrInfo &TII) {
688 bool isSub = NumBytes < 0;
689 uint64_t Offset = isSub ? -NumBytes : NumBytes;
692 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
693 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
695 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
696 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
697 uint64_t Chunk = (1LL << 31) - 1;
698 DebugLoc DL = MBB.findDebugLoc(MBBI);
701 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
703 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
706 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
711 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
713 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
714 unsigned StackPtr, uint64_t *NumBytes = NULL) {
715 if (MBBI == MBB.begin()) return;
717 MachineBasicBlock::iterator PI = prior(MBBI);
718 unsigned Opc = PI->getOpcode();
719 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
720 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
721 PI->getOperand(0).getReg() == StackPtr) {
723 *NumBytes += PI->getOperand(2).getImm();
725 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
726 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
727 PI->getOperand(0).getReg() == StackPtr) {
729 *NumBytes -= PI->getOperand(2).getImm();
734 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
736 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
737 MachineBasicBlock::iterator &MBBI,
738 unsigned StackPtr, uint64_t *NumBytes = NULL) {
739 // FIXME: THIS ISN'T RUN!!!
742 if (MBBI == MBB.end()) return;
744 MachineBasicBlock::iterator NI = llvm::next(MBBI);
745 if (NI == MBB.end()) return;
747 unsigned Opc = NI->getOpcode();
748 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
749 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
750 NI->getOperand(0).getReg() == StackPtr) {
752 *NumBytes -= NI->getOperand(2).getImm();
755 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
756 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
757 NI->getOperand(0).getReg() == StackPtr) {
759 *NumBytes += NI->getOperand(2).getImm();
765 /// mergeSPUpdates - Checks the instruction before/after the passed
766 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
767 /// stack adjustment is returned as a positive value for ADD and a negative for
769 static int mergeSPUpdates(MachineBasicBlock &MBB,
770 MachineBasicBlock::iterator &MBBI,
772 bool doMergeWithPrevious) {
773 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
774 (!doMergeWithPrevious && MBBI == MBB.end()))
777 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
778 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
779 unsigned Opc = PI->getOpcode();
782 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
783 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
784 PI->getOperand(0).getReg() == StackPtr){
785 Offset += PI->getOperand(2).getImm();
787 if (!doMergeWithPrevious) MBBI = NI;
788 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
789 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
790 PI->getOperand(0).getReg() == StackPtr) {
791 Offset -= PI->getOperand(2).getImm();
793 if (!doMergeWithPrevious) MBBI = NI;
799 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
801 unsigned FramePtr) const {
802 MachineFrameInfo *MFI = MF.getFrameInfo();
803 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
806 // Add callee saved registers to move list.
807 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
808 if (CSI.empty()) return;
810 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
811 const TargetData *TD = MF.getTarget().getTargetData();
812 bool HasFP = hasFP(MF);
814 // Calculate amount of bytes used for return address storing.
816 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
817 TargetFrameInfo::StackGrowsUp ?
818 TD->getPointerSize() : -TD->getPointerSize());
820 // FIXME: This is dirty hack. The code itself is pretty mess right now.
821 // It should be rewritten from scratch and generalized sometimes.
823 // Determine maximum offset (minumum due to stack growth).
824 int64_t MaxOffset = 0;
825 for (std::vector<CalleeSavedInfo>::const_iterator
826 I = CSI.begin(), E = CSI.end(); I != E; ++I)
827 MaxOffset = std::min(MaxOffset,
828 MFI->getObjectOffset(I->getFrameIdx()));
830 // Calculate offsets.
831 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
832 for (std::vector<CalleeSavedInfo>::const_iterator
833 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
834 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
835 unsigned Reg = I->getReg();
836 Offset = MaxOffset - Offset + saveAreaOffset;
838 // Don't output a new machine move if we're re-saving the frame
839 // pointer. This happens when the PrologEpilogInserter has inserted an extra
840 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
841 // generates one when frame pointers are used. If we generate a "machine
842 // move" for this extra "PUSH", the linker will lose track of the fact that
843 // the frame pointer should have the value of the first "PUSH" when it's
846 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
847 // another bug. I.e., one where we generate a prolog like this:
855 // The immediate re-push of EBP is unnecessary. At the least, it's an
856 // optimization bug. EBP can be used as a scratch register in certain
857 // cases, but probably not when we have a frame pointer.
858 if (HasFP && FramePtr == Reg)
861 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
862 MachineLocation CSSrc(Reg);
863 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
867 /// emitPrologue - Push callee-saved registers onto the stack, which
868 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
869 /// space for local variables. Also emit labels used by the exception handler to
870 /// generate the exception handling frames.
871 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
872 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
873 MachineBasicBlock::iterator MBBI = MBB.begin();
874 MachineFrameInfo *MFI = MF.getFrameInfo();
875 const Function *Fn = MF.getFunction();
876 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
877 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
878 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
879 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
880 !Fn->doesNotThrow() || UnwindTablesMandatory;
881 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
882 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
883 bool HasFP = hasFP(MF);
886 // Add RETADDR move area to callee saved frame size.
887 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
888 if (TailCallReturnAddrDelta < 0)
889 X86FI->setCalleeSavedFrameSize(
890 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
892 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
893 // function, and use up to 128 bytes of stack space, don't have a frame
894 // pointer, calls, or dynamic alloca then we do not need to adjust the
895 // stack pointer (we fit in the Red Zone).
896 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
897 !needsStackRealignment(MF) &&
898 !MFI->hasVarSizedObjects() && // No dynamic alloca.
899 !MFI->hasCalls() && // No calls.
900 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
901 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
902 if (HasFP) MinSize += SlotSize;
903 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
904 MFI->setStackSize(StackSize);
905 } else if (Subtarget->isTargetWin64()) {
906 // We need to always allocate 32 bytes as register spill area.
907 // FIXME: We might reuse these 32 bytes for leaf functions.
909 MFI->setStackSize(StackSize);
912 // Insert stack pointer adjustment for later moving of return addr. Only
913 // applies to tail call optimized functions where the callee argument stack
914 // size is bigger than the callers.
915 if (TailCallReturnAddrDelta < 0) {
917 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
920 .addImm(-TailCallReturnAddrDelta);
921 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
924 // Mapping for machine moves:
926 // DST: VirtualFP AND
927 // SRC: VirtualFP => DW_CFA_def_cfa_offset
928 // ELSE => DW_CFA_def_cfa
930 // SRC: VirtualFP AND
931 // DST: Register => DW_CFA_def_cfa_register
934 // OFFSET < 0 => DW_CFA_offset_extended_sf
935 // REG < 64 => DW_CFA_offset + Reg
936 // ELSE => DW_CFA_offset_extended
938 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
939 const TargetData *TD = MF.getTarget().getTargetData();
940 uint64_t NumBytes = 0;
942 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
943 TargetFrameInfo::StackGrowsUp ?
944 TD->getPointerSize() : -TD->getPointerSize());
947 // Calculate required stack adjustment.
948 uint64_t FrameSize = StackSize - SlotSize;
949 if (needsStackRealignment(MF))
950 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
952 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
954 // Get the offset of the stack slot for the EBP register, which is
955 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
956 // Update the frame offset adjustment.
957 MFI->setOffsetAdjustment(-NumBytes);
959 // Save EBP/RBP into the appropriate stack slot.
960 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
961 .addReg(FramePtr, RegState::Kill);
963 if (needsFrameMoves) {
964 // Mark the place where EBP/RBP was saved.
965 unsigned FrameLabelId = MMI->NextLabelID();
966 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
968 // Define the current CFA rule to use the provided offset.
970 MachineLocation SPDst(MachineLocation::VirtualFP);
971 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
972 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
974 // FIXME: Verify & implement for FP
975 MachineLocation SPDst(StackPtr);
976 MachineLocation SPSrc(StackPtr, stackGrowth);
977 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
980 // Change the rule for the FramePtr to be an "offset" rule.
981 MachineLocation FPDst(MachineLocation::VirtualFP,
983 MachineLocation FPSrc(FramePtr);
984 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
987 // Update EBP with the new base value...
988 BuildMI(MBB, MBBI, DL,
989 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
992 if (needsFrameMoves) {
993 // Mark effective beginning of when frame pointer becomes valid.
994 unsigned FrameLabelId = MMI->NextLabelID();
995 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
997 // Define the current CFA to use the EBP/RBP register.
998 MachineLocation FPDst(FramePtr);
999 MachineLocation FPSrc(MachineLocation::VirtualFP);
1000 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1003 // Mark the FramePtr as live-in in every block except the entry.
1004 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
1006 I->addLiveIn(FramePtr);
1009 if (needsStackRealignment(MF)) {
1011 BuildMI(MBB, MBBI, DL,
1012 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1013 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1015 // The EFLAGS implicit def is dead.
1016 MI->getOperand(3).setIsDead();
1019 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1022 // Skip the callee-saved push instructions.
1023 bool PushedRegs = false;
1024 int StackOffset = 2 * stackGrowth;
1026 while (MBBI != MBB.end() &&
1027 (MBBI->getOpcode() == X86::PUSH32r ||
1028 MBBI->getOpcode() == X86::PUSH64r)) {
1032 if (!HasFP && needsFrameMoves) {
1033 // Mark callee-saved push instruction.
1034 unsigned LabelId = MMI->NextLabelID();
1035 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1037 // Define the current CFA rule to use the provided offset.
1038 unsigned Ptr = StackSize ?
1039 MachineLocation::VirtualFP : StackPtr;
1040 MachineLocation SPDst(Ptr);
1041 MachineLocation SPSrc(Ptr, StackOffset);
1042 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1043 StackOffset += stackGrowth;
1047 DL = MBB.findDebugLoc(MBBI);
1049 // Adjust stack pointer: ESP -= numbytes.
1050 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1051 // Check, whether EAX is livein for this function.
1052 bool isEAXAlive = false;
1053 for (MachineRegisterInfo::livein_iterator
1054 II = MF.getRegInfo().livein_begin(),
1055 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1056 unsigned Reg = II->first;
1057 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1058 Reg == X86::AH || Reg == X86::AL);
1061 // Function prologue calls _alloca to probe the stack when allocating more
1062 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1063 // to ensure that the guard pages used by the OS virtual memory manager are
1064 // allocated in correct sequence.
1066 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1068 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1069 .addExternalSymbol("_alloca")
1070 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1073 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1074 .addReg(X86::EAX, RegState::Kill);
1076 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1077 // allocated bytes for EAX.
1078 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1079 .addImm(NumBytes - 4);
1080 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1081 .addExternalSymbol("_alloca")
1082 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1085 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1087 StackPtr, false, NumBytes - 4);
1088 MBB.insert(MBBI, MI);
1090 } else if (NumBytes) {
1091 // If there is an SUB32ri of ESP immediately before this instruction, merge
1092 // the two. This can be the case when tail call elimination is enabled and
1093 // the callee has more arguments then the caller.
1094 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1096 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1097 // instruction, merge the two instructions.
1098 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1101 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1104 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1105 // Mark end of stack pointer adjustment.
1106 unsigned LabelId = MMI->NextLabelID();
1107 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1109 if (!HasFP && NumBytes) {
1110 // Define the current CFA rule to use the provided offset.
1112 MachineLocation SPDst(MachineLocation::VirtualFP);
1113 MachineLocation SPSrc(MachineLocation::VirtualFP,
1114 -StackSize + stackGrowth);
1115 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1117 // FIXME: Verify & implement for FP
1118 MachineLocation SPDst(StackPtr);
1119 MachineLocation SPSrc(StackPtr, stackGrowth);
1120 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1124 // Emit DWARF info specifying the offsets of the callee-saved registers.
1126 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1130 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1131 MachineBasicBlock &MBB) const {
1132 const MachineFrameInfo *MFI = MF.getFrameInfo();
1133 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1134 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1135 unsigned RetOpcode = MBBI->getOpcode();
1136 DebugLoc DL = MBBI->getDebugLoc();
1138 switch (RetOpcode) {
1140 llvm_unreachable("Can only insert epilog into returning blocks");
1143 case X86::TCRETURNdi:
1144 case X86::TCRETURNri:
1145 case X86::TCRETURNri64:
1146 case X86::TCRETURNdi64:
1147 case X86::EH_RETURN:
1148 case X86::EH_RETURN64:
1152 break; // These are ok
1155 // Get the number of bytes to allocate from the FrameInfo.
1156 uint64_t StackSize = MFI->getStackSize();
1157 uint64_t MaxAlign = MFI->getMaxAlignment();
1158 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1159 uint64_t NumBytes = 0;
1162 // Calculate required stack adjustment.
1163 uint64_t FrameSize = StackSize - SlotSize;
1164 if (needsStackRealignment(MF))
1165 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1167 NumBytes = FrameSize - CSSize;
1170 BuildMI(MBB, MBBI, DL,
1171 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1173 NumBytes = StackSize - CSSize;
1176 // Skip the callee-saved pop instructions.
1177 MachineBasicBlock::iterator LastCSPop = MBBI;
1178 while (MBBI != MBB.begin()) {
1179 MachineBasicBlock::iterator PI = prior(MBBI);
1180 unsigned Opc = PI->getOpcode();
1182 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1183 !PI->getDesc().isTerminator())
1189 DL = MBBI->getDebugLoc();
1191 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1192 // instruction, merge the two instructions.
1193 if (NumBytes || MFI->hasVarSizedObjects())
1194 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1196 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1197 // slot before popping them off! Same applies for the case, when stack was
1199 if (needsStackRealignment(MF)) {
1200 // We cannot use LEA here, because stack pointer was realigned. We need to
1201 // deallocate local frame back.
1203 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1204 MBBI = prior(LastCSPop);
1207 BuildMI(MBB, MBBI, DL,
1208 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1209 StackPtr).addReg(FramePtr);
1210 } else if (MFI->hasVarSizedObjects()) {
1212 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1214 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1215 FramePtr, false, -CSSize);
1216 MBB.insert(MBBI, MI);
1218 BuildMI(MBB, MBBI, DL,
1219 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1222 } else if (NumBytes) {
1223 // Adjust stack pointer back: ESP += numbytes.
1224 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1227 // We're returning from function via eh_return.
1228 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1229 MBBI = prior(MBB.end());
1230 MachineOperand &DestAddr = MBBI->getOperand(0);
1231 assert(DestAddr.isReg() && "Offset should be in register!");
1232 BuildMI(MBB, MBBI, DL,
1233 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1234 StackPtr).addReg(DestAddr.getReg());
1235 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1236 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1237 // Tail call return: adjust the stack pointer and jump to callee.
1238 MBBI = prior(MBB.end());
1239 MachineOperand &JumpTarget = MBBI->getOperand(0);
1240 MachineOperand &StackAdjust = MBBI->getOperand(1);
1241 assert(StackAdjust.isImm() && "Expecting immediate value.");
1243 // Adjust stack pointer.
1244 int StackAdj = StackAdjust.getImm();
1245 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1247 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1249 // Incoporate the retaddr area.
1250 Offset = StackAdj-MaxTCDelta;
1251 assert(Offset >= 0 && "Offset should never be negative");
1254 // Check for possible merge with preceeding ADD instruction.
1255 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1256 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1259 // Jump to label or value in register.
1260 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64) {
1261 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1262 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1263 JumpTarget.getTargetFlags());
1264 } else if (RetOpcode == X86::TCRETURNri64) {
1265 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1267 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1270 MachineInstr *NewMI = prior(MBBI);
1271 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1272 NewMI->addOperand(MBBI->getOperand(i));
1274 // Delete the pseudo instruction TCRETURN.
1276 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1277 (X86FI->getTCReturnAddrDelta() < 0)) {
1278 // Add the return addr area delta back since we are not tail calling.
1279 int delta = -1*X86FI->getTCReturnAddrDelta();
1280 MBBI = prior(MBB.end());
1282 // Check for possible merge with preceeding ADD instruction.
1283 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1284 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1288 unsigned X86RegisterInfo::getRARegister() const {
1289 return Is64Bit ? X86::RIP // Should have dwarf #16.
1290 : X86::EIP; // Should have dwarf #8.
1293 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1294 return hasFP(MF) ? FramePtr : StackPtr;
1298 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1299 // Calculate amount of bytes used for return address storing
1300 int stackGrowth = (Is64Bit ? -8 : -4);
1302 // Initial state of the frame pointer is esp+4.
1303 MachineLocation Dst(MachineLocation::VirtualFP);
1304 MachineLocation Src(StackPtr, stackGrowth);
1305 Moves.push_back(MachineMove(0, Dst, Src));
1307 // Add return address to move list
1308 MachineLocation CSDst(StackPtr, stackGrowth);
1309 MachineLocation CSSrc(getRARegister());
1310 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1313 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1314 llvm_unreachable("What is the exception register");
1318 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1319 llvm_unreachable("What is the exception handler register");
1324 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1325 switch (VT.getSimpleVT().SimpleTy) {
1326 default: return Reg;
1331 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1333 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1335 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1337 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1343 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1345 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1347 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1349 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1351 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1353 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1355 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1357 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1359 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1361 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1363 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1365 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1367 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1369 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1371 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1373 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1379 default: return Reg;
1380 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1382 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1384 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1386 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1388 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1390 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1392 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1394 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1396 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1398 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1400 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1402 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1404 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1406 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1408 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1410 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1415 default: return Reg;
1416 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1418 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1420 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1422 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1424 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1426 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1428 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1430 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1432 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1434 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1436 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1438 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1440 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1442 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1444 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1446 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1451 default: return Reg;
1452 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1454 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1456 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1458 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1460 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1462 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1464 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1466 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1468 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1470 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1472 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1474 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1476 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1478 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1480 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1482 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1491 #include "X86GenRegisterInfo.inc"