1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "Support/CommandLine.h"
27 #include "Support/STLExtras.h"
32 NoFPElim("disable-fp-elim",
33 cl::desc("Disable frame pointer elimination optimization"));
36 X86RegisterInfo::X86RegisterInfo()
37 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
39 static unsigned getIdx(const TargetRegisterClass *RC) {
40 switch (RC->getSize()) {
41 default: assert(0 && "Invalid data size!");
49 int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MI,
51 unsigned SrcReg, int FrameIdx,
52 const TargetRegisterClass *RC) const {
53 static const unsigned Opcode[] =
54 { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 };
55 MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
56 FrameIdx).addReg(SrcReg);
61 int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MI,
63 unsigned DestReg, int FrameIdx,
64 const TargetRegisterClass *RC) const{
65 static const unsigned Opcode[] =
66 { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 };
67 unsigned OC = Opcode[getIdx(RC)];
68 MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
72 int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MI,
74 unsigned DestReg, unsigned SrcReg,
75 const TargetRegisterClass *RC) const {
76 static const unsigned Opcode[] =
77 { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
78 MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
82 //===----------------------------------------------------------------------===//
83 // Stack Frame Processing methods
84 //===----------------------------------------------------------------------===//
86 // hasFP - Return true if the specified function should have a dedicated frame
87 // pointer register. This is true if the function has variable sized allocas or
88 // if frame pointer elimination is disabled.
90 static bool hasFP(MachineFunction &MF) {
91 return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
94 void X86RegisterInfo::
95 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator I) const {
98 // If we have a frame pointer, turn the adjcallstackup instruction into a
99 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
101 MachineInstr *Old = I;
102 unsigned Amount = Old->getOperand(0).getImmedValue();
104 // We need to keep the stack aligned properly. To do this, we round the
105 // amount of space needed for the outgoing arguments up to the next
106 // alignment boundary.
107 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
108 Amount = (Amount+Align-1)/Align*Align;
111 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
112 New=BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
114 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
115 New=BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
118 // Replace the pseudo instruction with a new instruction...
126 void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
127 MachineBasicBlock::iterator II) const {
129 MachineInstr &MI = *II;
130 while (!MI.getOperand(i).isFrameIndex()) {
132 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
135 int FrameIndex = MI.getOperand(i).getFrameIndex();
137 // This must be part of a four operand memory reference. Replace the
138 // FrameIndex with base register with EBP. Add add an offset to the offset.
139 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
141 // Now add the frame object offset to the offset from EBP.
142 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
143 MI.getOperand(i+3).getImmedValue()+4;
146 Offset += MF.getFrameInfo()->getStackSize();
148 Offset += 4; // Skip the saved EBP
150 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
154 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
156 // Create a frame entry for the EBP register that must be saved.
157 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
158 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
159 "Slot for EBP register must be last in order to be found!");
163 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
164 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
165 MachineBasicBlock::iterator MBBI = MBB.begin();
166 MachineFrameInfo *MFI = MF.getFrameInfo();
169 // Get the number of bytes to allocate from the FrameInfo
170 unsigned NumBytes = MFI->getStackSize();
172 // Get the offset of the stack slot for the EBP register... which is
173 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
174 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
176 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
177 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
178 MBB.insert(MBBI, MI);
181 // Save EBP into the appropriate stack slot...
182 MI = addRegOffset(BuildMI(X86::MOVrm32, 5), // mov [ESP-<offset>], EBP
183 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
184 MBB.insert(MBBI, MI);
186 // Update EBP with the new base value...
187 if (NumBytes == 4) // mov EBP, ESP
188 MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
189 else // lea EBP, [ESP+StackSize]
190 MI = addRegOffset(BuildMI(X86::LEAr32, 5, X86::EBP), X86::ESP,NumBytes-4);
192 MBB.insert(MBBI, MI);
195 if (MFI->hasCalls()) {
196 // When we have no frame pointer, we reserve argument space for call sites
197 // in the function immediately on entry to the current function. This
198 // eliminates the need for add/sub ESP brackets around call sites.
200 NumBytes += MFI->getMaxCallFrameSize();
202 // Round the size to a multiple of the alignment (don't forget the 4 byte
204 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
205 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
208 // Update frame info to pretend that this is part of the stack...
209 MFI->setStackSize(NumBytes);
212 // adjust stack pointer: ESP -= numbytes
213 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
214 MBB.insert(MBBI, MI);
219 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
220 MachineBasicBlock &MBB) const {
221 const MachineFrameInfo *MFI = MF.getFrameInfo();
222 MachineBasicBlock::iterator MBBI = prior(MBB.end());
224 assert(MBBI->getOpcode() == X86::RET &&
225 "Can only insert epilog into returning blocks");
228 // Get the offset of the stack slot for the EBP register... which is
229 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
230 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
233 MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
234 MBB.insert(MBBI, MI);
237 MI = BuildMI(X86::POPr32, 0, X86::EBP);
238 MBB.insert(MBBI, MI);
240 // Get the number of bytes allocated from the FrameInfo...
241 unsigned NumBytes = MFI->getStackSize();
243 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
244 MI =BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
245 MBB.insert(MBBI, MI);
250 #include "X86GenRegisterInfo.inc"
252 const TargetRegisterClass*
253 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
254 switch (Ty->getPrimitiveID()) {
256 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
257 default: assert(0 && "Invalid type to getClass!");
259 case Type::SByteTyID:
260 case Type::UByteTyID: return &R8Instance;
261 case Type::ShortTyID:
262 case Type::UShortTyID: return &R16Instance;
265 case Type::PointerTyID: return &R32Instance;
267 case Type::FloatTyID:
268 case Type::DoubleTyID: return &RFPInstance;