1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/MachineValueType.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
48 ForceStackAlign("force-align-stack",
49 cl::desc("Force align the stack to the minimum alignment"
50 " needed for the function."),
51 cl::init(false), cl::Hidden);
54 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
57 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm)
58 : X86GenRegisterInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
59 ? X86::RIP : X86::EIP),
60 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
61 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true),
62 (tm.getSubtarget<X86Subtarget>().is64Bit()
63 ? X86::RIP : X86::EIP)),
65 X86_MC::InitLLVM2SEHRegisterMapping(this);
67 // Cache some information.
68 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
69 Is64Bit = Subtarget->is64Bit();
70 IsWin64 = Subtarget->isTargetWin64();
81 // Use a callee-saved register as the base pointer. These registers must
82 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
83 // requires GOT in the EBX register before function calls via PLT GOT pointer.
84 BasePtr = Is64Bit ? X86::RBX : X86::ESI;
87 /// getCompactUnwindRegNum - This function maps the register to the number for
88 /// compact unwind encoding. Return -1 if the register isn't valid.
89 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
90 switch (getLLVMRegNum(RegNum, isEH)) {
91 case X86::EBX: case X86::RBX: return 1;
92 case X86::ECX: case X86::R12: return 2;
93 case X86::EDX: case X86::R13: return 3;
94 case X86::EDI: case X86::R14: return 4;
95 case X86::ESI: case X86::R15: return 5;
96 case X86::EBP: case X86::RBP: return 6;
103 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
104 // ExeDepsFixer and PostRAScheduler require liveness.
109 X86RegisterInfo::getSEHRegNum(unsigned i) const {
110 return getEncodingValue(i);
113 const TargetRegisterClass *
114 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
115 unsigned Idx) const {
116 // The sub_8bit sub-register index is more constrained in 32-bit mode.
117 // It behaves just like the sub_8bit_hi index.
118 if (!Is64Bit && Idx == X86::sub_8bit)
119 Idx = X86::sub_8bit_hi;
121 // Forward to TableGen's default version.
122 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
125 const TargetRegisterClass *
126 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
127 const TargetRegisterClass *B,
128 unsigned SubIdx) const {
129 // The sub_8bit sub-register index is more constrained in 32-bit mode.
130 if (!Is64Bit && SubIdx == X86::sub_8bit) {
131 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
135 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
138 const TargetRegisterClass*
139 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
140 // Don't allow super-classes of GR8_NOREX. This class is only used after
141 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
142 // to the full GR8 register class in 64-bit mode, so we cannot allow the
143 // reigster class inflation.
145 // The GR8_NOREX class is always used in a way that won't be constrained to a
146 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
148 if (RC == &X86::GR8_NOREXRegClass)
151 const TargetRegisterClass *Super = RC;
152 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
154 switch (Super->getID()) {
155 case X86::GR8RegClassID:
156 case X86::GR16RegClassID:
157 case X86::GR32RegClassID:
158 case X86::GR64RegClassID:
159 case X86::FR32RegClassID:
160 case X86::FR64RegClassID:
161 case X86::RFP32RegClassID:
162 case X86::RFP64RegClassID:
163 case X86::RFP80RegClassID:
164 case X86::VR128RegClassID:
165 case X86::VR256RegClassID:
166 // Don't return a super-class that would shrink the spill size.
167 // That can happen with the vector and float classes.
168 if (Super->getSize() == RC->getSize())
176 const TargetRegisterClass *
177 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
179 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
181 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
182 case 0: // Normal GPRs.
183 if (Subtarget.isTarget64BitLP64())
184 return &X86::GR64RegClass;
185 return &X86::GR32RegClass;
186 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
187 if (Subtarget.isTarget64BitLP64())
188 return &X86::GR64_NOSPRegClass;
189 return &X86::GR32_NOSPRegClass;
190 case 2: // Available for tailcall (not callee-saved GPRs).
191 if (Subtarget.isTargetWin64())
192 return &X86::GR64_TCW64RegClass;
193 else if (Subtarget.is64Bit())
194 return &X86::GR64_TCRegClass;
196 const Function *F = MF.getFunction();
197 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
199 return &X86::GR32RegClass;
200 return &X86::GR32_TCRegClass;
204 const TargetRegisterClass *
205 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
206 if (RC == &X86::CCRRegClass) {
208 return &X86::GR64RegClass;
210 return &X86::GR32RegClass;
216 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
217 MachineFunction &MF) const {
218 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
220 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
221 switch (RC->getID()) {
224 case X86::GR32RegClassID:
226 case X86::GR64RegClassID:
228 case X86::VR128RegClassID:
229 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
230 case X86::VR64RegClassID:
236 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
237 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
238 bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
240 assert(MF && "MachineFunction required");
241 switch (MF->getFunction()->getCallingConv()) {
242 case CallingConv::GHC:
243 case CallingConv::HiPE:
244 return CSR_NoRegs_SaveList;
245 case CallingConv::AnyReg:
247 return CSR_64_AllRegs_AVX_SaveList;
248 return CSR_64_AllRegs_SaveList;
249 case CallingConv::PreserveMost:
250 return CSR_64_RT_MostRegs_SaveList;
251 case CallingConv::PreserveAll:
253 return CSR_64_RT_AllRegs_AVX_SaveList;
254 return CSR_64_RT_AllRegs_SaveList;
255 case CallingConv::Intel_OCL_BI: {
256 if (HasAVX512 && IsWin64)
257 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
258 if (HasAVX512 && Is64Bit)
259 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
260 if (HasAVX && IsWin64)
261 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
262 if (HasAVX && Is64Bit)
263 return CSR_64_Intel_OCL_BI_AVX_SaveList;
264 if (!HasAVX && !IsWin64 && Is64Bit)
265 return CSR_64_Intel_OCL_BI_SaveList;
268 case CallingConv::Cold:
270 return CSR_64_MostRegs_SaveList;
276 bool CallsEHReturn = MF->getMMI().callsEHReturn();
279 return CSR_Win64_SaveList;
281 return CSR_64EHRet_SaveList;
282 return CSR_64_SaveList;
285 return CSR_32EHRet_SaveList;
286 return CSR_32_SaveList;
290 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
291 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
292 bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
295 case CallingConv::GHC:
296 case CallingConv::HiPE:
297 return CSR_NoRegs_RegMask;
298 case CallingConv::AnyReg:
300 return CSR_64_AllRegs_AVX_RegMask;
301 return CSR_64_AllRegs_RegMask;
302 case CallingConv::PreserveMost:
303 return CSR_64_RT_MostRegs_RegMask;
304 case CallingConv::PreserveAll:
306 return CSR_64_RT_AllRegs_AVX_RegMask;
307 return CSR_64_RT_AllRegs_RegMask;
308 case CallingConv::Intel_OCL_BI: {
309 if (HasAVX512 && IsWin64)
310 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
311 if (HasAVX512 && Is64Bit)
312 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
313 if (HasAVX && IsWin64)
314 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
315 if (HasAVX && Is64Bit)
316 return CSR_64_Intel_OCL_BI_AVX_RegMask;
317 if (!HasAVX && !IsWin64 && Is64Bit)
318 return CSR_64_Intel_OCL_BI_RegMask;
321 case CallingConv::Cold:
323 return CSR_64_MostRegs_RegMask;
329 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
333 return CSR_Win64_RegMask;
334 return CSR_64_RegMask;
336 return CSR_32_RegMask;
340 X86RegisterInfo::getNoPreservedMask() const {
341 return CSR_NoRegs_RegMask;
344 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
345 BitVector Reserved(getNumRegs());
346 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
348 // Set the stack-pointer register and its aliases as reserved.
349 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
353 // Set the instruction pointer register and its aliases as reserved.
354 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
358 // Set the frame-pointer register and its aliases as reserved if needed.
359 if (TFI->hasFP(MF)) {
360 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
365 // Set the base-pointer register and its aliases as reserved if needed.
366 if (hasBasePointer(MF)) {
367 CallingConv::ID CC = MF.getFunction()->getCallingConv();
368 const uint32_t* RegMask = getCallPreservedMask(CC);
369 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
371 "Stack realignment in presence of dynamic allocas is not supported with"
372 "this calling convention.");
374 for (MCSubRegIterator I(getBaseRegister(), this, /*IncludeSelf=*/true);
379 // Mark the segment registers as reserved.
380 Reserved.set(X86::CS);
381 Reserved.set(X86::SS);
382 Reserved.set(X86::DS);
383 Reserved.set(X86::ES);
384 Reserved.set(X86::FS);
385 Reserved.set(X86::GS);
387 // Mark the floating point stack registers as reserved.
388 for (unsigned n = 0; n != 8; ++n)
389 Reserved.set(X86::ST0 + n);
391 // Reserve the registers that only exist in 64-bit mode.
393 // These 8-bit registers are part of the x86-64 extension even though their
394 // super-registers are old 32-bits.
395 Reserved.set(X86::SIL);
396 Reserved.set(X86::DIL);
397 Reserved.set(X86::BPL);
398 Reserved.set(X86::SPL);
400 for (unsigned n = 0; n != 8; ++n) {
402 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
406 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
410 if (!Is64Bit || !TM.getSubtarget<X86Subtarget>().hasAVX512()) {
411 for (unsigned n = 16; n != 32; ++n) {
412 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
420 //===----------------------------------------------------------------------===//
421 // Stack Frame Processing methods
422 //===----------------------------------------------------------------------===//
424 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
425 const MachineFrameInfo *MFI = MF.getFrameInfo();
427 if (!EnableBasePointer)
430 // When we need stack realignment, we can't address the stack from the frame
431 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
432 // can't address variables from the stack pointer. MS inline asm can
433 // reference locals while also adjusting the stack pointer. When we can't
434 // use both the SP and the FP, we need a separate base pointer register.
435 bool CantUseFP = needsStackRealignment(MF);
437 MFI->hasVarSizedObjects() || MFI->hasInlineAsmWithSPAdjust();
438 return CantUseFP && CantUseSP;
441 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
442 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
445 const MachineFrameInfo *MFI = MF.getFrameInfo();
446 const MachineRegisterInfo *MRI = &MF.getRegInfo();
448 // Stack realignment requires a frame pointer. If we already started
449 // register allocation with frame pointer elimination, it is too late now.
450 if (!MRI->canReserveReg(FramePtr))
453 // If a base pointer is necessary. Check that it isn't too late to reserve
455 if (MFI->hasVarSizedObjects())
456 return MRI->canReserveReg(BasePtr);
460 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
461 const MachineFrameInfo *MFI = MF.getFrameInfo();
462 const Function *F = MF.getFunction();
463 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
464 bool requiresRealignment =
465 ((MFI->getMaxAlignment() > StackAlign) ||
466 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
467 Attribute::StackAlignment));
469 // If we've requested that we force align the stack do so now.
471 return canRealignStack(MF);
473 return requiresRealignment && canRealignStack(MF);
476 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
477 unsigned Reg, int &FrameIdx) const {
478 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
480 if (Reg == FramePtr && TFI->hasFP(MF)) {
481 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
488 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
489 int SPAdj, unsigned FIOperandNum,
490 RegScavenger *RS) const {
491 assert(SPAdj == 0 && "Unexpected");
493 MachineInstr &MI = *II;
494 MachineFunction &MF = *MI.getParent()->getParent();
495 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
496 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
499 unsigned Opc = MI.getOpcode();
500 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
501 if (hasBasePointer(MF))
502 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
503 else if (needsStackRealignment(MF))
504 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
508 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
510 // This must be part of a four operand memory reference. Replace the
511 // FrameIndex with base register with EBP. Add an offset to the offset.
512 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
514 // Now add the frame object offset to the offset from EBP.
517 // Tail call jmp happens after FP is popped.
518 const MachineFrameInfo *MFI = MF.getFrameInfo();
519 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
521 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
523 // The frame index format for stackmaps and patchpoints is different from the
524 // X86 format. It only has a FI and an offset.
525 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
526 assert(BasePtr == FramePtr && "Expected the FP as base register");
527 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
528 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
532 if (MI.getOperand(FIOperandNum+3).isImm()) {
533 // Offset is a 32-bit integer.
534 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
535 int Offset = FIOffset + Imm;
536 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
537 "Requesting 64-bit offset in 32-bit immediate!");
538 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
540 // Offset is symbolic. This is extremely rare.
541 uint64_t Offset = FIOffset +
542 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
543 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
547 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
548 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
549 return TFI->hasFP(MF) ? FramePtr : StackPtr;
553 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
556 default: llvm_unreachable("Unexpected VT");
560 default: return getX86SubSuperRegister(Reg, MVT::i64);
561 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
563 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
565 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
567 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
569 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
571 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
573 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
575 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
580 default: llvm_unreachable("Unexpected register");
581 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
583 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
585 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
587 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
589 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
591 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
593 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
595 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
597 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
599 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
601 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
603 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
605 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
607 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
609 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
611 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
617 default: llvm_unreachable("Unexpected register");
618 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
620 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
622 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
624 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
626 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
628 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
630 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
632 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
634 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
636 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
638 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
640 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
642 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
644 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
646 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
648 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
653 default: llvm_unreachable("Unexpected register");
654 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
656 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
658 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
660 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
662 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
664 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
666 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
668 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
670 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
672 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
674 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
676 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
678 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
680 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
682 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
684 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
689 default: llvm_unreachable("Unexpected register");
690 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
692 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
694 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
696 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
698 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
700 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
702 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
704 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
706 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
708 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
710 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
712 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
714 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
716 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
718 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
720 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
726 unsigned get512BitSuperRegister(unsigned Reg) {
727 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
728 return X86::ZMM0 + (Reg - X86::XMM0);
729 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
730 return X86::ZMM0 + (Reg - X86::YMM0);
731 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
733 llvm_unreachable("Unexpected SIMD register");