1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
48 ForceStackAlign("force-align-stack",
49 cl::desc("Force align the stack to the minimum alignment"
50 " needed for the function."),
51 cl::init(false), cl::Hidden);
53 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
54 const TargetInstrInfo &tii)
55 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
56 ? X86::RIP : X86::EIP,
57 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
58 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
60 X86_MC::InitLLVM2SEHRegisterMapping(this);
62 // Cache some information.
63 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
64 Is64Bit = Subtarget->is64Bit();
65 IsWin64 = Subtarget->isTargetWin64();
78 /// getCompactUnwindRegNum - This function maps the register to the number for
79 /// compact unwind encoding. Return -1 if the register isn't valid.
80 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
81 switch (getLLVMRegNum(RegNum, isEH)) {
82 case X86::EBX: case X86::RBX: return 1;
83 case X86::ECX: case X86::R12: return 2;
84 case X86::EDX: case X86::R13: return 3;
85 case X86::EDI: case X86::R14: return 4;
86 case X86::ESI: case X86::R15: return 5;
87 case X86::EBP: case X86::RBP: return 6;
94 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
95 // Only enable when post-RA scheduling is enabled and this is needed.
96 return TM.getSubtargetImpl()->postRAScheduler();
100 X86RegisterInfo::getSEHRegNum(unsigned i) const {
101 int reg = X86_MC::getX86RegNum(i);
103 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
105 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
106 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
107 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
108 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
109 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
110 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
111 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
112 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
113 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
114 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
120 const TargetRegisterClass *
121 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
122 unsigned Idx) const {
123 // The sub_8bit sub-register index is more constrained in 32-bit mode.
124 // It behaves just like the sub_8bit_hi index.
125 if (!Is64Bit && Idx == X86::sub_8bit)
126 Idx = X86::sub_8bit_hi;
128 // Forward to TableGen's default version.
129 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
132 const TargetRegisterClass *
133 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
134 const TargetRegisterClass *B,
135 unsigned SubIdx) const {
136 // The sub_8bit sub-register index is more constrained in 32-bit mode.
137 if (!Is64Bit && SubIdx == X86::sub_8bit) {
138 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
142 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
145 const TargetRegisterClass*
146 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
147 // Don't allow super-classes of GR8_NOREX. This class is only used after
148 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
149 // to the full GR8 register class in 64-bit mode, so we cannot allow the
150 // reigster class inflation.
152 // The GR8_NOREX class is always used in a way that won't be constrained to a
153 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
155 if (RC == &X86::GR8_NOREXRegClass)
158 const TargetRegisterClass *Super = RC;
159 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
161 switch (Super->getID()) {
162 case X86::GR8RegClassID:
163 case X86::GR16RegClassID:
164 case X86::GR32RegClassID:
165 case X86::GR64RegClassID:
166 case X86::FR32RegClassID:
167 case X86::FR64RegClassID:
168 case X86::RFP32RegClassID:
169 case X86::RFP64RegClassID:
170 case X86::RFP80RegClassID:
171 case X86::VR128RegClassID:
172 case X86::VR256RegClassID:
173 // Don't return a super-class that would shrink the spill size.
174 // That can happen with the vector and float classes.
175 if (Super->getSize() == RC->getSize())
183 const TargetRegisterClass *
184 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
186 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
187 case 0: // Normal GPRs.
188 if (TM.getSubtarget<X86Subtarget>().is64Bit())
189 return &X86::GR64RegClass;
190 return &X86::GR32RegClass;
191 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
192 if (TM.getSubtarget<X86Subtarget>().is64Bit())
193 return &X86::GR64_NOSPRegClass;
194 return &X86::GR32_NOSPRegClass;
195 case 2: // Available for tailcall (not callee-saved GPRs).
196 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
197 return &X86::GR64_TCW64RegClass;
198 if (TM.getSubtarget<X86Subtarget>().is64Bit())
199 return &X86::GR64_TCRegClass;
200 return &X86::GR32_TCRegClass;
204 const TargetRegisterClass *
205 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
206 if (RC == &X86::CCRRegClass) {
208 return &X86::GR64RegClass;
210 return &X86::GR32RegClass;
216 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
217 MachineFunction &MF) const {
218 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
220 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
221 switch (RC->getID()) {
224 case X86::GR32RegClassID:
226 case X86::GR64RegClassID:
228 case X86::VR128RegClassID:
229 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
230 case X86::VR64RegClassID:
236 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
237 bool callsEHReturn = false;
238 bool ghcCall = false;
241 callsEHReturn = MF->getMMI().callsEHReturn();
242 const Function *F = MF->getFunction();
243 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
247 return CSR_Ghc_SaveList;
250 return CSR_Win64_SaveList;
252 return CSR_64EHRet_SaveList;
253 return CSR_64_SaveList;
256 return CSR_32EHRet_SaveList;
257 return CSR_32_SaveList;
261 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
262 if (CC == CallingConv::GHC)
263 return CSR_Ghc_RegMask;
265 return CSR_32_RegMask;
267 return CSR_Win64_RegMask;
268 return CSR_64_RegMask;
271 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
272 BitVector Reserved(getNumRegs());
273 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
275 // Set the stack-pointer register and its aliases as reserved.
276 Reserved.set(X86::RSP);
277 Reserved.set(X86::ESP);
278 Reserved.set(X86::SP);
279 Reserved.set(X86::SPL);
281 // Set the instruction pointer register and its aliases as reserved.
282 Reserved.set(X86::RIP);
283 Reserved.set(X86::EIP);
284 Reserved.set(X86::IP);
286 // Set the frame-pointer register and its aliases as reserved if needed.
287 if (TFI->hasFP(MF)) {
288 Reserved.set(X86::RBP);
289 Reserved.set(X86::EBP);
290 Reserved.set(X86::BP);
291 Reserved.set(X86::BPL);
294 // Mark the segment registers as reserved.
295 Reserved.set(X86::CS);
296 Reserved.set(X86::SS);
297 Reserved.set(X86::DS);
298 Reserved.set(X86::ES);
299 Reserved.set(X86::FS);
300 Reserved.set(X86::GS);
302 // Reserve the registers that only exist in 64-bit mode.
304 // These 8-bit registers are part of the x86-64 extension even though their
305 // super-registers are old 32-bits.
306 Reserved.set(X86::SIL);
307 Reserved.set(X86::DIL);
308 Reserved.set(X86::BPL);
309 Reserved.set(X86::SPL);
311 for (unsigned n = 0; n != 8; ++n) {
313 static const uint16_t GPR64[] = {
314 X86::R8, X86::R9, X86::R10, X86::R11,
315 X86::R12, X86::R13, X86::R14, X86::R15
317 for (const uint16_t *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
321 assert(X86::XMM15 == X86::XMM8+7);
322 for (const uint16_t *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
331 //===----------------------------------------------------------------------===//
332 // Stack Frame Processing methods
333 //===----------------------------------------------------------------------===//
335 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
336 const MachineFrameInfo *MFI = MF.getFrameInfo();
337 return (MF.getTarget().Options.RealignStack &&
338 !MFI->hasVarSizedObjects());
341 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
342 const MachineFrameInfo *MFI = MF.getFrameInfo();
343 const Function *F = MF.getFunction();
344 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
345 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
346 F->hasFnAttr(Attribute::StackAlignment));
348 // FIXME: Currently we don't support stack realignment for functions with
349 // variable-sized allocas.
350 // FIXME: It's more complicated than this...
351 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
353 "Stack realignment in presence of dynamic allocas is not supported");
355 // If we've requested that we force align the stack do so now.
357 return canRealignStack(MF);
359 return requiresRealignment && canRealignStack(MF);
362 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
363 unsigned Reg, int &FrameIdx) const {
364 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
366 if (Reg == FramePtr && TFI->hasFP(MF)) {
367 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
373 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
376 return X86::SUB64ri8;
377 return X86::SUB64ri32;
380 return X86::SUB32ri8;
385 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
388 return X86::ADD64ri8;
389 return X86::ADD64ri32;
392 return X86::ADD32ri8;
397 void X86RegisterInfo::
398 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
399 MachineBasicBlock::iterator I) const {
400 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
401 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
402 int Opcode = I->getOpcode();
403 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
404 DebugLoc DL = I->getDebugLoc();
405 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
406 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
409 if (!reseveCallFrame) {
410 // If the stack pointer can be changed after prologue, turn the
411 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
412 // adjcallstackdown instruction into 'add ESP, <amt>'
413 // TODO: consider using push / pop instead of sub + store / add
417 // We need to keep the stack aligned properly. To do this, we round the
418 // amount of space needed for the outgoing arguments up to the next
419 // alignment boundary.
420 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
421 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
423 MachineInstr *New = 0;
424 if (Opcode == TII.getCallFrameSetupOpcode()) {
425 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
430 assert(Opcode == TII.getCallFrameDestroyOpcode());
432 // Factor out the amount the callee already popped.
436 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
437 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
438 .addReg(StackPtr).addImm(Amount);
443 // The EFLAGS implicit def is dead.
444 New->getOperand(3).setIsDead();
446 // Replace the pseudo instruction with a new instruction.
453 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
454 // If we are performing frame pointer elimination and if the callee pops
455 // something off the stack pointer, add it back. We do this until we have
456 // more advanced stack pointer tracking ability.
457 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
458 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
459 .addReg(StackPtr).addImm(CalleeAmt);
461 // The EFLAGS implicit def is dead.
462 New->getOperand(3).setIsDead();
464 // We are not tracking the stack pointer adjustment by the callee, so make
465 // sure we restore the stack pointer immediately after the call, there may
466 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
467 MachineBasicBlock::iterator B = MBB.begin();
468 while (I != B && !llvm::prior(I)->isCall())
475 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
476 int SPAdj, RegScavenger *RS) const{
477 assert(SPAdj == 0 && "Unexpected");
480 MachineInstr &MI = *II;
481 MachineFunction &MF = *MI.getParent()->getParent();
482 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
484 while (!MI.getOperand(i).isFI()) {
486 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
489 int FrameIndex = MI.getOperand(i).getIndex();
492 unsigned Opc = MI.getOpcode();
493 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
494 if (needsStackRealignment(MF))
495 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
499 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
501 // This must be part of a four operand memory reference. Replace the
502 // FrameIndex with base register with EBP. Add an offset to the offset.
503 MI.getOperand(i).ChangeToRegister(BasePtr, false);
505 // Now add the frame object offset to the offset from EBP.
508 // Tail call jmp happens after FP is popped.
509 const MachineFrameInfo *MFI = MF.getFrameInfo();
510 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
512 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
514 if (MI.getOperand(i+3).isImm()) {
515 // Offset is a 32-bit integer.
516 int Imm = (int)(MI.getOperand(i + 3).getImm());
517 int Offset = FIOffset + Imm;
518 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
519 "Requesting 64-bit offset in 32-bit immediate!");
520 MI.getOperand(i + 3).ChangeToImmediate(Offset);
522 // Offset is symbolic. This is extremely rare.
523 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
524 MI.getOperand(i+3).setOffset(Offset);
528 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
529 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
530 return TFI->hasFP(MF) ? FramePtr : StackPtr;
533 unsigned X86RegisterInfo::getEHExceptionRegister() const {
534 llvm_unreachable("What is the exception register");
537 unsigned X86RegisterInfo::getEHHandlerRegister() const {
538 llvm_unreachable("What is the exception handler register");
542 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
543 switch (VT.getSimpleVT().SimpleTy) {
548 default: return getX86SubSuperRegister(Reg, MVT::i64, High);
549 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
551 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
553 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
555 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
561 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
563 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
565 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
567 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
569 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
571 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
573 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
575 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
577 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
579 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
581 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
583 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
585 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
587 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
589 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
591 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
598 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
600 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
602 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
604 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
606 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
608 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
610 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
612 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
614 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
616 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
618 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
620 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
622 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
624 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
626 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
628 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
634 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
636 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
638 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
640 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
642 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
644 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
646 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
648 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
650 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
652 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
654 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
656 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
658 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
660 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
662 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
664 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
668 // For 64-bit mode if we've requested a "high" register and the
669 // Q or r constraints we want one of these high registers or
670 // just the register name otherwise.
673 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
675 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
677 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
679 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
686 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
688 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
690 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
692 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
694 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
696 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
698 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
700 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
702 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
704 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
706 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
708 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
710 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
712 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
714 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
716 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
724 struct MSAH : public MachineFunctionPass {
726 MSAH() : MachineFunctionPass(ID) {}
728 virtual bool runOnMachineFunction(MachineFunction &MF) {
729 const X86TargetMachine *TM =
730 static_cast<const X86TargetMachine *>(&MF.getTarget());
731 const TargetFrameLowering *TFI = TM->getFrameLowering();
732 MachineRegisterInfo &RI = MF.getRegInfo();
733 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
734 unsigned StackAlignment = TFI->getStackAlignment();
736 // Be over-conservative: scan over all vreg defs and find whether vector
737 // registers are used. If yes, there is a possibility that vector register
738 // will be spilled and thus require dynamic stack realignment.
739 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
740 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
741 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
742 FuncInfo->setForceFramePointer(true);
750 virtual const char *getPassName() const {
751 return "X86 Maximal Stack Alignment Check";
754 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
755 AU.setPreservesCFG();
756 MachineFunctionPass::getAnalysisUsage(AU);
764 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }