1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
48 ForceStackAlign("force-align-stack",
49 cl::desc("Force align the stack to the minimum alignment"
50 " needed for the function."),
51 cl::init(false), cl::Hidden);
53 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
54 const TargetInstrInfo &tii)
55 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
56 ? X86::RIP : X86::EIP,
57 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
58 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
60 X86_MC::InitLLVM2SEHRegisterMapping(this);
62 // Cache some information.
63 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
64 Is64Bit = Subtarget->is64Bit();
65 IsWin64 = Subtarget->isTargetWin64();
78 /// getCompactUnwindRegNum - This function maps the register to the number for
79 /// compact unwind encoding. Return -1 if the register isn't valid.
80 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
81 switch (getLLVMRegNum(RegNum, isEH)) {
82 case X86::EBX: case X86::RBX: return 1;
83 case X86::ECX: case X86::R12: return 2;
84 case X86::EDX: case X86::R13: return 3;
85 case X86::EDI: case X86::R14: return 4;
86 case X86::ESI: case X86::R15: return 5;
87 case X86::EBP: case X86::RBP: return 6;
94 X86RegisterInfo::getSEHRegNum(unsigned i) const {
95 int reg = X86_MC::getX86RegNum(i);
97 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
98 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
99 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
100 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
101 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
102 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
103 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
104 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
105 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
106 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
107 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
108 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
114 const TargetRegisterClass *
115 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
116 const TargetRegisterClass *B,
117 unsigned SubIdx) const {
121 if (B == &X86::GR8RegClass) {
122 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
124 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
125 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
126 A == &X86::GR64_NOREXRegClass ||
127 A == &X86::GR64_NOSPRegClass ||
128 A == &X86::GR64_NOREX_NOSPRegClass)
129 return &X86::GR64_ABCDRegClass;
130 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
131 A == &X86::GR32_NOREXRegClass ||
132 A == &X86::GR32_NOSPRegClass)
133 return &X86::GR32_ABCDRegClass;
134 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
135 A == &X86::GR16_NOREXRegClass)
136 return &X86::GR16_ABCDRegClass;
137 } else if (B == &X86::GR8_NOREXRegClass) {
138 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
139 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
140 return &X86::GR64_NOREXRegClass;
141 else if (A == &X86::GR64_ABCDRegClass)
142 return &X86::GR64_ABCDRegClass;
143 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
144 A == &X86::GR32_NOSPRegClass)
145 return &X86::GR32_NOREXRegClass;
146 else if (A == &X86::GR32_ABCDRegClass)
147 return &X86::GR32_ABCDRegClass;
148 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
149 return &X86::GR16_NOREXRegClass;
150 else if (A == &X86::GR16_ABCDRegClass)
151 return &X86::GR16_ABCDRegClass;
154 case X86::sub_8bit_hi:
155 if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass))
156 switch (A->getSize()) {
157 case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
158 case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
159 case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
164 if (B == &X86::GR16RegClass) {
165 if (A->getSize() == 4 || A->getSize() == 8)
167 } else if (B == &X86::GR16_ABCDRegClass) {
168 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
169 A == &X86::GR64_NOREXRegClass ||
170 A == &X86::GR64_NOSPRegClass ||
171 A == &X86::GR64_NOREX_NOSPRegClass)
172 return &X86::GR64_ABCDRegClass;
173 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
174 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
175 return &X86::GR32_ABCDRegClass;
176 } else if (B == &X86::GR16_NOREXRegClass) {
177 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
178 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
179 return &X86::GR64_NOREXRegClass;
180 else if (A == &X86::GR64_ABCDRegClass)
181 return &X86::GR64_ABCDRegClass;
182 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
183 A == &X86::GR32_NOSPRegClass)
184 return &X86::GR32_NOREXRegClass;
185 else if (A == &X86::GR32_ABCDRegClass)
186 return &X86::GR64_ABCDRegClass;
190 if (B == &X86::GR32RegClass) {
191 if (A->getSize() == 8)
193 } else if (B == &X86::GR32_NOSPRegClass) {
194 if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
195 return &X86::GR64_NOSPRegClass;
196 if (A->getSize() == 8)
197 return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
198 } else if (B == &X86::GR32_ABCDRegClass) {
199 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
200 A == &X86::GR64_NOREXRegClass ||
201 A == &X86::GR64_NOSPRegClass ||
202 A == &X86::GR64_NOREX_NOSPRegClass)
203 return &X86::GR64_ABCDRegClass;
204 } else if (B == &X86::GR32_NOREXRegClass) {
205 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
206 return &X86::GR64_NOREXRegClass;
207 else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
208 return &X86::GR64_NOREX_NOSPRegClass;
209 else if (A == &X86::GR64_ABCDRegClass)
210 return &X86::GR64_ABCDRegClass;
211 } else if (B == &X86::GR32_NOREX_NOSPRegClass) {
212 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
213 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
214 return &X86::GR64_NOREX_NOSPRegClass;
215 else if (A == &X86::GR64_ABCDRegClass)
216 return &X86::GR64_ABCDRegClass;
220 if (B == &X86::FR32RegClass)
224 if (B == &X86::FR64RegClass)
228 if (B == &X86::VR128RegClass)
235 const TargetRegisterClass*
236 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
237 const TargetRegisterClass *Super = RC;
238 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
240 switch (Super->getID()) {
241 case X86::GR8RegClassID:
242 case X86::GR16RegClassID:
243 case X86::GR32RegClassID:
244 case X86::GR64RegClassID:
245 case X86::FR32RegClassID:
246 case X86::FR64RegClassID:
247 case X86::RFP32RegClassID:
248 case X86::RFP64RegClassID:
249 case X86::RFP80RegClassID:
250 case X86::VR128RegClassID:
251 case X86::VR256RegClassID:
252 // Don't return a super-class that would shrink the spill size.
253 // That can happen with the vector and float classes.
254 if (Super->getSize() == RC->getSize())
262 const TargetRegisterClass *
263 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
265 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
266 case 0: // Normal GPRs.
267 if (TM.getSubtarget<X86Subtarget>().is64Bit())
268 return &X86::GR64RegClass;
269 return &X86::GR32RegClass;
270 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
271 if (TM.getSubtarget<X86Subtarget>().is64Bit())
272 return &X86::GR64_NOSPRegClass;
273 return &X86::GR32_NOSPRegClass;
274 case 2: // Available for tailcall (not callee-saved GPRs).
275 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
276 return &X86::GR64_TCW64RegClass;
277 if (TM.getSubtarget<X86Subtarget>().is64Bit())
278 return &X86::GR64_TCRegClass;
279 return &X86::GR32_TCRegClass;
283 const TargetRegisterClass *
284 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
285 if (RC == &X86::CCRRegClass) {
287 return &X86::GR64RegClass;
289 return &X86::GR32RegClass;
295 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
296 MachineFunction &MF) const {
297 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
299 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
300 switch (RC->getID()) {
303 case X86::GR32RegClassID:
305 case X86::GR64RegClassID:
307 case X86::VR128RegClassID:
308 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
309 case X86::VR64RegClassID:
315 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
316 bool callsEHReturn = false;
317 bool ghcCall = false;
320 callsEHReturn = MF->getMMI().callsEHReturn();
321 const Function *F = MF->getFunction();
322 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
325 static const unsigned GhcCalleeSavedRegs[] = {
329 static const unsigned CalleeSavedRegs32Bit[] = {
330 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
333 static const unsigned CalleeSavedRegs32EHRet[] = {
334 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
337 static const unsigned CalleeSavedRegs64Bit[] = {
338 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
341 static const unsigned CalleeSavedRegs64EHRet[] = {
342 X86::RAX, X86::RDX, X86::RBX, X86::R12,
343 X86::R13, X86::R14, X86::R15, X86::RBP, 0
346 static const unsigned CalleeSavedRegsWin64[] = {
347 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
348 X86::R12, X86::R13, X86::R14, X86::R15,
349 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
350 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
351 X86::XMM14, X86::XMM15, 0
355 return GhcCalleeSavedRegs;
356 } else if (Is64Bit) {
358 return CalleeSavedRegsWin64;
360 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
362 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
366 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
367 BitVector Reserved(getNumRegs());
368 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
370 // Set the stack-pointer register and its aliases as reserved.
371 Reserved.set(X86::RSP);
372 Reserved.set(X86::ESP);
373 Reserved.set(X86::SP);
374 Reserved.set(X86::SPL);
376 // Set the instruction pointer register and its aliases as reserved.
377 Reserved.set(X86::RIP);
378 Reserved.set(X86::EIP);
379 Reserved.set(X86::IP);
381 // Set the frame-pointer register and its aliases as reserved if needed.
382 if (TFI->hasFP(MF)) {
383 Reserved.set(X86::RBP);
384 Reserved.set(X86::EBP);
385 Reserved.set(X86::BP);
386 Reserved.set(X86::BPL);
389 // Mark the segment registers as reserved.
390 Reserved.set(X86::CS);
391 Reserved.set(X86::SS);
392 Reserved.set(X86::DS);
393 Reserved.set(X86::ES);
394 Reserved.set(X86::FS);
395 Reserved.set(X86::GS);
397 // Reserve the registers that only exist in 64-bit mode.
399 // These 8-bit registers are part of the x86-64 extension even though their
400 // super-registers are old 32-bits.
401 Reserved.set(X86::SIL);
402 Reserved.set(X86::DIL);
403 Reserved.set(X86::BPL);
404 Reserved.set(X86::SPL);
406 for (unsigned n = 0; n != 8; ++n) {
408 const unsigned GPR64[] = {
409 X86::R8, X86::R9, X86::R10, X86::R11,
410 X86::R12, X86::R13, X86::R14, X86::R15
412 for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
416 assert(X86::XMM15 == X86::XMM8+7);
417 for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
426 //===----------------------------------------------------------------------===//
427 // Stack Frame Processing methods
428 //===----------------------------------------------------------------------===//
430 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
431 const MachineFrameInfo *MFI = MF.getFrameInfo();
432 return (RealignStack &&
433 !MFI->hasVarSizedObjects());
436 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
437 const MachineFrameInfo *MFI = MF.getFrameInfo();
438 const Function *F = MF.getFunction();
439 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
440 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
441 F->hasFnAttr(Attribute::StackAlignment));
443 // FIXME: Currently we don't support stack realignment for functions with
444 // variable-sized allocas.
445 // FIXME: It's more complicated than this...
446 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
448 "Stack realignment in presence of dynamic allocas is not supported");
450 // If we've requested that we force align the stack do so now.
452 return canRealignStack(MF);
454 return requiresRealignment && canRealignStack(MF);
457 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
458 unsigned Reg, int &FrameIdx) const {
459 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
461 if (Reg == FramePtr && TFI->hasFP(MF)) {
462 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
468 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
471 return X86::SUB64ri8;
472 return X86::SUB64ri32;
475 return X86::SUB32ri8;
480 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
483 return X86::ADD64ri8;
484 return X86::ADD64ri32;
487 return X86::ADD32ri8;
492 void X86RegisterInfo::
493 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
494 MachineBasicBlock::iterator I) const {
495 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
496 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
497 int Opcode = I->getOpcode();
498 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
499 DebugLoc DL = I->getDebugLoc();
500 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
501 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
504 if (!reseveCallFrame) {
505 // If the stack pointer can be changed after prologue, turn the
506 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
507 // adjcallstackdown instruction into 'add ESP, <amt>'
508 // TODO: consider using push / pop instead of sub + store / add
512 // We need to keep the stack aligned properly. To do this, we round the
513 // amount of space needed for the outgoing arguments up to the next
514 // alignment boundary.
515 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
516 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
518 MachineInstr *New = 0;
519 if (Opcode == TII.getCallFrameSetupOpcode()) {
520 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
525 assert(Opcode == TII.getCallFrameDestroyOpcode());
527 // Factor out the amount the callee already popped.
531 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
532 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
533 .addReg(StackPtr).addImm(Amount);
538 // The EFLAGS implicit def is dead.
539 New->getOperand(3).setIsDead();
541 // Replace the pseudo instruction with a new instruction.
548 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
549 // If we are performing frame pointer elimination and if the callee pops
550 // something off the stack pointer, add it back. We do this until we have
551 // more advanced stack pointer tracking ability.
552 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
553 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
554 .addReg(StackPtr).addImm(CalleeAmt);
556 // The EFLAGS implicit def is dead.
557 New->getOperand(3).setIsDead();
559 // We are not tracking the stack pointer adjustment by the callee, so make
560 // sure we restore the stack pointer immediately after the call, there may
561 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
562 MachineBasicBlock::iterator B = MBB.begin();
563 while (I != B && !llvm::prior(I)->getDesc().isCall())
570 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
571 int SPAdj, RegScavenger *RS) const{
572 assert(SPAdj == 0 && "Unexpected");
575 MachineInstr &MI = *II;
576 MachineFunction &MF = *MI.getParent()->getParent();
577 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
579 while (!MI.getOperand(i).isFI()) {
581 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
584 int FrameIndex = MI.getOperand(i).getIndex();
587 unsigned Opc = MI.getOpcode();
588 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
589 if (needsStackRealignment(MF))
590 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
594 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
596 // This must be part of a four operand memory reference. Replace the
597 // FrameIndex with base register with EBP. Add an offset to the offset.
598 MI.getOperand(i).ChangeToRegister(BasePtr, false);
600 // Now add the frame object offset to the offset from EBP.
603 // Tail call jmp happens after FP is popped.
604 const MachineFrameInfo *MFI = MF.getFrameInfo();
605 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
607 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
609 if (MI.getOperand(i+3).isImm()) {
610 // Offset is a 32-bit integer.
611 int Imm = (int)(MI.getOperand(i + 3).getImm());
612 int Offset = FIOffset + Imm;
613 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
614 "Requesting 64-bit offset in 32-bit immediate!");
615 MI.getOperand(i + 3).ChangeToImmediate(Offset);
617 // Offset is symbolic. This is extremely rare.
618 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
619 MI.getOperand(i+3).setOffset(Offset);
623 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
624 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
625 return TFI->hasFP(MF) ? FramePtr : StackPtr;
628 unsigned X86RegisterInfo::getEHExceptionRegister() const {
629 llvm_unreachable("What is the exception register");
633 unsigned X86RegisterInfo::getEHHandlerRegister() const {
634 llvm_unreachable("What is the exception handler register");
639 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
640 switch (VT.getSimpleVT().SimpleTy) {
646 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
648 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
650 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
652 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
658 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
660 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
662 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
664 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
666 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
668 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
670 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
672 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
674 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
676 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
678 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
680 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
682 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
684 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
686 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
688 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
695 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
697 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
699 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
701 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
703 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
705 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
707 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
709 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
711 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
713 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
715 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
717 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
719 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
721 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
723 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
725 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
731 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
733 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
735 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
737 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
739 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
741 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
743 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
745 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
747 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
749 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
751 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
753 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
755 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
757 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
759 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
761 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
767 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
769 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
771 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
773 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
775 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
777 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
779 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
781 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
783 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
785 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
787 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
789 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
791 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
793 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
795 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
797 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
807 struct MSAH : public MachineFunctionPass {
809 MSAH() : MachineFunctionPass(ID) {}
811 virtual bool runOnMachineFunction(MachineFunction &MF) {
812 const X86TargetMachine *TM =
813 static_cast<const X86TargetMachine *>(&MF.getTarget());
814 const TargetFrameLowering *TFI = TM->getFrameLowering();
815 MachineRegisterInfo &RI = MF.getRegInfo();
816 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
817 unsigned StackAlignment = TFI->getStackAlignment();
819 // Be over-conservative: scan over all vreg defs and find whether vector
820 // registers are used. If yes, there is a possibility that vector register
821 // will be spilled and thus require dynamic stack realignment.
822 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
823 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
824 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
825 FuncInfo->setForceFramePointer(true);
833 virtual const char *getPassName() const {
834 return "X86 Maximal Stack Alignment Check";
837 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
838 AU.setPreservesCFG();
839 MachineFunctionPass::getAnalysisUsage(AU);
847 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }