1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
68 // getDwarfRegNum - This function maps LLVM register identifiers to the
69 // Dwarf specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
74 if (!Subtarget->is64Bit()) {
75 if (Subtarget->isTargetDarwin()) {
77 Flavour = DWARFFlavour::X86_32_DarwinEH;
79 Flavour = DWARFFlavour::X86_32_Generic;
80 } else if (Subtarget->isTargetCygMing()) {
81 // Unsupported by now, just quick fallback
82 Flavour = DWARFFlavour::X86_32_Generic;
84 Flavour = DWARFFlavour::X86_32_Generic;
88 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
91 // getX86RegNum - This function maps LLVM register identifiers to their X86
92 // specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8: case X86::MM0:
132 case X86::XMM1: case X86::XMM9: case X86::MM1:
134 case X86::XMM2: case X86::XMM10: case X86::MM2:
136 case X86::XMM3: case X86::XMM11: case X86::MM3:
138 case X86::XMM4: case X86::XMM12: case X86::MM4:
140 case X86::XMM5: case X86::XMM13: case X86::MM5:
142 case X86::XMM6: case X86::XMM14: case X86::MM6:
144 case X86::XMM7: case X86::XMM15: case X86::MM7:
148 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
149 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
154 const TargetRegisterClass *
155 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
156 if (RC == &X86::CCRRegClass) {
158 return &X86::GR64RegClass;
160 return &X86::GR32RegClass;
166 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
167 bool callsEHReturn = false;
170 const MachineFrameInfo *MFI = MF->getFrameInfo();
171 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
172 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
175 static const unsigned CalleeSavedRegs32Bit[] = {
176 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
179 static const unsigned CalleeSavedRegs32EHRet[] = {
180 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
183 static const unsigned CalleeSavedRegs64Bit[] = {
184 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
187 static const unsigned CalleeSavedRegs64EHRet[] = {
188 X86::RAX, X86::RDX, X86::RBX, X86::R12,
189 X86::R13, X86::R14, X86::R15, X86::RBP, 0
192 static const unsigned CalleeSavedRegsWin64[] = {
193 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
194 X86::R12, X86::R13, X86::R14, X86::R15,
195 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
196 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
197 X86::XMM14, X86::XMM15, 0
202 return CalleeSavedRegsWin64;
204 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
206 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
210 const TargetRegisterClass* const*
211 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
212 bool callsEHReturn = false;
215 const MachineFrameInfo *MFI = MF->getFrameInfo();
216 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
217 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
220 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
221 &X86::GR32RegClass, &X86::GR32RegClass,
222 &X86::GR32RegClass, &X86::GR32RegClass, 0
224 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
225 &X86::GR32RegClass, &X86::GR32RegClass,
226 &X86::GR32RegClass, &X86::GR32RegClass,
227 &X86::GR32RegClass, &X86::GR32RegClass, 0
229 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
230 &X86::GR64RegClass, &X86::GR64RegClass,
231 &X86::GR64RegClass, &X86::GR64RegClass,
232 &X86::GR64RegClass, &X86::GR64RegClass, 0
234 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
235 &X86::GR64RegClass, &X86::GR64RegClass,
236 &X86::GR64RegClass, &X86::GR64RegClass,
237 &X86::GR64RegClass, &X86::GR64RegClass,
238 &X86::GR64RegClass, &X86::GR64RegClass, 0
240 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
241 &X86::GR64RegClass, &X86::GR64RegClass,
242 &X86::GR64RegClass, &X86::GR64RegClass,
243 &X86::GR64RegClass, &X86::GR64RegClass,
244 &X86::GR64RegClass, &X86::GR64RegClass,
245 &X86::VR128RegClass, &X86::VR128RegClass,
246 &X86::VR128RegClass, &X86::VR128RegClass,
247 &X86::VR128RegClass, &X86::VR128RegClass,
248 &X86::VR128RegClass, &X86::VR128RegClass,
249 &X86::VR128RegClass, &X86::VR128RegClass, 0
254 return CalleeSavedRegClassesWin64;
256 return (callsEHReturn ?
257 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
259 return (callsEHReturn ?
260 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
264 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
265 BitVector Reserved(getNumRegs());
266 // Set the stack-pointer register and its aliases as reserved.
267 Reserved.set(X86::RSP);
268 Reserved.set(X86::ESP);
269 Reserved.set(X86::SP);
270 Reserved.set(X86::SPL);
271 // Set the frame-pointer register and its aliases as reserved if needed.
273 Reserved.set(X86::RBP);
274 Reserved.set(X86::EBP);
275 Reserved.set(X86::BP);
276 Reserved.set(X86::BPL);
278 // Mark the x87 stack registers as reserved, since they don't
279 // behave normally with respect to liveness. We don't fully
280 // model the effects of x87 stack pushes and pops after
282 Reserved.set(X86::ST0);
283 Reserved.set(X86::ST1);
284 Reserved.set(X86::ST2);
285 Reserved.set(X86::ST3);
286 Reserved.set(X86::ST4);
287 Reserved.set(X86::ST5);
288 Reserved.set(X86::ST6);
289 Reserved.set(X86::ST7);
293 //===----------------------------------------------------------------------===//
294 // Stack Frame Processing methods
295 //===----------------------------------------------------------------------===//
297 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
298 unsigned MaxAlign = 0;
299 for (int i = FFI->getObjectIndexBegin(),
300 e = FFI->getObjectIndexEnd(); i != e; ++i) {
301 if (FFI->isDeadObjectIndex(i))
303 unsigned Align = FFI->getObjectAlignment(i);
304 MaxAlign = std::max(MaxAlign, Align);
310 // hasFP - Return true if the specified function should have a dedicated frame
311 // pointer register. This is true if the function has variable sized allocas or
312 // if frame pointer elimination is disabled.
314 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
315 const MachineFrameInfo *MFI = MF.getFrameInfo();
316 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
318 return (NoFramePointerElim ||
319 needsStackRealignment(MF) ||
320 MFI->hasVarSizedObjects() ||
321 MFI->isFrameAddressTaken() ||
322 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
323 (MMI && MMI->callsUnwindInit()));
326 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
327 const MachineFrameInfo *MFI = MF.getFrameInfo();;
329 // FIXME: Currently we don't support stack realignment for functions with
330 // variable-sized allocas
331 return (RealignStack &&
332 (MFI->getMaxAlignment() > StackAlign &&
333 !MFI->hasVarSizedObjects()));
336 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
337 return !MF.getFrameInfo()->hasVarSizedObjects();
341 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
342 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
343 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
345 if (needsStackRealignment(MF)) {
347 // Skip the saved EBP
350 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
351 assert( (-(Offset + StackSize)) % Align == 0);
353 return Offset + StackSize;
356 // FIXME: Support tail calls
359 return Offset + StackSize;
361 // Skip the saved EBP
364 // Skip the RETADDR move area
365 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
366 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
367 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
373 void X86RegisterInfo::
374 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
375 MachineBasicBlock::iterator I) const {
376 if (!hasReservedCallFrame(MF)) {
377 // If the stack pointer can be changed after prologue, turn the
378 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
379 // adjcallstackdown instruction into 'add ESP, <amt>'
380 // TODO: consider using push / pop instead of sub + store / add
381 MachineInstr *Old = I;
382 uint64_t Amount = Old->getOperand(0).getImm();
384 // We need to keep the stack aligned properly. To do this, we round the
385 // amount of space needed for the outgoing arguments up to the next
386 // alignment boundary.
387 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
389 MachineInstr *New = 0;
390 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
391 New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
392 StackPtr).addReg(StackPtr).addImm(Amount);
394 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
395 // factor out the amount the callee already popped.
396 uint64_t CalleeAmt = Old->getOperand(1).getImm();
399 unsigned Opc = (Amount < 128) ?
400 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
401 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
402 New = BuildMI(MF, TII.get(Opc), StackPtr)
403 .addReg(StackPtr).addImm(Amount);
407 // The EFLAGS implicit def is dead.
408 New->getOperand(3).setIsDead();
410 // Replace the pseudo instruction with a new instruction...
411 if (New) MBB.insert(I, New);
413 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
414 // If we are performing frame pointer elimination and if the callee pops
415 // something off the stack pointer, add it back. We do this until we have
416 // more advanced stack pointer tracking ability.
417 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
418 unsigned Opc = (CalleeAmt < 128) ?
419 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
420 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
422 BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
423 // The EFLAGS implicit def is dead.
424 New->getOperand(3).setIsDead();
433 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
434 int SPAdj, RegScavenger *RS) const{
435 assert(SPAdj == 0 && "Unexpected");
438 MachineInstr &MI = *II;
439 MachineFunction &MF = *MI.getParent()->getParent();
440 while (!MI.getOperand(i).isFI()) {
442 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
445 int FrameIndex = MI.getOperand(i).getIndex();
448 if (needsStackRealignment(MF))
449 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
451 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
453 // This must be part of a four operand memory reference. Replace the
454 // FrameIndex with base register with EBP. Add an offset to the offset.
455 MI.getOperand(i).ChangeToRegister(BasePtr, false);
457 // Now add the frame object offset to the offset from EBP.
458 if (MI.getOperand(i+3).isImm()) {
459 // Offset is a 32-bit integer.
460 int Offset = getFrameIndexOffset(MF, FrameIndex) +
461 (int)(MI.getOperand(i+3).getImm());
463 MI.getOperand(i+3).ChangeToImmediate(Offset);
465 // Offset is symbolic. This is extremely rare.
466 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
467 (uint64_t)MI.getOperand(i+3).getOffset();
468 MI.getOperand(i+3).setOffset(Offset);
473 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
474 RegScavenger *RS) const {
475 MachineFrameInfo *FFI = MF.getFrameInfo();
477 // Calculate and set max stack object alignment early, so we can decide
478 // whether we will need stack realignment (and thus FP).
479 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
480 calculateMaxStackAlignment(FFI));
482 FFI->setMaxAlignment(MaxAlign);
486 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
487 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
488 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
489 if (TailCallReturnAddrDelta < 0) {
490 // create RETURNADDR area
500 CreateFixedObject(-TailCallReturnAddrDelta,
501 (-1*SlotSize)+TailCallReturnAddrDelta);
504 assert((TailCallReturnAddrDelta <= 0) &&
505 "The Delta should always be zero or negative");
506 // Create a frame entry for the EBP register that must be saved.
507 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
509 TailCallReturnAddrDelta);
510 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
511 "Slot for EBP register must be last in order to be found!");
516 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
517 /// stack pointer by a constant value.
519 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
520 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
521 const TargetInstrInfo &TII) {
522 bool isSub = NumBytes < 0;
523 uint64_t Offset = isSub ? -NumBytes : NumBytes;
526 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
527 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
529 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
530 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
531 uint64_t Chunk = (1LL << 31) - 1;
534 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
536 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
537 // The EFLAGS implicit def is dead.
538 MI->getOperand(3).setIsDead();
543 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
545 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
546 unsigned StackPtr, uint64_t *NumBytes = NULL) {
547 if (MBBI == MBB.begin()) return;
549 MachineBasicBlock::iterator PI = prior(MBBI);
550 unsigned Opc = PI->getOpcode();
551 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
552 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
553 PI->getOperand(0).getReg() == StackPtr) {
555 *NumBytes += PI->getOperand(2).getImm();
557 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
558 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
559 PI->getOperand(0).getReg() == StackPtr) {
561 *NumBytes -= PI->getOperand(2).getImm();
566 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
568 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
569 MachineBasicBlock::iterator &MBBI,
570 unsigned StackPtr, uint64_t *NumBytes = NULL) {
573 if (MBBI == MBB.end()) return;
575 MachineBasicBlock::iterator NI = next(MBBI);
576 if (NI == MBB.end()) return;
578 unsigned Opc = NI->getOpcode();
579 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
580 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
581 NI->getOperand(0).getReg() == StackPtr) {
583 *NumBytes -= NI->getOperand(2).getImm();
586 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
587 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
588 NI->getOperand(0).getReg() == StackPtr) {
590 *NumBytes += NI->getOperand(2).getImm();
596 /// mergeSPUpdates - Checks the instruction before/after the passed
597 /// instruction. If it is an ADD/SUB instruction it is deleted
598 /// argument and the stack adjustment is returned as a positive value for ADD
599 /// and a negative for SUB.
600 static int mergeSPUpdates(MachineBasicBlock &MBB,
601 MachineBasicBlock::iterator &MBBI,
603 bool doMergeWithPrevious) {
605 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
606 (!doMergeWithPrevious && MBBI == MBB.end()))
611 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
612 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
613 unsigned Opc = PI->getOpcode();
614 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
615 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
616 PI->getOperand(0).getReg() == StackPtr){
617 Offset += PI->getOperand(2).getImm();
619 if (!doMergeWithPrevious) MBBI = NI;
620 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
621 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
622 PI->getOperand(0).getReg() == StackPtr) {
623 Offset -= PI->getOperand(2).getImm();
625 if (!doMergeWithPrevious) MBBI = NI;
631 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
632 unsigned FrameLabelId,
633 unsigned ReadyLabelId) const {
634 MachineFrameInfo *MFI = MF.getFrameInfo();
635 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
639 uint64_t StackSize = MFI->getStackSize();
640 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
641 const TargetData *TD = MF.getTarget().getTargetData();
643 // Calculate amount of bytes used for return address storing
645 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
646 TargetFrameInfo::StackGrowsUp ?
647 TD->getPointerSize() : -TD->getPointerSize());
650 // Show update of SP.
653 MachineLocation SPDst(MachineLocation::VirtualFP);
654 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
655 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
657 MachineLocation SPDst(MachineLocation::VirtualFP);
658 MachineLocation SPSrc(MachineLocation::VirtualFP,
659 -StackSize+stackGrowth);
660 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
663 //FIXME: Verify & implement for FP
664 MachineLocation SPDst(StackPtr);
665 MachineLocation SPSrc(StackPtr, stackGrowth);
666 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
669 // Add callee saved registers to move list.
670 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
672 // FIXME: This is dirty hack. The code itself is pretty mess right now.
673 // It should be rewritten from scratch and generalized sometimes.
675 // Determine maximum offset (minumum due to stack growth)
676 int64_t MaxOffset = 0;
677 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
678 MaxOffset = std::min(MaxOffset,
679 MFI->getObjectOffset(CSI[I].getFrameIdx()));
682 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
683 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
684 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
685 unsigned Reg = CSI[I].getReg();
686 Offset = (MaxOffset-Offset+saveAreaOffset);
687 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
688 MachineLocation CSSrc(Reg);
689 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
694 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
695 MachineLocation FPSrc(FramePtr);
696 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
699 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
700 MachineLocation FPSrc(MachineLocation::VirtualFP);
701 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
705 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
706 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
707 MachineFrameInfo *MFI = MF.getFrameInfo();
708 const Function* Fn = MF.getFunction();
709 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
710 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
711 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
712 MachineBasicBlock::iterator MBBI = MBB.begin();
713 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
714 !Fn->doesNotThrow() ||
715 UnwindTablesMandatory;
716 // Prepare for frame info.
717 unsigned FrameLabelId = 0;
719 // Get the number of bytes to allocate from the FrameInfo.
720 uint64_t StackSize = MFI->getStackSize();
721 // Get desired stack alignment
722 uint64_t MaxAlign = MFI->getMaxAlignment();
724 // Add RETADDR move area to callee saved frame size.
725 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
726 if (TailCallReturnAddrDelta < 0)
727 X86FI->setCalleeSavedFrameSize(
728 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
730 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
731 // function, and use up to 128 bytes of stack space, don't have a frame
732 // pointer, calls, or dynamic alloca then we do not need to adjust the
733 // stack pointer (we fit in the Red Zone).
734 if (Is64Bit && !DisableRedZone &&
735 !needsStackRealignment(MF) &&
736 !MFI->hasVarSizedObjects() && // No dynamic alloca.
737 !MFI->hasCalls()) { // No calls.
738 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
739 if (hasFP(MF)) MinSize += SlotSize;
740 StackSize = std::max(MinSize,
741 StackSize > 128 ? StackSize - 128 : 0);
742 MFI->setStackSize(StackSize);
745 // Insert stack pointer adjustment for later moving of return addr. Only
746 // applies to tail call optimized functions where the callee argument stack
747 // size is bigger than the callers.
748 if (TailCallReturnAddrDelta < 0) {
750 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
751 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
752 // The EFLAGS implicit def is dead.
753 MI->getOperand(3).setIsDead();
756 uint64_t NumBytes = 0;
758 // Calculate required stack adjustment
759 uint64_t FrameSize = StackSize - SlotSize;
760 if (needsStackRealignment(MF))
761 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
763 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
765 // Get the offset of the stack slot for the EBP register... which is
766 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
767 // Update the frame offset adjustment.
768 MFI->setOffsetAdjustment(-NumBytes);
770 // Save EBP into the appropriate stack slot...
771 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
772 .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
774 if (needsFrameMoves) {
775 // Mark effective beginning of when frame pointer becomes valid.
776 FrameLabelId = MMI->NextLabelID();
777 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
780 // Update EBP with the new base value...
781 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
784 // Mark the FramePtr as live-in in every block except the entry.
785 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
787 I->addLiveIn(FramePtr);
790 if (needsStackRealignment(MF)) {
793 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
794 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
795 // The EFLAGS implicit def is dead.
796 MI->getOperand(3).setIsDead();
799 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
801 unsigned ReadyLabelId = 0;
802 if (needsFrameMoves) {
803 // Mark effective beginning of when frame pointer is ready.
804 ReadyLabelId = MMI->NextLabelID();
805 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
808 // Skip the callee-saved push instructions.
809 while (MBBI != MBB.end() &&
810 (MBBI->getOpcode() == X86::PUSH32r ||
811 MBBI->getOpcode() == X86::PUSH64r))
814 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
815 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
816 // Check, whether EAX is livein for this function
817 bool isEAXAlive = false;
818 for (MachineRegisterInfo::livein_iterator
819 II = MF.getRegInfo().livein_begin(),
820 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
821 unsigned Reg = II->first;
822 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
823 Reg == X86::AH || Reg == X86::AL);
826 // Function prologue calls _alloca to probe the stack when allocating
827 // more than 4k bytes in one go. Touching the stack at 4K increments is
828 // necessary to ensure that the guard pages used by the OS virtual memory
829 // manager are allocated in correct sequence.
831 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
832 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
833 .addExternalSymbol("_alloca");
836 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r))
837 .addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
838 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
839 // allocated bytes for EAX.
840 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
841 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
842 .addExternalSymbol("_alloca");
844 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
845 StackPtr, false, NumBytes-4);
846 MBB.insert(MBBI, MI);
849 // If there is an SUB32ri of ESP immediately before this instruction,
850 // merge the two. This can be the case when tail call elimination is
851 // enabled and the callee has more arguments then the caller.
852 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
853 // If there is an ADD32ri or SUB32ri of ESP immediately after this
854 // instruction, merge the two instructions.
855 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
858 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
863 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
866 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
867 MachineBasicBlock &MBB) const {
868 const MachineFrameInfo *MFI = MF.getFrameInfo();
869 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
870 MachineBasicBlock::iterator MBBI = prior(MBB.end());
871 unsigned RetOpcode = MBBI->getOpcode();
876 case X86::TCRETURNdi:
877 case X86::TCRETURNri:
878 case X86::TCRETURNri64:
879 case X86::TCRETURNdi64:
881 case X86::EH_RETURN64:
884 case X86::TAILJMPm: break; // These are ok
886 assert(0 && "Can only insert epilog into returning blocks");
889 // Get the number of bytes to allocate from the FrameInfo
890 uint64_t StackSize = MFI->getStackSize();
891 uint64_t MaxAlign = MFI->getMaxAlignment();
892 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
893 uint64_t NumBytes = 0;
896 // Calculate required stack adjustment
897 uint64_t FrameSize = StackSize - SlotSize;
898 if (needsStackRealignment(MF))
899 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
901 NumBytes = FrameSize - CSSize;
904 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
906 NumBytes = StackSize - CSSize;
908 // Skip the callee-saved pop instructions.
909 MachineBasicBlock::iterator LastCSPop = MBBI;
910 while (MBBI != MBB.begin()) {
911 MachineBasicBlock::iterator PI = prior(MBBI);
912 unsigned Opc = PI->getOpcode();
913 if (Opc != X86::POP32r && Opc != X86::POP64r &&
914 !PI->getDesc().isTerminator())
919 // If there is an ADD32ri or SUB32ri of ESP immediately before this
920 // instruction, merge the two instructions.
921 if (NumBytes || MFI->hasVarSizedObjects())
922 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
924 // If dynamic alloca is used, then reset esp to point to the last callee-saved
925 // slot before popping them off! Same applies for the case, when stack was
927 if (needsStackRealignment(MF)) {
928 // We cannot use LEA here, because stack pointer was realigned. We need to
929 // deallocate local frame back
931 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
932 MBBI = prior(LastCSPop);
936 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
937 StackPtr).addReg(FramePtr);
938 } else if (MFI->hasVarSizedObjects()) {
940 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
941 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
942 FramePtr, false, -CSSize);
943 MBB.insert(MBBI, MI);
945 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
946 StackPtr).addReg(FramePtr);
949 // adjust stack pointer back: ESP += numbytes
951 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
954 // We're returning from function via eh_return.
955 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
956 MBBI = prior(MBB.end());
957 MachineOperand &DestAddr = MBBI->getOperand(0);
958 assert(DestAddr.isReg() && "Offset should be in register!");
960 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
961 StackPtr).addReg(DestAddr.getReg());
962 // Tail call return: adjust the stack pointer and jump to callee
963 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
964 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
965 MBBI = prior(MBB.end());
966 MachineOperand &JumpTarget = MBBI->getOperand(0);
967 MachineOperand &StackAdjust = MBBI->getOperand(1);
968 assert(StackAdjust.isImm() && "Expecting immediate value.");
970 // Adjust stack pointer.
971 int StackAdj = StackAdjust.getImm();
972 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
974 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
975 // Incoporate the retaddr area.
976 Offset = StackAdj-MaxTCDelta;
977 assert(Offset >= 0 && "Offset should never be negative");
979 // Check for possible merge with preceeding ADD instruction.
980 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
981 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
983 // Jump to label or value in register.
984 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
985 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
986 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
987 else if (RetOpcode== X86::TCRETURNri64) {
988 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
990 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
991 // Delete the pseudo instruction TCRETURN.
993 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
994 (X86FI->getTCReturnAddrDelta() < 0)) {
995 // Add the return addr area delta back since we are not tail calling.
996 int delta = -1*X86FI->getTCReturnAddrDelta();
997 MBBI = prior(MBB.end());
998 // Check for possible merge with preceeding ADD instruction.
999 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1000 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1004 unsigned X86RegisterInfo::getRARegister() const {
1006 return X86::RIP; // Should have dwarf #16
1008 return X86::EIP; // Should have dwarf #8
1011 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1012 return hasFP(MF) ? FramePtr : StackPtr;
1015 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1017 // Calculate amount of bytes used for return address storing
1018 int stackGrowth = (Is64Bit ? -8 : -4);
1020 // Initial state of the frame pointer is esp+4.
1021 MachineLocation Dst(MachineLocation::VirtualFP);
1022 MachineLocation Src(StackPtr, stackGrowth);
1023 Moves.push_back(MachineMove(0, Dst, Src));
1025 // Add return address to move list
1026 MachineLocation CSDst(StackPtr, stackGrowth);
1027 MachineLocation CSSrc(getRARegister());
1028 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1031 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1032 assert(0 && "What is the exception register");
1036 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1037 assert(0 && "What is the exception handler register");
1042 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1043 switch (VT.getSimpleVT()) {
1044 default: return Reg;
1049 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1051 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1053 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1055 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1061 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1063 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1065 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1067 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1069 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1071 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1073 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1075 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1077 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1079 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1081 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1083 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1085 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1087 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1089 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1091 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1097 default: return Reg;
1098 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1100 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1102 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1104 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1106 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1108 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1110 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1112 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1114 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1116 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1118 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1120 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1122 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1124 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1126 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1128 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1133 default: return Reg;
1134 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1136 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1138 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1140 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1142 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1144 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1146 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1148 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1150 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1152 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1154 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1156 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1158 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1160 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1162 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1164 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1169 default: return Reg;
1170 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1172 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1174 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1176 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1178 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1180 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1182 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1184 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1186 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1188 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1190 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1192 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1194 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1196 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1198 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1200 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1209 #include "X86GenRegisterInfo.inc"
1212 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1214 MSAC() : MachineFunctionPass(&ID) {}
1216 virtual bool runOnMachineFunction(MachineFunction &MF) {
1217 MachineFrameInfo *FFI = MF.getFrameInfo();
1218 MachineRegisterInfo &RI = MF.getRegInfo();
1220 // Calculate max stack alignment of all already allocated stack objects.
1221 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1223 // Be over-conservative: scan over all vreg defs and find, whether vector
1224 // registers are used. If yes - there is probability, that vector register
1225 // will be spilled and thus stack needs to be aligned properly.
1226 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1227 RegNum < RI.getLastVirtReg(); ++RegNum)
1228 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1230 FFI->setMaxAlignment(MaxAlign);
1235 virtual const char *getPassName() const {
1236 return "X86 Maximal Stack Alignment Calculator";
1244 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }