1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/ADT/STLExtras.h"
35 NoFusing("disable-spill-fusing",
36 cl::desc("Disable fusing of spill code into instructions"));
38 PrintFailedFusing("print-failed-fuse-candidates",
39 cl::desc("Print instructions that the allocator wants to"
40 " fuse, but the X86 backend currently can't"),
44 X86RegisterInfo::X86RegisterInfo()
45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
47 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
48 MachineBasicBlock::iterator MI,
49 unsigned SrcReg, int FrameIdx,
50 const TargetRegisterClass *RC) const {
52 if (RC == &X86::R32RegClass) {
54 } else if (RC == &X86::R8RegClass) {
56 } else if (RC == &X86::R16RegClass) {
58 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
60 } else if (RC == &X86::V4F4RegClass) {
62 } else if (RC == &X86::V2F8RegClass) {
65 assert(0 && "Unknown regclass");
68 addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
71 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator MI,
73 unsigned DestReg, int FrameIdx,
74 const TargetRegisterClass *RC) const{
76 if (RC == &X86::R32RegClass) {
78 } else if (RC == &X86::R8RegClass) {
80 } else if (RC == &X86::R16RegClass) {
82 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
84 } else if (RC == &X86::V4F4RegClass) {
86 } else if (RC == &X86::V2F8RegClass) {
89 assert(0 && "Unknown regclass");
92 addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
95 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator MI,
97 unsigned DestReg, unsigned SrcReg,
98 const TargetRegisterClass *RC) const {
100 if (RC == &X86::R32RegClass) {
102 } else if (RC == &X86::R8RegClass) {
104 } else if (RC == &X86::R16RegClass) {
106 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
108 } else if (RC == &X86::V4F4RegClass) {
110 } else if (RC == &X86::V2F8RegClass) {
113 assert(0 && "Unknown regclass");
116 BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
119 unsigned X86RegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
120 int &FrameIndex) const {
121 switch (MI->getOpcode()) {
129 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
130 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
131 MI->getOperand(2).getImmedValue() == 1 &&
132 MI->getOperand(3).getReg() == 0 &&
133 MI->getOperand(4).getImmedValue() == 0) {
134 FrameIndex = MI->getOperand(1).getFrameIndex();
135 return MI->getOperand(0).getReg();
143 static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
145 return addFrameReference(BuildMI(Opcode, 4), FrameIndex);
148 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
150 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
151 .addReg(MI->getOperand(1).getReg());
154 static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
156 return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
157 .addReg(MI->getOperand(1).getReg())
158 .addZImm(MI->getOperand(2).getImmedValue());
161 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
163 if (MI->getOperand(1).isImmediate())
164 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
165 .addZImm(MI->getOperand(1).getImmedValue());
166 else if (MI->getOperand(1).isGlobalAddress())
167 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
168 .addGlobalAddress(MI->getOperand(1).getGlobal());
169 assert(0 && "Unknown operand for MakeMI!");
173 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
175 const MachineOperand& op = MI->getOperand(0);
176 return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
180 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
182 const MachineOperand& op = MI->getOperand(0);
183 return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
184 FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
188 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
190 int FrameIndex) const {
191 if (NoFusing) return NULL;
193 /// FIXME: This should obviously be autogenerated by tablegen when patterns
195 MachineBasicBlock& MBB = *MI->getParent();
197 switch(MI->getOpcode()) {
198 case X86::XCHG8rr: return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI);
199 case X86::XCHG16rr: return MakeMRInst(X86::XCHG16mr,FrameIndex, MI);
200 case X86::XCHG32rr: return MakeMRInst(X86::XCHG32mr,FrameIndex, MI);
201 case X86::MOV8rr: return MakeMRInst(X86::MOV8mr , FrameIndex, MI);
202 case X86::MOV16rr: return MakeMRInst(X86::MOV16mr, FrameIndex, MI);
203 case X86::MOV32rr: return MakeMRInst(X86::MOV32mr, FrameIndex, MI);
204 case X86::MOV8ri: return MakeMIInst(X86::MOV8mi , FrameIndex, MI);
205 case X86::MOV16ri: return MakeMIInst(X86::MOV16mi, FrameIndex, MI);
206 case X86::MOV32ri: return MakeMIInst(X86::MOV32mi, FrameIndex, MI);
207 case X86::MUL8r: return MakeMInst( X86::MUL8m , FrameIndex, MI);
208 case X86::MUL16r: return MakeMInst( X86::MUL16m, FrameIndex, MI);
209 case X86::MUL32r: return MakeMInst( X86::MUL32m, FrameIndex, MI);
210 case X86::IMUL8r: return MakeMInst( X86::IMUL8m , FrameIndex, MI);
211 case X86::IMUL16r: return MakeMInst( X86::IMUL16m, FrameIndex, MI);
212 case X86::IMUL32r: return MakeMInst( X86::IMUL32m, FrameIndex, MI);
213 case X86::DIV8r: return MakeMInst( X86::DIV8m , FrameIndex, MI);
214 case X86::DIV16r: return MakeMInst( X86::DIV16m, FrameIndex, MI);
215 case X86::DIV32r: return MakeMInst( X86::DIV32m, FrameIndex, MI);
216 case X86::IDIV8r: return MakeMInst( X86::IDIV8m , FrameIndex, MI);
217 case X86::IDIV16r: return MakeMInst( X86::IDIV16m, FrameIndex, MI);
218 case X86::IDIV32r: return MakeMInst( X86::IDIV32m, FrameIndex, MI);
219 case X86::NEG8r: return MakeMInst( X86::NEG8m , FrameIndex, MI);
220 case X86::NEG16r: return MakeMInst( X86::NEG16m, FrameIndex, MI);
221 case X86::NEG32r: return MakeMInst( X86::NEG32m, FrameIndex, MI);
222 case X86::NOT8r: return MakeMInst( X86::NOT8m , FrameIndex, MI);
223 case X86::NOT16r: return MakeMInst( X86::NOT16m, FrameIndex, MI);
224 case X86::NOT32r: return MakeMInst( X86::NOT32m, FrameIndex, MI);
225 case X86::INC8r: return MakeMInst( X86::INC8m , FrameIndex, MI);
226 case X86::INC16r: return MakeMInst( X86::INC16m, FrameIndex, MI);
227 case X86::INC32r: return MakeMInst( X86::INC32m, FrameIndex, MI);
228 case X86::DEC8r: return MakeMInst( X86::DEC8m , FrameIndex, MI);
229 case X86::DEC16r: return MakeMInst( X86::DEC16m, FrameIndex, MI);
230 case X86::DEC32r: return MakeMInst( X86::DEC32m, FrameIndex, MI);
231 case X86::ADD8rr: return MakeMRInst(X86::ADD8mr , FrameIndex, MI);
232 case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI);
233 case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI);
234 case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
235 case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
236 case X86::ADD8ri: return MakeMIInst(X86::ADD8mi , FrameIndex, MI);
237 case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI);
238 case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI);
239 case X86::SUB8rr: return MakeMRInst(X86::SUB8mr , FrameIndex, MI);
240 case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
241 case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
242 case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
243 case X86::SBB8ri: return MakeMIInst(X86::SBB8mi, FrameIndex, MI);
244 case X86::SBB16ri: return MakeMIInst(X86::SBB16mi, FrameIndex, MI);
245 case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
246 case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
247 case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
248 case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI);
249 case X86::AND8rr: return MakeMRInst(X86::AND8mr , FrameIndex, MI);
250 case X86::AND16rr: return MakeMRInst(X86::AND16mr, FrameIndex, MI);
251 case X86::AND32rr: return MakeMRInst(X86::AND32mr, FrameIndex, MI);
252 case X86::AND8ri: return MakeMIInst(X86::AND8mi , FrameIndex, MI);
253 case X86::AND16ri: return MakeMIInst(X86::AND16mi, FrameIndex, MI);
254 case X86::AND32ri: return MakeMIInst(X86::AND32mi, FrameIndex, MI);
255 case X86::OR8rr: return MakeMRInst(X86::OR8mr , FrameIndex, MI);
256 case X86::OR16rr: return MakeMRInst(X86::OR16mr, FrameIndex, MI);
257 case X86::OR32rr: return MakeMRInst(X86::OR32mr, FrameIndex, MI);
258 case X86::OR8ri: return MakeMIInst(X86::OR8mi , FrameIndex, MI);
259 case X86::OR16ri: return MakeMIInst(X86::OR16mi, FrameIndex, MI);
260 case X86::OR32ri: return MakeMIInst(X86::OR32mi, FrameIndex, MI);
261 case X86::XOR8rr: return MakeMRInst(X86::XOR8mr , FrameIndex, MI);
262 case X86::XOR16rr: return MakeMRInst(X86::XOR16mr, FrameIndex, MI);
263 case X86::XOR32rr: return MakeMRInst(X86::XOR32mr, FrameIndex, MI);
264 case X86::XOR8ri: return MakeMIInst(X86::XOR8mi , FrameIndex, MI);
265 case X86::XOR16ri: return MakeMIInst(X86::XOR16mi, FrameIndex, MI);
266 case X86::XOR32ri: return MakeMIInst(X86::XOR32mi, FrameIndex, MI);
267 case X86::SHL8rCL: return MakeMInst( X86::SHL8mCL ,FrameIndex, MI);
268 case X86::SHL16rCL: return MakeMInst( X86::SHL16mCL,FrameIndex, MI);
269 case X86::SHL32rCL: return MakeMInst( X86::SHL32mCL,FrameIndex, MI);
270 case X86::SHL8ri: return MakeMIInst(X86::SHL8mi , FrameIndex, MI);
271 case X86::SHL16ri: return MakeMIInst(X86::SHL16mi, FrameIndex, MI);
272 case X86::SHL32ri: return MakeMIInst(X86::SHL32mi, FrameIndex, MI);
273 case X86::SHR8rCL: return MakeMInst( X86::SHR8mCL ,FrameIndex, MI);
274 case X86::SHR16rCL: return MakeMInst( X86::SHR16mCL,FrameIndex, MI);
275 case X86::SHR32rCL: return MakeMInst( X86::SHR32mCL,FrameIndex, MI);
276 case X86::SHR8ri: return MakeMIInst(X86::SHR8mi , FrameIndex, MI);
277 case X86::SHR16ri: return MakeMIInst(X86::SHR16mi, FrameIndex, MI);
278 case X86::SHR32ri: return MakeMIInst(X86::SHR32mi, FrameIndex, MI);
279 case X86::SAR8rCL: return MakeMInst( X86::SAR8mCL ,FrameIndex, MI);
280 case X86::SAR16rCL: return MakeMInst( X86::SAR16mCL,FrameIndex, MI);
281 case X86::SAR32rCL: return MakeMInst( X86::SAR32mCL,FrameIndex, MI);
282 case X86::SAR8ri: return MakeMIInst(X86::SAR8mi , FrameIndex, MI);
283 case X86::SAR16ri: return MakeMIInst(X86::SAR16mi, FrameIndex, MI);
284 case X86::SAR32ri: return MakeMIInst(X86::SAR32mi, FrameIndex, MI);
285 case X86::ROL8rCL: return MakeMInst( X86::ROL8mCL ,FrameIndex, MI);
286 case X86::ROL16rCL: return MakeMInst( X86::ROL16mCL,FrameIndex, MI);
287 case X86::ROL32rCL: return MakeMInst( X86::ROL32mCL,FrameIndex, MI);
288 case X86::ROL8ri: return MakeMIInst(X86::ROL8mi , FrameIndex, MI);
289 case X86::ROL16ri: return MakeMIInst(X86::ROL16mi, FrameIndex, MI);
290 case X86::ROL32ri: return MakeMIInst(X86::ROL32mi, FrameIndex, MI);
291 case X86::ROR8rCL: return MakeMInst( X86::ROR8mCL ,FrameIndex, MI);
292 case X86::ROR16rCL: return MakeMInst( X86::ROR16mCL,FrameIndex, MI);
293 case X86::ROR32rCL: return MakeMInst( X86::ROR32mCL,FrameIndex, MI);
294 case X86::ROR8ri: return MakeMIInst(X86::ROR8mi , FrameIndex, MI);
295 case X86::ROR16ri: return MakeMIInst(X86::ROR16mi, FrameIndex, MI);
296 case X86::ROR32ri: return MakeMIInst(X86::ROR32mi, FrameIndex, MI);
297 case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);
298 case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
299 case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
300 case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI);
301 case X86::SHLD16rrCL:return MakeMRInst( X86::SHLD16mrCL,FrameIndex, MI);
302 case X86::SHLD16rri8:return MakeMRIInst(X86::SHLD16mri8,FrameIndex, MI);
303 case X86::SHRD16rrCL:return MakeMRInst( X86::SHRD16mrCL,FrameIndex, MI);
304 case X86::SHRD16rri8:return MakeMRIInst(X86::SHRD16mri8,FrameIndex, MI);
305 case X86::SETBr: return MakeMInst( X86::SETBm, FrameIndex, MI);
306 case X86::SETAEr: return MakeMInst( X86::SETAEm, FrameIndex, MI);
307 case X86::SETEr: return MakeMInst( X86::SETEm, FrameIndex, MI);
308 case X86::SETNEr: return MakeMInst( X86::SETNEm, FrameIndex, MI);
309 case X86::SETBEr: return MakeMInst( X86::SETBEm, FrameIndex, MI);
310 case X86::SETAr: return MakeMInst( X86::SETAm, FrameIndex, MI);
311 case X86::SETSr: return MakeMInst( X86::SETSm, FrameIndex, MI);
312 case X86::SETNSr: return MakeMInst( X86::SETNSm, FrameIndex, MI);
313 case X86::SETPr: return MakeMInst( X86::SETPm, FrameIndex, MI);
314 case X86::SETNPr: return MakeMInst( X86::SETNPm, FrameIndex, MI);
315 case X86::SETLr: return MakeMInst( X86::SETLm, FrameIndex, MI);
316 case X86::SETGEr: return MakeMInst( X86::SETGEm, FrameIndex, MI);
317 case X86::SETLEr: return MakeMInst( X86::SETLEm, FrameIndex, MI);
318 case X86::SETGr: return MakeMInst( X86::SETGm, FrameIndex, MI);
319 case X86::TEST8rr: return MakeMRInst(X86::TEST8mr ,FrameIndex, MI);
320 case X86::TEST16rr: return MakeMRInst(X86::TEST16mr,FrameIndex, MI);
321 case X86::TEST32rr: return MakeMRInst(X86::TEST32mr,FrameIndex, MI);
322 case X86::TEST8ri: return MakeMIInst(X86::TEST8mi ,FrameIndex, MI);
323 case X86::TEST16ri: return MakeMIInst(X86::TEST16mi,FrameIndex, MI);
324 case X86::TEST32ri: return MakeMIInst(X86::TEST32mi,FrameIndex, MI);
325 case X86::CMP8rr: return MakeMRInst(X86::CMP8mr , FrameIndex, MI);
326 case X86::CMP16rr: return MakeMRInst(X86::CMP16mr, FrameIndex, MI);
327 case X86::CMP32rr: return MakeMRInst(X86::CMP32mr, FrameIndex, MI);
328 case X86::CMP8ri: return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
329 case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
330 case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
333 switch(MI->getOpcode()) {
334 case X86::XCHG8rr: return MakeRMInst(X86::XCHG8rm ,FrameIndex, MI);
335 case X86::XCHG16rr: return MakeRMInst(X86::XCHG16rm,FrameIndex, MI);
336 case X86::XCHG32rr: return MakeRMInst(X86::XCHG32rm,FrameIndex, MI);
337 case X86::MOV8rr: return MakeRMInst(X86::MOV8rm , FrameIndex, MI);
338 case X86::MOV16rr: return MakeRMInst(X86::MOV16rm, FrameIndex, MI);
339 case X86::MOV32rr: return MakeRMInst(X86::MOV32rm, FrameIndex, MI);
340 case X86::CMOVB16rr: return MakeRMInst(X86::CMOVB16rm , FrameIndex, MI);
341 case X86::CMOVB32rr: return MakeRMInst(X86::CMOVB32rm , FrameIndex, MI);
342 case X86::CMOVAE16rr: return MakeRMInst(X86::CMOVAE16rm , FrameIndex, MI);
343 case X86::CMOVAE32rr: return MakeRMInst(X86::CMOVAE32rm , FrameIndex, MI);
344 case X86::CMOVE16rr: return MakeRMInst(X86::CMOVE16rm , FrameIndex, MI);
345 case X86::CMOVE32rr: return MakeRMInst(X86::CMOVE32rm , FrameIndex, MI);
346 case X86::CMOVNE16rr:return MakeRMInst(X86::CMOVNE16rm, FrameIndex, MI);
347 case X86::CMOVNE32rr:return MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI);
348 case X86::CMOVBE16rr:return MakeRMInst(X86::CMOVBE16rm, FrameIndex, MI);
349 case X86::CMOVBE32rr:return MakeRMInst(X86::CMOVBE32rm, FrameIndex, MI);
350 case X86::CMOVA16rr:return MakeRMInst(X86::CMOVA16rm, FrameIndex, MI);
351 case X86::CMOVA32rr:return MakeRMInst(X86::CMOVA32rm, FrameIndex, MI);
352 case X86::CMOVS16rr: return MakeRMInst(X86::CMOVS16rm , FrameIndex, MI);
353 case X86::CMOVS32rr: return MakeRMInst(X86::CMOVS32rm , FrameIndex, MI);
354 case X86::CMOVNS16rr: return MakeRMInst(X86::CMOVNS16rm , FrameIndex, MI);
355 case X86::CMOVNS32rr: return MakeRMInst(X86::CMOVNS32rm , FrameIndex, MI);
356 case X86::CMOVP16rr: return MakeRMInst(X86::CMOVP16rm , FrameIndex, MI);
357 case X86::CMOVP32rr: return MakeRMInst(X86::CMOVP32rm , FrameIndex, MI);
358 case X86::CMOVNP16rr: return MakeRMInst(X86::CMOVNP16rm , FrameIndex, MI);
359 case X86::CMOVNP32rr: return MakeRMInst(X86::CMOVNP32rm , FrameIndex, MI);
360 case X86::CMOVL16rr: return MakeRMInst(X86::CMOVL16rm , FrameIndex, MI);
361 case X86::CMOVL32rr: return MakeRMInst(X86::CMOVL32rm , FrameIndex, MI);
362 case X86::CMOVGE16rr: return MakeRMInst(X86::CMOVGE16rm , FrameIndex, MI);
363 case X86::CMOVGE32rr: return MakeRMInst(X86::CMOVGE32rm , FrameIndex, MI);
364 case X86::CMOVLE16rr: return MakeRMInst(X86::CMOVLE16rm , FrameIndex, MI);
365 case X86::CMOVLE32rr: return MakeRMInst(X86::CMOVLE32rm , FrameIndex, MI);
366 case X86::CMOVG16rr: return MakeRMInst(X86::CMOVG16rm , FrameIndex, MI);
367 case X86::CMOVG32rr: return MakeRMInst(X86::CMOVG32rm , FrameIndex, MI);
368 case X86::ADD8rr: return MakeRMInst(X86::ADD8rm , FrameIndex, MI);
369 case X86::ADD16rr: return MakeRMInst(X86::ADD16rm, FrameIndex, MI);
370 case X86::ADD32rr: return MakeRMInst(X86::ADD32rm, FrameIndex, MI);
371 case X86::ADC32rr: return MakeRMInst(X86::ADC32rm, FrameIndex, MI);
372 case X86::SUB8rr: return MakeRMInst(X86::SUB8rm , FrameIndex, MI);
373 case X86::SUB16rr: return MakeRMInst(X86::SUB16rm, FrameIndex, MI);
374 case X86::SUB32rr: return MakeRMInst(X86::SUB32rm, FrameIndex, MI);
375 case X86::SBB32rr: return MakeRMInst(X86::SBB32rm, FrameIndex, MI);
376 case X86::AND8rr: return MakeRMInst(X86::AND8rm , FrameIndex, MI);
377 case X86::AND16rr: return MakeRMInst(X86::AND16rm, FrameIndex, MI);
378 case X86::AND32rr: return MakeRMInst(X86::AND32rm, FrameIndex, MI);
379 case X86::OR8rr: return MakeRMInst(X86::OR8rm , FrameIndex, MI);
380 case X86::OR16rr: return MakeRMInst(X86::OR16rm, FrameIndex, MI);
381 case X86::OR32rr: return MakeRMInst(X86::OR32rm, FrameIndex, MI);
382 case X86::XOR8rr: return MakeRMInst(X86::XOR8rm , FrameIndex, MI);
383 case X86::XOR16rr: return MakeRMInst(X86::XOR16rm, FrameIndex, MI);
384 case X86::XOR32rr: return MakeRMInst(X86::XOR32rm, FrameIndex, MI);
385 case X86::TEST8rr: return MakeRMInst(X86::TEST8rm ,FrameIndex, MI);
386 case X86::TEST16rr: return MakeRMInst(X86::TEST16rm,FrameIndex, MI);
387 case X86::TEST32rr: return MakeRMInst(X86::TEST32rm,FrameIndex, MI);
388 case X86::IMUL16rr: return MakeRMInst(X86::IMUL16rm,FrameIndex, MI);
389 case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI);
390 case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);
391 case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI);
392 case X86::CMP8rr: return MakeRMInst(X86::CMP8rm , FrameIndex, MI);
393 case X86::CMP16rr: return MakeRMInst(X86::CMP16rm, FrameIndex, MI);
394 case X86::CMP32rr: return MakeRMInst(X86::CMP32rm, FrameIndex, MI);
395 case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI);
396 case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI);
397 case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI);
398 case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI);
399 case X86::MOVZX32rr8: return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
400 case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI);
403 if (PrintFailedFusing)
404 std::cerr << "We failed to fuse: " << *MI;
408 //===----------------------------------------------------------------------===//
409 // Stack Frame Processing methods
410 //===----------------------------------------------------------------------===//
412 // hasFP - Return true if the specified function should have a dedicated frame
413 // pointer register. This is true if the function has variable sized allocas or
414 // if frame pointer elimination is disabled.
416 static bool hasFP(MachineFunction &MF) {
417 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
420 void X86RegisterInfo::
421 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
422 MachineBasicBlock::iterator I) const {
424 // If we have a frame pointer, turn the adjcallstackup instruction into a
425 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
427 MachineInstr *Old = I;
428 unsigned Amount = Old->getOperand(0).getImmedValue();
430 // We need to keep the stack aligned properly. To do this, we round the
431 // amount of space needed for the outgoing arguments up to the next
432 // alignment boundary.
433 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
434 Amount = (Amount+Align-1)/Align*Align;
436 MachineInstr *New = 0;
437 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
438 New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
441 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
442 // factor out the amount the callee already popped.
443 unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
446 New = BuildMI(X86::ADD32ri, 1, X86::ESP,
447 MachineOperand::UseAndDef).addZImm(Amount);
450 // Replace the pseudo instruction with a new instruction...
451 if (New) MBB.insert(I, New);
453 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
454 // If we are performing frame pointer elimination and if the callee pops
455 // something off the stack pointer, add it back. We do this until we have
456 // more advanced stack pointer tracking ability.
457 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
459 BuildMI(X86::SUB32ri, 1, X86::ESP,
460 MachineOperand::UseAndDef).addZImm(CalleeAmt);
468 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
470 MachineInstr &MI = *II;
471 MachineFunction &MF = *MI.getParent()->getParent();
472 while (!MI.getOperand(i).isFrameIndex()) {
474 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
477 int FrameIndex = MI.getOperand(i).getFrameIndex();
479 // This must be part of a four operand memory reference. Replace the
480 // FrameIndex with base register with EBP. Add add an offset to the offset.
481 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
483 // Now add the frame object offset to the offset from EBP.
484 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
485 MI.getOperand(i+3).getImmedValue()+4;
488 Offset += MF.getFrameInfo()->getStackSize();
490 Offset += 4; // Skip the saved EBP
492 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
496 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
498 // Create a frame entry for the EBP register that must be saved.
499 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
500 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
501 "Slot for EBP register must be last in order to be found!");
505 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
506 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
507 MachineBasicBlock::iterator MBBI = MBB.begin();
508 MachineFrameInfo *MFI = MF.getFrameInfo();
511 // Get the number of bytes to allocate from the FrameInfo
512 unsigned NumBytes = MFI->getStackSize();
514 // Get the offset of the stack slot for the EBP register... which is
515 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
516 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
518 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
519 MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
521 MBB.insert(MBBI, MI);
524 // Save EBP into the appropriate stack slot...
525 MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP
526 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
527 MBB.insert(MBBI, MI);
529 // Update EBP with the new base value...
530 if (NumBytes == 4) // mov EBP, ESP
531 MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
532 else // lea EBP, [ESP+StackSize]
533 MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
535 MBB.insert(MBBI, MI);
538 if (MFI->hasCalls()) {
539 // When we have no frame pointer, we reserve argument space for call sites
540 // in the function immediately on entry to the current function. This
541 // eliminates the need for add/sub ESP brackets around call sites.
543 NumBytes += MFI->getMaxCallFrameSize();
545 // Round the size to a multiple of the alignment (don't forget the 4 byte
547 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
548 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
551 // Update frame info to pretend that this is part of the stack...
552 MFI->setStackSize(NumBytes);
555 // adjust stack pointer: ESP -= numbytes
556 MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
558 MBB.insert(MBBI, MI);
563 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
564 MachineBasicBlock &MBB) const {
565 const MachineFrameInfo *MFI = MF.getFrameInfo();
566 MachineBasicBlock::iterator MBBI = prior(MBB.end());
568 switch (MBBI->getOpcode()) {
573 case X86::TAILJMPm: break; // These are ok
575 assert(0 && "Can only insert epilog into returning blocks");
579 // Get the offset of the stack slot for the EBP register... which is
580 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
581 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
584 BuildMI(MBB, MBBI, X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP);
587 BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP);
589 // Get the number of bytes allocated from the FrameInfo...
590 unsigned NumBytes = MFI->getStackSize();
592 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
593 // If there is an ADD32ri or SUB32ri of ESP immediately before this
594 // instruction, merge the two instructions.
595 if (MBBI != MBB.begin()) {
596 MachineBasicBlock::iterator PI = prior(MBBI);
597 if (PI->getOpcode() == X86::ADD32ri &&
598 PI->getOperand(0).getReg() == X86::ESP) {
599 NumBytes += PI->getOperand(1).getImmedValue();
601 } else if (PI->getOpcode() == X86::SUB32ri &&
602 PI->getOperand(0).getReg() == X86::ESP) {
603 NumBytes -= PI->getOperand(1).getImmedValue();
605 } else if (PI->getOpcode() == X86::ADJSTACKPTRri) {
606 NumBytes += PI->getOperand(1).getImmedValue();
612 BuildMI(MBB, MBBI, X86::ADD32ri, 2)
613 .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(NumBytes);
614 else if ((int)NumBytes < 0)
615 BuildMI(MBB, MBBI, X86::SUB32ri, 2)
616 .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(-NumBytes);
621 #include "X86GenRegisterInfo.inc"