1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/ADT/STLExtras.h"
40 NoFusing("disable-spill-fusing",
41 cl::desc("Disable fusing of spill code into instructions"));
43 PrintFailedFusing("print-failed-fuse-candidates",
44 cl::desc("Print instructions that the allocator wants to"
45 " fuse, but the X86 backend currently can't"),
49 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
50 const TargetInstrInfo &tii)
51 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
67 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator MI,
69 unsigned SrcReg, int FrameIdx,
70 const TargetRegisterClass *RC) const {
72 if (RC == &X86::GR64RegClass) {
74 } else if (RC == &X86::GR32RegClass) {
76 } else if (RC == &X86::GR16RegClass) {
78 } else if (RC == &X86::GR8RegClass) {
80 } else if (RC == &X86::GR32_RegClass) {
82 } else if (RC == &X86::GR16_RegClass) {
84 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
86 } else if (RC == &X86::FR32RegClass) {
88 } else if (RC == &X86::FR64RegClass) {
90 } else if (RC == &X86::VR128RegClass) {
93 assert(0 && "Unknown regclass");
96 addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
99 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
100 MachineBasicBlock::iterator MI,
101 unsigned DestReg, int FrameIdx,
102 const TargetRegisterClass *RC) const{
104 if (RC == &X86::GR64RegClass) {
106 } else if (RC == &X86::GR32RegClass) {
108 } else if (RC == &X86::GR16RegClass) {
110 } else if (RC == &X86::GR8RegClass) {
112 } else if (RC == &X86::GR32_RegClass) {
114 } else if (RC == &X86::GR16_RegClass) {
116 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
118 } else if (RC == &X86::FR32RegClass) {
120 } else if (RC == &X86::FR64RegClass) {
122 } else if (RC == &X86::VR128RegClass) {
125 assert(0 && "Unknown regclass");
128 addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
131 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator MI,
133 unsigned DestReg, unsigned SrcReg,
134 const TargetRegisterClass *RC) const {
136 if (RC == &X86::GR64RegClass) {
138 } else if (RC == &X86::GR32RegClass) {
140 } else if (RC == &X86::GR16RegClass) {
142 } else if (RC == &X86::GR8RegClass) {
144 } else if (RC == &X86::GR32_RegClass) {
146 } else if (RC == &X86::GR16_RegClass) {
148 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
150 } else if (RC == &X86::FR32RegClass) {
151 Opc = X86::FsMOVAPSrr;
152 } else if (RC == &X86::FR64RegClass) {
153 Opc = X86::FsMOVAPDrr;
154 } else if (RC == &X86::VR128RegClass) {
157 assert(0 && "Unknown regclass");
160 BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
163 static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
165 unsigned NumOps = MI->getNumOperands()-2;
166 // Create the base instruction with the memory operand as the first part.
167 MachineInstrBuilder MIB = addFrameReference(BuildMI(Opcode, 4+NumOps),
170 // Loop over the rest of the ri operands, converting them over.
171 for (unsigned i = 0; i != NumOps; ++i) {
172 MachineOperand &MO = MI->getOperand(i+2);
174 MIB = MIB.addReg(MO.getReg());
176 MIB = MIB.addImm(MO.getImm());
177 else if (MO.isGlobalAddress())
178 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
179 else if (MO.isJumpTableIndex())
180 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
182 assert(0 && "Unknown operand type!");
187 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
188 unsigned FrameIndex, MachineInstr *MI) {
189 MachineInstrBuilder MIB = BuildMI(Opcode, MI->getNumOperands()+3);
191 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
192 MachineOperand &MO = MI->getOperand(i);
194 assert(MO.isReg() && "Expected to fold into reg operand!");
195 MIB = addFrameReference(MIB, FrameIndex);
196 } else if (MO.isReg())
197 MIB = MIB.addReg(MO.getReg(), MO.isDef());
199 MIB = MIB.addImm(MO.getImm());
200 else if (MO.isGlobalAddress())
201 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
202 else if (MO.isJumpTableIndex())
203 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
205 assert(0 && "Unknown operand for FuseInst!");
210 static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
212 return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0);
216 //===----------------------------------------------------------------------===//
217 // Efficient Lookup Table Support
218 //===----------------------------------------------------------------------===//
221 /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode.
224 unsigned from; // Original opcode.
225 unsigned to; // New opcode.
227 // less operators used by STL search.
228 bool operator<(const TableEntry &TE) const { return from < TE.from; }
229 friend bool operator<(const TableEntry &TE, unsigned V) {
232 friend bool operator<(unsigned V, const TableEntry &TE) {
238 /// TableIsSorted - Return true if the table is in 'from' opcode order.
240 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
241 for (unsigned i = 1; i != NumEntries; ++i)
242 if (!(Table[i-1] < Table[i])) {
243 std::cerr << "Entries out of order " << Table[i-1].from
244 << " " << Table[i].from << "\n";
250 /// TableLookup - Return the table entry matching the specified opcode.
251 /// Otherwise return NULL.
252 static const TableEntry *TableLookup(const TableEntry *Table, unsigned N,
254 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
255 if (I != Table+N && I->from == Opcode)
260 #define ARRAY_SIZE(TABLE) \
261 (sizeof(TABLE)/sizeof(TABLE[0]))
264 #define ASSERT_SORTED(TABLE)
266 #define ASSERT_SORTED(TABLE) \
267 { static bool TABLE##Checked = false; \
268 if (!TABLE##Checked) { \
269 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
270 "All lookup tables must be sorted for efficient access!"); \
271 TABLE##Checked = true; \
277 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
279 int FrameIndex) const {
281 if (NoFusing) return NULL;
283 // Table (and size) to search
284 const TableEntry *OpcodeTablePtr = NULL;
285 unsigned OpcodeTableSize = 0;
286 bool isTwoAddrFold = false;
288 // Folding a memory location into the two-address part of a two-address
289 // instruction is different than folding it other places. It requires
290 // replacing the *two* registers with the memory location.
291 if (MI->getNumOperands() >= 2 && MI->getOperand(0).isReg() &&
292 MI->getOperand(1).isReg() && i < 2 &&
293 MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
294 TII.isTwoAddrInstr(MI->getOpcode())) {
295 static const TableEntry OpcodeTable[] = {
296 { X86::ADC32ri, X86::ADC32mi },
297 { X86::ADC32ri8, X86::ADC32mi8 },
298 { X86::ADC32rr, X86::ADC32mr },
299 { X86::ADC64ri32, X86::ADC64mi32 },
300 { X86::ADC64ri8, X86::ADC64mi8 },
301 { X86::ADC64rr, X86::ADC64mr },
302 { X86::ADD16ri, X86::ADD16mi },
303 { X86::ADD16ri8, X86::ADD16mi8 },
304 { X86::ADD16rr, X86::ADD16mr },
305 { X86::ADD32ri, X86::ADD32mi },
306 { X86::ADD32ri8, X86::ADD32mi8 },
307 { X86::ADD32rr, X86::ADD32mr },
308 { X86::ADD64ri32, X86::ADD64mi32 },
309 { X86::ADD64ri8, X86::ADD64mi8 },
310 { X86::ADD64rr, X86::ADD64mr },
311 { X86::ADD8ri, X86::ADD8mi },
312 { X86::ADD8rr, X86::ADD8mr },
313 { X86::AND16ri, X86::AND16mi },
314 { X86::AND16ri8, X86::AND16mi8 },
315 { X86::AND16rr, X86::AND16mr },
316 { X86::AND32ri, X86::AND32mi },
317 { X86::AND32ri8, X86::AND32mi8 },
318 { X86::AND32rr, X86::AND32mr },
319 { X86::AND64ri32, X86::AND64mi32 },
320 { X86::AND64ri8, X86::AND64mi8 },
321 { X86::AND64rr, X86::AND64mr },
322 { X86::AND8ri, X86::AND8mi },
323 { X86::AND8rr, X86::AND8mr },
324 { X86::DEC16r, X86::DEC16m },
325 { X86::DEC32r, X86::DEC32m },
326 { X86::DEC64_16r, X86::DEC16m },
327 { X86::DEC64_32r, X86::DEC32m },
328 { X86::DEC64r, X86::DEC64m },
329 { X86::DEC8r, X86::DEC8m },
330 { X86::INC16r, X86::INC16m },
331 { X86::INC32r, X86::INC32m },
332 { X86::INC64_16r, X86::INC16m },
333 { X86::INC64_32r, X86::INC32m },
334 { X86::INC64r, X86::INC64m },
335 { X86::INC8r, X86::INC8m },
336 { X86::NEG16r, X86::NEG16m },
337 { X86::NEG32r, X86::NEG32m },
338 { X86::NEG64r, X86::NEG64m },
339 { X86::NEG8r, X86::NEG8m },
340 { X86::NOT16r, X86::NOT16m },
341 { X86::NOT32r, X86::NOT32m },
342 { X86::NOT64r, X86::NOT64m },
343 { X86::NOT8r, X86::NOT8m },
344 { X86::OR16ri, X86::OR16mi },
345 { X86::OR16ri8, X86::OR16mi8 },
346 { X86::OR16rr, X86::OR16mr },
347 { X86::OR32ri, X86::OR32mi },
348 { X86::OR32ri8, X86::OR32mi8 },
349 { X86::OR32rr, X86::OR32mr },
350 { X86::OR64ri32, X86::OR64mi32 },
351 { X86::OR64ri8, X86::OR64mi8 },
352 { X86::OR64rr, X86::OR64mr },
353 { X86::OR8ri, X86::OR8mi },
354 { X86::OR8rr, X86::OR8mr },
355 { X86::ROL16r1, X86::ROL16m1 },
356 { X86::ROL16rCL, X86::ROL16mCL },
357 { X86::ROL16ri, X86::ROL16mi },
358 { X86::ROL32r1, X86::ROL32m1 },
359 { X86::ROL32rCL, X86::ROL32mCL },
360 { X86::ROL32ri, X86::ROL32mi },
361 { X86::ROL64r1, X86::ROL64m1 },
362 { X86::ROL64rCL, X86::ROL64mCL },
363 { X86::ROL64ri, X86::ROL64mi },
364 { X86::ROL8r1, X86::ROL8m1 },
365 { X86::ROL8rCL, X86::ROL8mCL },
366 { X86::ROL8ri, X86::ROL8mi },
367 { X86::ROR16r1, X86::ROR16m1 },
368 { X86::ROR16rCL, X86::ROR16mCL },
369 { X86::ROR16ri, X86::ROR16mi },
370 { X86::ROR32r1, X86::ROR32m1 },
371 { X86::ROR32rCL, X86::ROR32mCL },
372 { X86::ROR32ri, X86::ROR32mi },
373 { X86::ROR64r1, X86::ROR64m1 },
374 { X86::ROR64rCL, X86::ROR64mCL },
375 { X86::ROR64ri, X86::ROR64mi },
376 { X86::ROR8r1, X86::ROR8m1 },
377 { X86::ROR8rCL, X86::ROR8mCL },
378 { X86::ROR8ri, X86::ROR8mi },
379 { X86::SAR16r1, X86::SAR16m1 },
380 { X86::SAR16rCL, X86::SAR16mCL },
381 { X86::SAR16ri, X86::SAR16mi },
382 { X86::SAR32r1, X86::SAR32m1 },
383 { X86::SAR32rCL, X86::SAR32mCL },
384 { X86::SAR32ri, X86::SAR32mi },
385 { X86::SAR64r1, X86::SAR64m1 },
386 { X86::SAR64rCL, X86::SAR64mCL },
387 { X86::SAR64ri, X86::SAR64mi },
388 { X86::SAR8r1, X86::SAR8m1 },
389 { X86::SAR8rCL, X86::SAR8mCL },
390 { X86::SAR8ri, X86::SAR8mi },
391 { X86::SBB32ri, X86::SBB32mi },
392 { X86::SBB32ri8, X86::SBB32mi8 },
393 { X86::SBB32rr, X86::SBB32mr },
394 { X86::SBB64ri32, X86::SBB64mi32 },
395 { X86::SBB64ri8, X86::SBB64mi8 },
396 { X86::SBB64rr, X86::SBB64mr },
397 { X86::SHL16r1, X86::SHL16m1 },
398 { X86::SHL16rCL, X86::SHL16mCL },
399 { X86::SHL16ri, X86::SHL16mi },
400 { X86::SHL32r1, X86::SHL32m1 },
401 { X86::SHL32rCL, X86::SHL32mCL },
402 { X86::SHL32ri, X86::SHL32mi },
403 { X86::SHL64r1, X86::SHL64m1 },
404 { X86::SHL64rCL, X86::SHL64mCL },
405 { X86::SHL64ri, X86::SHL64mi },
406 { X86::SHL8r1, X86::SHL8m1 },
407 { X86::SHL8rCL, X86::SHL8mCL },
408 { X86::SHL8ri, X86::SHL8mi },
409 { X86::SHLD16rrCL, X86::SHLD16mrCL },
410 { X86::SHLD16rri8, X86::SHLD16mri8 },
411 { X86::SHLD32rrCL, X86::SHLD32mrCL },
412 { X86::SHLD32rri8, X86::SHLD32mri8 },
413 { X86::SHLD64rrCL, X86::SHLD64mrCL },
414 { X86::SHLD64rri8, X86::SHLD64mri8 },
415 { X86::SHR16r1, X86::SHR16m1 },
416 { X86::SHR16rCL, X86::SHR16mCL },
417 { X86::SHR16ri, X86::SHR16mi },
418 { X86::SHR32r1, X86::SHR32m1 },
419 { X86::SHR32rCL, X86::SHR32mCL },
420 { X86::SHR32ri, X86::SHR32mi },
421 { X86::SHR64r1, X86::SHR64m1 },
422 { X86::SHR64rCL, X86::SHR64mCL },
423 { X86::SHR64ri, X86::SHR64mi },
424 { X86::SHR8r1, X86::SHR8m1 },
425 { X86::SHR8rCL, X86::SHR8mCL },
426 { X86::SHR8ri, X86::SHR8mi },
427 { X86::SHRD16rrCL, X86::SHRD16mrCL },
428 { X86::SHRD16rri8, X86::SHRD16mri8 },
429 { X86::SHRD32rrCL, X86::SHRD32mrCL },
430 { X86::SHRD32rri8, X86::SHRD32mri8 },
431 { X86::SHRD64rrCL, X86::SHRD64mrCL },
432 { X86::SHRD64rri8, X86::SHRD64mri8 },
433 { X86::SUB16ri, X86::SUB16mi },
434 { X86::SUB16ri8, X86::SUB16mi8 },
435 { X86::SUB16rr, X86::SUB16mr },
436 { X86::SUB32ri, X86::SUB32mi },
437 { X86::SUB32ri8, X86::SUB32mi8 },
438 { X86::SUB32rr, X86::SUB32mr },
439 { X86::SUB64ri32, X86::SUB64mi32 },
440 { X86::SUB64ri8, X86::SUB64mi8 },
441 { X86::SUB64rr, X86::SUB64mr },
442 { X86::SUB8ri, X86::SUB8mi },
443 { X86::SUB8rr, X86::SUB8mr },
444 { X86::XOR16ri, X86::XOR16mi },
445 { X86::XOR16ri8, X86::XOR16mi8 },
446 { X86::XOR16rr, X86::XOR16mr },
447 { X86::XOR32ri, X86::XOR32mi },
448 { X86::XOR32ri8, X86::XOR32mi8 },
449 { X86::XOR32rr, X86::XOR32mr },
450 { X86::XOR64ri32, X86::XOR64mi32 },
451 { X86::XOR64ri8, X86::XOR64mi8 },
452 { X86::XOR64rr, X86::XOR64mr },
453 { X86::XOR8ri, X86::XOR8mi },
454 { X86::XOR8rr, X86::XOR8mr }
456 ASSERT_SORTED(OpcodeTable);
457 OpcodeTablePtr = OpcodeTable;
458 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
459 isTwoAddrFold = true;
460 } else if (i == 0) { // If operand 0
461 if (MI->getOpcode() == X86::MOV16r0)
462 return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
463 else if (MI->getOpcode() == X86::MOV32r0)
464 return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
465 else if (MI->getOpcode() == X86::MOV64r0)
466 return MakeM0Inst(X86::MOV64mi32, FrameIndex, MI);
467 else if (MI->getOpcode() == X86::MOV8r0)
468 return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
470 static const TableEntry OpcodeTable[] = {
471 { X86::CMP16ri, X86::CMP16mi },
472 { X86::CMP16ri8, X86::CMP16mi8 },
473 { X86::CMP32ri, X86::CMP32mi },
474 { X86::CMP32ri8, X86::CMP32mi8 },
475 { X86::CMP8ri, X86::CMP8mi },
476 { X86::DIV16r, X86::DIV16m },
477 { X86::DIV32r, X86::DIV32m },
478 { X86::DIV64r, X86::DIV64m },
479 { X86::DIV8r, X86::DIV8m },
480 { X86::FsMOVAPDrr, X86::MOVSDmr },
481 { X86::FsMOVAPSrr, X86::MOVSSmr },
482 { X86::IDIV16r, X86::IDIV16m },
483 { X86::IDIV32r, X86::IDIV32m },
484 { X86::IDIV64r, X86::IDIV64m },
485 { X86::IDIV8r, X86::IDIV8m },
486 { X86::IMUL16r, X86::IMUL16m },
487 { X86::IMUL32r, X86::IMUL32m },
488 { X86::IMUL64r, X86::IMUL64m },
489 { X86::IMUL8r, X86::IMUL8m },
490 { X86::MOV16ri, X86::MOV16mi },
491 { X86::MOV16rr, X86::MOV16mr },
492 { X86::MOV32ri, X86::MOV32mi },
493 { X86::MOV32rr, X86::MOV32mr },
494 { X86::MOV64ri32, X86::MOV64mi32 },
495 { X86::MOV64rr, X86::MOV64mr },
496 { X86::MOV8ri, X86::MOV8mi },
497 { X86::MOV8rr, X86::MOV8mr },
498 { X86::MOVAPDrr, X86::MOVAPDmr },
499 { X86::MOVAPSrr, X86::MOVAPSmr },
500 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
501 { X86::MOVPS2SSrr, X86::MOVPS2SSmr },
502 { X86::MOVSDrr, X86::MOVSDmr },
503 { X86::MOVSSrr, X86::MOVSSmr },
504 { X86::MOVUPDrr, X86::MOVUPDmr },
505 { X86::MOVUPSrr, X86::MOVUPSmr },
506 { X86::MUL16r, X86::MUL16m },
507 { X86::MUL32r, X86::MUL32m },
508 { X86::MUL64r, X86::MUL64m },
509 { X86::MUL8r, X86::MUL8m },
510 { X86::SETAEr, X86::SETAEm },
511 { X86::SETAr, X86::SETAm },
512 { X86::SETBEr, X86::SETBEm },
513 { X86::SETBr, X86::SETBm },
514 { X86::SETEr, X86::SETEm },
515 { X86::SETGEr, X86::SETGEm },
516 { X86::SETGr, X86::SETGm },
517 { X86::SETLEr, X86::SETLEm },
518 { X86::SETLr, X86::SETLm },
519 { X86::SETNEr, X86::SETNEm },
520 { X86::SETNPr, X86::SETNPm },
521 { X86::SETNSr, X86::SETNSm },
522 { X86::SETPr, X86::SETPm },
523 { X86::SETSr, X86::SETSm },
524 { X86::TEST16ri, X86::TEST16mi },
525 { X86::TEST32ri, X86::TEST32mi },
526 { X86::TEST64ri32, X86::TEST64mi32 },
527 { X86::TEST8ri, X86::TEST8mi },
528 { X86::XCHG16rr, X86::XCHG16mr },
529 { X86::XCHG32rr, X86::XCHG32mr },
530 { X86::XCHG64rr, X86::XCHG64mr },
531 { X86::XCHG8rr, X86::XCHG8mr }
533 ASSERT_SORTED(OpcodeTable);
534 OpcodeTablePtr = OpcodeTable;
535 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
537 static const TableEntry OpcodeTable[] = {
538 { X86::CMP16rr, X86::CMP16rm },
539 { X86::CMP32rr, X86::CMP32rm },
540 { X86::CMP64ri32, X86::CMP64mi32 },
541 { X86::CMP64ri8, X86::CMP64mi8 },
542 { X86::CMP64rr, X86::CMP64rm },
543 { X86::CMP8rr, X86::CMP8rm },
544 { X86::CMPPDrri, X86::CMPPDrmi },
545 { X86::CMPPSrri, X86::CMPPSrmi },
546 { X86::CMPSDrr, X86::CMPSDrm },
547 { X86::CMPSSrr, X86::CMPSSrm },
548 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
549 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
550 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
551 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
552 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
553 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
554 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
555 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
556 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
557 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
558 { X86::FsMOVAPDrr, X86::MOVSDrm },
559 { X86::FsMOVAPSrr, X86::MOVSSrm },
560 { X86::IMUL16rri, X86::IMUL16rmi },
561 { X86::IMUL16rri8, X86::IMUL16rmi8 },
562 { X86::IMUL32rri, X86::IMUL32rmi },
563 { X86::IMUL32rri8, X86::IMUL32rmi8 },
564 { X86::IMUL64rr, X86::IMUL64rm },
565 { X86::IMUL64rri32, X86::IMUL64rmi32 },
566 { X86::IMUL64rri8, X86::IMUL64rmi8 },
567 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
568 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
569 { X86::Int_COMISDrr, X86::Int_COMISDrm },
570 { X86::Int_COMISSrr, X86::Int_COMISSrm },
571 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
572 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
573 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
574 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
575 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
576 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
577 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
578 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
579 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
580 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
581 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
582 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
583 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
584 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
585 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
586 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
587 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
588 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
589 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
590 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
591 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
592 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
593 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
594 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
595 { X86::MOV16rr, X86::MOV16rm },
596 { X86::MOV32rr, X86::MOV32rm },
597 { X86::MOV64rr, X86::MOV64rm },
598 { X86::MOV8rr, X86::MOV8rm },
599 { X86::MOVAPDrr, X86::MOVAPDrm },
600 { X86::MOVAPSrr, X86::MOVAPSrm },
601 { X86::MOVDDUPrr, X86::MOVDDUPrm },
602 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
603 { X86::MOVQI2PQIrr, X86::MOVQI2PQIrm },
604 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
605 { X86::MOVSDrr, X86::MOVSDrm },
606 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
607 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
608 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
609 { X86::MOVSSrr, X86::MOVSSrm },
610 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
611 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
612 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
613 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
614 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
615 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
616 { X86::MOVUPDrr, X86::MOVUPDrm },
617 { X86::MOVUPSrr, X86::MOVUPSrm },
618 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
619 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
620 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
621 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
622 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
623 { X86::PSHUFDri, X86::PSHUFDmi },
624 { X86::PSHUFHWri, X86::PSHUFHWmi },
625 { X86::PSHUFLWri, X86::PSHUFLWmi },
626 { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
627 { X86::TEST16rr, X86::TEST16rm },
628 { X86::TEST32rr, X86::TEST32rm },
629 { X86::TEST64rr, X86::TEST64rm },
630 { X86::TEST8rr, X86::TEST8rm },
631 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
632 { X86::UCOMISDrr, X86::UCOMISDrm },
633 { X86::UCOMISSrr, X86::UCOMISSrm },
634 { X86::XCHG16rr, X86::XCHG16rm },
635 { X86::XCHG32rr, X86::XCHG32rm },
636 { X86::XCHG64rr, X86::XCHG64rm },
637 { X86::XCHG8rr, X86::XCHG8rm }
639 ASSERT_SORTED(OpcodeTable);
640 OpcodeTablePtr = OpcodeTable;
641 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
643 static const TableEntry OpcodeTable[] = {
644 { X86::ADC32rr, X86::ADC32rm },
645 { X86::ADC64rr, X86::ADC64rm },
646 { X86::ADD16rr, X86::ADD16rm },
647 { X86::ADD32rr, X86::ADD32rm },
648 { X86::ADD64rr, X86::ADD64rm },
649 { X86::ADD8rr, X86::ADD8rm },
650 { X86::ADDPDrr, X86::ADDPDrm },
651 { X86::ADDPSrr, X86::ADDPSrm },
652 { X86::ADDSDrr, X86::ADDSDrm },
653 { X86::ADDSSrr, X86::ADDSSrm },
654 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
655 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
656 { X86::AND16rr, X86::AND16rm },
657 { X86::AND32rr, X86::AND32rm },
658 { X86::AND64rr, X86::AND64rm },
659 { X86::AND8rr, X86::AND8rm },
660 { X86::ANDNPDrr, X86::ANDNPDrm },
661 { X86::ANDNPSrr, X86::ANDNPSrm },
662 { X86::ANDPDrr, X86::ANDPDrm },
663 { X86::ANDPSrr, X86::ANDPSrm },
664 { X86::CMOVA16rr, X86::CMOVA16rm },
665 { X86::CMOVA32rr, X86::CMOVA32rm },
666 { X86::CMOVA64rr, X86::CMOVA64rm },
667 { X86::CMOVAE16rr, X86::CMOVAE16rm },
668 { X86::CMOVAE32rr, X86::CMOVAE32rm },
669 { X86::CMOVAE64rr, X86::CMOVAE64rm },
670 { X86::CMOVB16rr, X86::CMOVB16rm },
671 { X86::CMOVB32rr, X86::CMOVB32rm },
672 { X86::CMOVB64rr, X86::CMOVB64rm },
673 { X86::CMOVBE16rr, X86::CMOVBE16rm },
674 { X86::CMOVBE32rr, X86::CMOVBE32rm },
675 { X86::CMOVBE64rr, X86::CMOVBE64rm },
676 { X86::CMOVE16rr, X86::CMOVE16rm },
677 { X86::CMOVE32rr, X86::CMOVE32rm },
678 { X86::CMOVE64rr, X86::CMOVE64rm },
679 { X86::CMOVG16rr, X86::CMOVG16rm },
680 { X86::CMOVG32rr, X86::CMOVG32rm },
681 { X86::CMOVG64rr, X86::CMOVG64rm },
682 { X86::CMOVGE16rr, X86::CMOVGE16rm },
683 { X86::CMOVGE32rr, X86::CMOVGE32rm },
684 { X86::CMOVGE64rr, X86::CMOVGE64rm },
685 { X86::CMOVL16rr, X86::CMOVL16rm },
686 { X86::CMOVL32rr, X86::CMOVL32rm },
687 { X86::CMOVL64rr, X86::CMOVL64rm },
688 { X86::CMOVLE16rr, X86::CMOVLE16rm },
689 { X86::CMOVLE32rr, X86::CMOVLE32rm },
690 { X86::CMOVLE64rr, X86::CMOVLE64rm },
691 { X86::CMOVNE16rr, X86::CMOVNE16rm },
692 { X86::CMOVNE32rr, X86::CMOVNE32rm },
693 { X86::CMOVNE64rr, X86::CMOVNE64rm },
694 { X86::CMOVNP16rr, X86::CMOVNP16rm },
695 { X86::CMOVNP32rr, X86::CMOVNP32rm },
696 { X86::CMOVNP64rr, X86::CMOVNP64rm },
697 { X86::CMOVNS16rr, X86::CMOVNS16rm },
698 { X86::CMOVNS32rr, X86::CMOVNS32rm },
699 { X86::CMOVNS64rr, X86::CMOVNS64rm },
700 { X86::CMOVP16rr, X86::CMOVP16rm },
701 { X86::CMOVP32rr, X86::CMOVP32rm },
702 { X86::CMOVP64rr, X86::CMOVP64rm },
703 { X86::CMOVS16rr, X86::CMOVS16rm },
704 { X86::CMOVS32rr, X86::CMOVS32rm },
705 { X86::CMOVS64rr, X86::CMOVS64rm },
706 { X86::DIVPDrr, X86::DIVPDrm },
707 { X86::DIVPSrr, X86::DIVPSrm },
708 { X86::DIVSDrr, X86::DIVSDrm },
709 { X86::DIVSSrr, X86::DIVSSrm },
710 { X86::HADDPDrr, X86::HADDPDrm },
711 { X86::HADDPSrr, X86::HADDPSrm },
712 { X86::HSUBPDrr, X86::HSUBPDrm },
713 { X86::HSUBPSrr, X86::HSUBPSrm },
714 { X86::IMUL16rr, X86::IMUL16rm },
715 { X86::IMUL32rr, X86::IMUL32rm },
716 { X86::MAXPDrr, X86::MAXPDrm },
717 { X86::MAXPSrr, X86::MAXPSrm },
718 { X86::MINPDrr, X86::MINPDrm },
719 { X86::MINPSrr, X86::MINPSrm },
720 { X86::MULPDrr, X86::MULPDrm },
721 { X86::MULPSrr, X86::MULPSrm },
722 { X86::MULSDrr, X86::MULSDrm },
723 { X86::MULSSrr, X86::MULSSrm },
724 { X86::OR16rr, X86::OR16rm },
725 { X86::OR32rr, X86::OR32rm },
726 { X86::OR64rr, X86::OR64rm },
727 { X86::OR8rr, X86::OR8rm },
728 { X86::ORPDrr, X86::ORPDrm },
729 { X86::ORPSrr, X86::ORPSrm },
730 { X86::PACKSSDWrr, X86::PACKSSDWrm },
731 { X86::PACKSSWBrr, X86::PACKSSWBrm },
732 { X86::PACKUSWBrr, X86::PACKUSWBrm },
733 { X86::PADDBrr, X86::PADDBrm },
734 { X86::PADDDrr, X86::PADDDrm },
735 { X86::PADDSBrr, X86::PADDSBrm },
736 { X86::PADDSWrr, X86::PADDSWrm },
737 { X86::PADDWrr, X86::PADDWrm },
738 { X86::PANDNrr, X86::PANDNrm },
739 { X86::PANDrr, X86::PANDrm },
740 { X86::PAVGBrr, X86::PAVGBrm },
741 { X86::PAVGWrr, X86::PAVGWrm },
742 { X86::PCMPEQBrr, X86::PCMPEQBrm },
743 { X86::PCMPEQDrr, X86::PCMPEQDrm },
744 { X86::PCMPEQWrr, X86::PCMPEQWrm },
745 { X86::PCMPGTBrr, X86::PCMPGTBrm },
746 { X86::PCMPGTDrr, X86::PCMPGTDrm },
747 { X86::PCMPGTWrr, X86::PCMPGTWrm },
748 { X86::PINSRWrri, X86::PINSRWrmi },
749 { X86::PMADDWDrr, X86::PMADDWDrm },
750 { X86::PMAXSWrr, X86::PMAXSWrm },
751 { X86::PMAXUBrr, X86::PMAXUBrm },
752 { X86::PMINSWrr, X86::PMINSWrm },
753 { X86::PMINUBrr, X86::PMINUBrm },
754 { X86::PMULHUWrr, X86::PMULHUWrm },
755 { X86::PMULHWrr, X86::PMULHWrm },
756 { X86::PMULLWrr, X86::PMULLWrm },
757 { X86::PMULUDQrr, X86::PMULUDQrm },
758 { X86::PORrr, X86::PORrm },
759 { X86::PSADBWrr, X86::PSADBWrm },
760 { X86::PSLLDrr, X86::PSLLDrm },
761 { X86::PSLLQrr, X86::PSLLQrm },
762 { X86::PSLLWrr, X86::PSLLWrm },
763 { X86::PSRADrr, X86::PSRADrm },
764 { X86::PSRAWrr, X86::PSRAWrm },
765 { X86::PSRLDrr, X86::PSRLDrm },
766 { X86::PSRLQrr, X86::PSRLQrm },
767 { X86::PSRLWrr, X86::PSRLWrm },
768 { X86::PSUBBrr, X86::PSUBBrm },
769 { X86::PSUBDrr, X86::PSUBDrm },
770 { X86::PSUBSBrr, X86::PSUBSBrm },
771 { X86::PSUBSWrr, X86::PSUBSWrm },
772 { X86::PSUBWrr, X86::PSUBWrm },
773 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
774 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
775 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
776 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
777 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
778 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
779 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
780 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
781 { X86::PXORrr, X86::PXORrm },
782 { X86::RCPPSr, X86::RCPPSm },
783 { X86::RSQRTPSr, X86::RSQRTPSm },
784 { X86::SBB32rr, X86::SBB32rm },
785 { X86::SBB64rr, X86::SBB64rm },
786 { X86::SHUFPDrri, X86::SHUFPDrmi },
787 { X86::SHUFPSrri, X86::SHUFPSrmi },
788 { X86::SQRTPDr, X86::SQRTPDm },
789 { X86::SQRTPSr, X86::SQRTPSm },
790 { X86::SQRTSDr, X86::SQRTSDm },
791 { X86::SQRTSSr, X86::SQRTSSm },
792 { X86::SUB16rr, X86::SUB16rm },
793 { X86::SUB32rr, X86::SUB32rm },
794 { X86::SUB64rr, X86::SUB64rm },
795 { X86::SUB8rr, X86::SUB8rm },
796 { X86::SUBPDrr, X86::SUBPDrm },
797 { X86::SUBPSrr, X86::SUBPSrm },
798 { X86::SUBSDrr, X86::SUBSDrm },
799 { X86::SUBSSrr, X86::SUBSSrm },
800 // FIXME: TEST*rr -> swapped operand of TEST*mr.
801 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
802 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
803 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
804 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
805 { X86::XOR16rr, X86::XOR16rm },
806 { X86::XOR32rr, X86::XOR32rm },
807 { X86::XOR64rr, X86::XOR64rm },
808 { X86::XOR8rr, X86::XOR8rm },
809 { X86::XORPDrr, X86::XORPDrm },
810 { X86::XORPSrr, X86::XORPSrm }
812 ASSERT_SORTED(OpcodeTable);
813 OpcodeTablePtr = OpcodeTable;
814 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
817 // If table selected...
818 if (OpcodeTablePtr) {
819 // Find the Opcode to fuse
820 unsigned fromOpcode = MI->getOpcode();
821 // Lookup fromOpcode in table
822 if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
825 return FuseTwoAddrInst(Entry->to, FrameIndex, MI);
827 return FuseInst(Entry->to, i, FrameIndex, MI);
832 if (PrintFailedFusing)
833 std::cerr << "We failed to fuse ("
834 << ((i == 1) ? "r" : "s") << "): " << *MI;
839 const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
840 static const unsigned CalleeSaveRegs32Bit[] = {
841 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
843 static const unsigned CalleeSaveRegs64Bit[] = {
844 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
847 return Is64Bit ? CalleeSaveRegs64Bit : CalleeSaveRegs32Bit;
850 const TargetRegisterClass* const*
851 X86RegisterInfo::getCalleeSaveRegClasses() const {
852 static const TargetRegisterClass * const CalleeSaveRegClasses32Bit[] = {
853 &X86::GR32RegClass, &X86::GR32RegClass,
854 &X86::GR32RegClass, &X86::GR32RegClass, 0
856 static const TargetRegisterClass * const CalleeSaveRegClasses64Bit[] = {
857 &X86::GR64RegClass, &X86::GR64RegClass,
858 &X86::GR64RegClass, &X86::GR64RegClass,
859 &X86::GR64RegClass, &X86::GR64RegClass, 0
862 return Is64Bit ? CalleeSaveRegClasses64Bit : CalleeSaveRegClasses32Bit;
865 //===----------------------------------------------------------------------===//
866 // Stack Frame Processing methods
867 //===----------------------------------------------------------------------===//
869 // hasFP - Return true if the specified function should have a dedicated frame
870 // pointer register. This is true if the function has variable sized allocas or
871 // if frame pointer elimination is disabled.
873 static bool hasFP(const MachineFunction &MF) {
874 return (NoFramePointerElim ||
875 MF.getFrameInfo()->hasVarSizedObjects() ||
876 MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
879 void X86RegisterInfo::
880 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
881 MachineBasicBlock::iterator I) const {
883 // If we have a frame pointer, turn the adjcallstackup instruction into a
884 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
886 MachineInstr *Old = I;
887 unsigned Amount = Old->getOperand(0).getImmedValue();
889 // We need to keep the stack aligned properly. To do this, we round the
890 // amount of space needed for the outgoing arguments up to the next
891 // alignment boundary.
892 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
893 Amount = (Amount+Align-1)/Align*Align;
895 MachineInstr *New = 0;
896 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
897 New=BuildMI(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr)
898 .addReg(StackPtr).addImm(Amount);
900 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
901 // factor out the amount the callee already popped.
902 unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
905 unsigned Opc = (Amount < 128) ?
906 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
907 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
908 New = BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(Amount);
912 // Replace the pseudo instruction with a new instruction...
913 if (New) MBB.insert(I, New);
915 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
916 // If we are performing frame pointer elimination and if the callee pops
917 // something off the stack pointer, add it back. We do this until we have
918 // more advanced stack pointer tracking ability.
919 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
920 unsigned Opc = (CalleeAmt < 128) ?
921 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
922 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
924 BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt);
932 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
934 MachineInstr &MI = *II;
935 MachineFunction &MF = *MI.getParent()->getParent();
936 while (!MI.getOperand(i).isFrameIndex()) {
938 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
941 int FrameIndex = MI.getOperand(i).getFrameIndex();
942 // This must be part of a four operand memory reference. Replace the
943 // FrameIndex with base register with EBP. Add an offset to the offset.
944 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
946 // Now add the frame object offset to the offset from EBP.
947 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
948 MI.getOperand(i+3).getImmedValue()+SlotSize;
951 Offset += MF.getFrameInfo()->getStackSize();
953 Offset += SlotSize; // Skip the saved EBP
955 MI.getOperand(i+3).ChangeToImmediate(Offset);
959 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
961 // Create a frame entry for the EBP register that must be saved.
962 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,SlotSize * -2);
963 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
964 "Slot for EBP register must be last in order to be found!");
968 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
969 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
970 MachineBasicBlock::iterator MBBI = MBB.begin();
971 MachineFrameInfo *MFI = MF.getFrameInfo();
972 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
973 const Function* Fn = MF.getFunction();
974 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
977 // Get the number of bytes to allocate from the FrameInfo
978 unsigned NumBytes = MFI->getStackSize();
979 if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
980 // When we have no frame pointer, we reserve argument space for call sites
981 // in the function immediately on entry to the current function. This
982 // eliminates the need for add/sub ESP brackets around call sites.
985 NumBytes += MFI->getMaxCallFrameSize();
987 // Round the size to a multiple of the alignment (don't forget the 4/8 byte
989 NumBytes = ((NumBytes+SlotSize)+Align-1)/Align*Align - SlotSize;
992 // Update frame info to pretend that this is part of the stack...
993 MFI->setStackSize(NumBytes);
995 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
996 if (NumBytes >= 4096 && Subtarget->isTargetCygwin()) {
997 // Function prologue calls _alloca to probe the stack when allocating
998 // more than 4k bytes in one go. Touching the stack at 4K increments is
999 // necessary to ensure that the guard pages used by the OS virtual memory
1000 // manager are allocated in correct sequence.
1001 MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
1002 MBB.insert(MBBI, MI);
1003 MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
1004 MBB.insert(MBBI, MI);
1006 unsigned Opc = (NumBytes < 128) ?
1007 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1008 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1009 MI= BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes);
1010 MBB.insert(MBBI, MI);
1015 // Get the offset of the stack slot for the EBP register... which is
1016 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1017 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+SlotSize;
1019 // Save EBP into the appropriate stack slot...
1020 // mov [ESP-<offset>], EBP
1021 MI = addRegOffset(BuildMI(Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5),
1022 StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
1023 MBB.insert(MBBI, MI);
1025 // Update EBP with the new base value...
1026 if (NumBytes == SlotSize) // mov EBP, ESP
1027 MI = BuildMI(Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr).
1029 else // lea EBP, [ESP+StackSize]
1030 MI = addRegOffset(BuildMI(Is64Bit ? X86::LEA64r : X86::LEA32r,
1031 5, FramePtr), StackPtr, NumBytes-SlotSize);
1033 MBB.insert(MBBI, MI);
1036 // If it's main() on Cygwin\Mingw32 we should align stack as well
1037 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1038 Subtarget->isTargetCygwin()) {
1039 MI = BuildMI(X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align);
1040 MBB.insert(MBBI, MI);
1043 MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(Align);
1044 MBB.insert(MBBI, MI);
1045 MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
1046 MBB.insert(MBBI, MI);
1050 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1051 MachineBasicBlock &MBB) const {
1052 const MachineFrameInfo *MFI = MF.getFrameInfo();
1053 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1055 switch (MBBI->getOpcode()) {
1060 case X86::TAILJMPm: break; // These are ok
1062 assert(0 && "Can only insert epilog into returning blocks");
1066 // Get the offset of the stack slot for the EBP register... which is
1067 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1068 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+SlotSize;
1071 BuildMI(MBB, MBBI, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 1, StackPtr).
1075 BuildMI(MBB, MBBI, Is64Bit ? X86::POP64r : X86::POP32r, 0, FramePtr);
1077 // Get the number of bytes allocated from the FrameInfo...
1078 unsigned NumBytes = MFI->getStackSize();
1080 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
1081 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1082 // instruction, merge the two instructions.
1083 if (MBBI != MBB.begin()) {
1084 MachineBasicBlock::iterator PI = prior(MBBI);
1085 unsigned Opc = PI->getOpcode();
1086 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1087 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1088 PI->getOperand(0).getReg() == StackPtr) {
1089 NumBytes += PI->getOperand(2).getImmedValue();
1091 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1092 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1093 PI->getOperand(0).getReg() == StackPtr) {
1094 NumBytes -= PI->getOperand(2).getImmedValue();
1100 unsigned Opc = (NumBytes < 128) ?
1101 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1102 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1103 BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(NumBytes);
1104 } else if ((int)NumBytes < 0) {
1105 unsigned Opc = (-NumBytes < 128) ?
1106 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1107 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1108 BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(-NumBytes);
1114 unsigned X86RegisterInfo::getRARegister() const {
1115 return X86::ST0; // use a non-register register
1118 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1119 return hasFP(MF) ? FramePtr : StackPtr;
1123 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
1125 default: return Reg;
1130 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1132 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1134 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1136 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1142 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1144 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1146 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1148 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1150 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1152 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1154 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1156 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1158 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1160 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1162 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1164 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1166 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1168 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1170 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1172 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1178 default: return Reg;
1179 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1181 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1183 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1185 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1187 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1189 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1191 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1193 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1195 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1197 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1199 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1201 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1203 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1205 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1207 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1209 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1214 default: return Reg;
1215 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1217 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1219 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1221 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1223 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1225 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1227 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1229 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1231 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1233 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1235 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1237 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1239 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1241 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1243 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1245 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1250 default: return Reg;
1251 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1253 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1255 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1257 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1259 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1261 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1263 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1265 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1267 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1269 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1271 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1273 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1275 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1277 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1279 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1281 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1290 #include "X86GenRegisterInfo.inc"