1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/Support/Compiler.h"
42 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
43 const TargetInstrInfo &tii)
44 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
46 // Cache some information.
47 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
48 Is64Bit = Subtarget->is64Bit();
49 IsWin64 = Subtarget->isTargetWin64();
50 StackAlign = TM.getFrameInfo()->getStackAlignment();
62 // getDwarfRegNum - This function maps LLVM register identifiers to the
63 // Dwarf specific numbering, used in debug info and exception tables.
65 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
66 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
67 unsigned Flavour = DWARFFlavour::X86_64;
68 if (!Subtarget->is64Bit()) {
69 if (Subtarget->isTargetDarwin()) {
71 Flavour = DWARFFlavour::X86_32_DarwinEH;
73 Flavour = DWARFFlavour::X86_32_Generic;
74 } else if (Subtarget->isTargetCygMing()) {
75 // Unsupported by now, just quick fallback
76 Flavour = DWARFFlavour::X86_32_Generic;
78 Flavour = DWARFFlavour::X86_32_Generic;
82 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
85 // getX86RegNum - This function maps LLVM register identifiers to their X86
86 // specific numbering, which is used in various places encoding instructions.
88 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
90 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
91 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
92 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
93 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
94 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
96 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
98 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
100 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
103 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
105 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
107 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
109 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
111 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
113 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
115 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
117 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
120 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
121 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
122 return RegNo-X86::ST0;
124 case X86::XMM0: case X86::XMM8: case X86::MM0:
126 case X86::XMM1: case X86::XMM9: case X86::MM1:
128 case X86::XMM2: case X86::XMM10: case X86::MM2:
130 case X86::XMM3: case X86::XMM11: case X86::MM3:
132 case X86::XMM4: case X86::XMM12: case X86::MM4:
134 case X86::XMM5: case X86::XMM13: case X86::MM5:
136 case X86::XMM6: case X86::XMM14: case X86::MM6:
138 case X86::XMM7: case X86::XMM15: case X86::MM7:
142 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
143 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
148 const TargetRegisterClass *
149 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
150 if (RC == &X86::CCRRegClass) {
152 return &X86::GR64RegClass;
154 return &X86::GR32RegClass;
160 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
161 static const unsigned CalleeSavedRegs32Bit[] = {
162 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
165 static const unsigned CalleeSavedRegs32EHRet[] = {
166 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
169 static const unsigned CalleeSavedRegs64Bit[] = {
170 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
173 static const unsigned CalleeSavedRegsWin64[] = {
174 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
175 X86::R12, X86::R13, X86::R14, X86::R15, 0
180 return CalleeSavedRegsWin64;
182 return CalleeSavedRegs64Bit;
185 MachineFrameInfo *MFI = MF->getFrameInfo();
186 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
187 if (MMI && MMI->callsEHReturn())
188 return CalleeSavedRegs32EHRet;
190 return CalleeSavedRegs32Bit;
194 const TargetRegisterClass* const*
195 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
196 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
197 &X86::GR32RegClass, &X86::GR32RegClass,
198 &X86::GR32RegClass, &X86::GR32RegClass, 0
200 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
201 &X86::GR32RegClass, &X86::GR32RegClass,
202 &X86::GR32RegClass, &X86::GR32RegClass,
203 &X86::GR32RegClass, &X86::GR32RegClass, 0
205 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
206 &X86::GR64RegClass, &X86::GR64RegClass,
207 &X86::GR64RegClass, &X86::GR64RegClass,
208 &X86::GR64RegClass, &X86::GR64RegClass, 0
210 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
211 &X86::GR64RegClass, &X86::GR64RegClass,
212 &X86::GR64RegClass, &X86::GR64RegClass,
213 &X86::GR64RegClass, &X86::GR64RegClass,
214 &X86::GR64RegClass, &X86::GR64RegClass, 0
219 return CalleeSavedRegClassesWin64;
221 return CalleeSavedRegClasses64Bit;
224 MachineFrameInfo *MFI = MF->getFrameInfo();
225 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
226 if (MMI && MMI->callsEHReturn())
227 return CalleeSavedRegClasses32EHRet;
229 return CalleeSavedRegClasses32Bit;
234 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
235 BitVector Reserved(getNumRegs());
236 Reserved.set(X86::RSP);
237 Reserved.set(X86::ESP);
238 Reserved.set(X86::SP);
239 Reserved.set(X86::SPL);
241 Reserved.set(X86::RBP);
242 Reserved.set(X86::EBP);
243 Reserved.set(X86::BP);
244 Reserved.set(X86::BPL);
249 //===----------------------------------------------------------------------===//
250 // Stack Frame Processing methods
251 //===----------------------------------------------------------------------===//
253 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
254 unsigned MaxAlign = 0;
255 for (int i = FFI->getObjectIndexBegin(),
256 e = FFI->getObjectIndexEnd(); i != e; ++i) {
257 if (FFI->isDeadObjectIndex(i))
259 unsigned Align = FFI->getObjectAlignment(i);
260 MaxAlign = std::max(MaxAlign, Align);
266 // hasFP - Return true if the specified function should have a dedicated frame
267 // pointer register. This is true if the function has variable sized allocas or
268 // if frame pointer elimination is disabled.
270 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
271 MachineFrameInfo *MFI = MF.getFrameInfo();
272 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
274 return (NoFramePointerElim ||
275 needsStackRealignment(MF) ||
276 MFI->hasVarSizedObjects() ||
277 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
278 (MMI && MMI->callsUnwindInit()));
281 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
282 MachineFrameInfo *MFI = MF.getFrameInfo();;
284 // FIXME: Currently we don't support stack realignment for functions with
285 // variable-sized allocas
286 return (MFI->getMaxAlignment() &&
287 (MFI->getMaxAlignment() > StackAlign &&
288 !MFI->hasVarSizedObjects()));
291 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
292 return !MF.getFrameInfo()->hasVarSizedObjects();
296 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
297 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
298 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
300 if (needsStackRealignment(MF)) {
302 // Skip the saved EBP
305 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment();
307 (StackSize - SlotSize + MaxAlign - 1)/MaxAlign*MaxAlign;
309 return Offset + FrameSize - SlotSize;
312 // FIXME: Support tail calls
315 return Offset + StackSize;
317 // Skip the saved EBP
320 // Skip the RETADDR move area
321 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
322 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
323 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
329 void X86RegisterInfo::
330 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
331 MachineBasicBlock::iterator I) const {
332 if (!hasReservedCallFrame(MF)) {
333 // If the stack pointer can be changed after prologue, turn the
334 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
335 // adjcallstackdown instruction into 'add ESP, <amt>'
336 // TODO: consider using push / pop instead of sub + store / add
337 MachineInstr *Old = I;
338 uint64_t Amount = Old->getOperand(0).getImm();
340 // We need to keep the stack aligned properly. To do this, we round the
341 // amount of space needed for the outgoing arguments up to the next
342 // alignment boundary.
343 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
345 MachineInstr *New = 0;
346 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
347 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
348 .addReg(StackPtr).addImm(Amount);
350 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
351 // factor out the amount the callee already popped.
352 uint64_t CalleeAmt = Old->getOperand(1).getImm();
355 unsigned Opc = (Amount < 128) ?
356 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
357 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
358 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
362 // Replace the pseudo instruction with a new instruction...
363 if (New) MBB.insert(I, New);
365 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
366 // If we are performing frame pointer elimination and if the callee pops
367 // something off the stack pointer, add it back. We do this until we have
368 // more advanced stack pointer tracking ability.
369 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
370 unsigned Opc = (CalleeAmt < 128) ?
371 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
372 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
374 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
382 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
383 int SPAdj, RegScavenger *RS) const{
384 assert(SPAdj == 0 && "Unexpected");
387 MachineInstr &MI = *II;
388 MachineFunction &MF = *MI.getParent()->getParent();
389 while (!MI.getOperand(i).isFrameIndex()) {
391 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
394 int FrameIndex = MI.getOperand(i).getIndex();
397 if (needsStackRealignment(MF))
398 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
400 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
402 // This must be part of a four operand memory reference. Replace the
403 // FrameIndex with base register with EBP. Add an offset to the offset.
404 MI.getOperand(i).ChangeToRegister(BasePtr, false);
406 // Now add the frame object offset to the offset from EBP.
407 int64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
408 MI.getOperand(i+3).getImm();
410 MI.getOperand(i+3).ChangeToImmediate(Offset);
414 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
415 RegScavenger *RS) const {
416 MachineFrameInfo *FFI = MF.getFrameInfo();
418 // Calculate and set max stack object alignment early, so we can decide
419 // whether we will need stack realignment (and thus FP).
420 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
421 calculateMaxStackAlignment(FFI));
423 FFI->setMaxAlignment(MaxAlign);
427 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
428 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
429 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
430 if (TailCallReturnAddrDelta < 0) {
431 // create RETURNADDR area
441 CreateFixedObject(-TailCallReturnAddrDelta,
442 (-1*SlotSize)+TailCallReturnAddrDelta);
445 assert((TailCallReturnAddrDelta <= 0) &&
446 "The Delta should always be zero or negative");
447 // Create a frame entry for the EBP register that must be saved.
448 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
450 TailCallReturnAddrDelta);
451 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
452 "Slot for EBP register must be last in order to be found!");
456 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
457 /// stack pointer by a constant value.
459 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
460 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
461 const TargetInstrInfo &TII) {
462 bool isSub = NumBytes < 0;
463 uint64_t Offset = isSub ? -NumBytes : NumBytes;
466 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
467 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
469 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
470 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
471 uint64_t Chunk = (1LL << 31) - 1;
474 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
475 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
480 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
482 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
483 unsigned StackPtr, uint64_t *NumBytes = NULL) {
484 if (MBBI == MBB.begin()) return;
486 MachineBasicBlock::iterator PI = prior(MBBI);
487 unsigned Opc = PI->getOpcode();
488 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
489 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
490 PI->getOperand(0).getReg() == StackPtr) {
492 *NumBytes += PI->getOperand(2).getImm();
494 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
495 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
496 PI->getOperand(0).getReg() == StackPtr) {
498 *NumBytes -= PI->getOperand(2).getImm();
503 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
505 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
506 MachineBasicBlock::iterator &MBBI,
507 unsigned StackPtr, uint64_t *NumBytes = NULL) {
510 if (MBBI == MBB.end()) return;
512 MachineBasicBlock::iterator NI = next(MBBI);
513 if (NI == MBB.end()) return;
515 unsigned Opc = NI->getOpcode();
516 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
517 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
518 NI->getOperand(0).getReg() == StackPtr) {
520 *NumBytes -= NI->getOperand(2).getImm();
523 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
524 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
525 NI->getOperand(0).getReg() == StackPtr) {
527 *NumBytes += NI->getOperand(2).getImm();
533 /// mergeSPUpdates - Checks the instruction before/after the passed
534 /// instruction. If it is an ADD/SUB instruction it is deleted
535 /// argument and the stack adjustment is returned as a positive value for ADD
536 /// and a negative for SUB.
537 static int mergeSPUpdates(MachineBasicBlock &MBB,
538 MachineBasicBlock::iterator &MBBI,
540 bool doMergeWithPrevious) {
542 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
543 (!doMergeWithPrevious && MBBI == MBB.end()))
548 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
549 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
550 unsigned Opc = PI->getOpcode();
551 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
552 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
553 PI->getOperand(0).getReg() == StackPtr){
554 Offset += PI->getOperand(2).getImm();
556 if (!doMergeWithPrevious) MBBI = NI;
557 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
558 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
559 PI->getOperand(0).getReg() == StackPtr) {
560 Offset -= PI->getOperand(2).getImm();
562 if (!doMergeWithPrevious) MBBI = NI;
568 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
569 unsigned FrameLabelId,
570 unsigned ReadyLabelId) const {
571 MachineFrameInfo *MFI = MF.getFrameInfo();
572 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
576 uint64_t StackSize = MFI->getStackSize();
577 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
578 const TargetData *TD = MF.getTarget().getTargetData();
580 // Calculate amount of bytes used for return address storing
582 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
583 TargetFrameInfo::StackGrowsUp ?
584 TD->getPointerSize() : -TD->getPointerSize());
587 // Show update of SP.
590 MachineLocation SPDst(MachineLocation::VirtualFP);
591 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
592 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
594 MachineLocation SPDst(MachineLocation::VirtualFP);
595 MachineLocation SPSrc(MachineLocation::VirtualFP,
596 -StackSize+stackGrowth);
597 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
600 //FIXME: Verify & implement for FP
601 MachineLocation SPDst(StackPtr);
602 MachineLocation SPSrc(StackPtr, stackGrowth);
603 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
606 // Add callee saved registers to move list.
607 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
609 // FIXME: This is dirty hack. The code itself is pretty mess right now.
610 // It should be rewritten from scratch and generalized sometimes.
612 // Determine maximum offset (minumum due to stack growth)
613 int64_t MaxOffset = 0;
614 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
615 MaxOffset = std::min(MaxOffset,
616 MFI->getObjectOffset(CSI[I].getFrameIdx()));
619 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
620 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
621 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
622 unsigned Reg = CSI[I].getReg();
623 Offset = (MaxOffset-Offset+saveAreaOffset);
624 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
625 MachineLocation CSSrc(Reg);
626 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
631 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
632 MachineLocation FPSrc(FramePtr);
633 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
636 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
637 MachineLocation FPSrc(MachineLocation::VirtualFP);
638 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
642 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
643 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
644 MachineFrameInfo *MFI = MF.getFrameInfo();
645 const Function* Fn = MF.getFunction();
646 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
647 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
648 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
649 MachineBasicBlock::iterator MBBI = MBB.begin();
650 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
651 !Fn->doesNotThrow() ||
652 UnwindTablesMandatory;
653 // Prepare for frame info.
654 unsigned FrameLabelId = 0;
656 // Get the number of bytes to allocate from the FrameInfo.
657 uint64_t StackSize = MFI->getStackSize();
658 // Get desired stack alignment
659 uint64_t MaxAlign = MFI->getMaxAlignment();
661 // Add RETADDR move area to callee saved frame size.
662 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
663 if (TailCallReturnAddrDelta < 0)
664 X86FI->setCalleeSavedFrameSize(
665 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
667 // Insert stack pointer adjustment for later moving of return addr. Only
668 // applies to tail call optimized functions where the callee argument stack
669 // size is bigger than the callers.
670 if (TailCallReturnAddrDelta < 0) {
671 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
672 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
675 uint64_t NumBytes = 0;
677 // Calculate required stack adjustment
678 uint64_t FrameSize = StackSize - SlotSize;
679 if (needsStackRealignment(MF))
680 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
682 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
684 // Get the offset of the stack slot for the EBP register... which is
685 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
686 // Update the frame offset adjustment.
687 MFI->setOffsetAdjustment(-NumBytes);
689 // Save EBP into the appropriate stack slot...
690 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
693 if (needsFrameMoves) {
694 // Mark effective beginning of when frame pointer becomes valid.
695 FrameLabelId = MMI->NextLabelID();
696 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
699 // Update EBP with the new base value...
700 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
704 if (needsStackRealignment(MF))
706 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
707 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
709 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
711 unsigned ReadyLabelId = 0;
712 if (needsFrameMoves) {
713 // Mark effective beginning of when frame pointer is ready.
714 ReadyLabelId = MMI->NextLabelID();
715 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
718 // Skip the callee-saved push instructions.
719 while (MBBI != MBB.end() &&
720 (MBBI->getOpcode() == X86::PUSH32r ||
721 MBBI->getOpcode() == X86::PUSH64r))
724 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
725 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
726 // Check, whether EAX is livein for this function
727 bool isEAXAlive = false;
728 for (MachineRegisterInfo::livein_iterator
729 II = MF.getRegInfo().livein_begin(),
730 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
731 unsigned Reg = II->first;
732 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
733 Reg == X86::AH || Reg == X86::AL);
736 // Function prologue calls _alloca to probe the stack when allocating
737 // more than 4k bytes in one go. Touching the stack at 4K increments is
738 // necessary to ensure that the guard pages used by the OS virtual memory
739 // manager are allocated in correct sequence.
741 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
742 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
743 .addExternalSymbol("_alloca");
746 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
747 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
748 // allocated bytes for EAX.
749 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
750 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
751 .addExternalSymbol("_alloca");
753 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
754 StackPtr, NumBytes-4);
755 MBB.insert(MBBI, MI);
758 // If there is an SUB32ri of ESP immediately before this instruction,
759 // merge the two. This can be the case when tail call elimination is
760 // enabled and the callee has more arguments then the caller.
761 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
762 // If there is an ADD32ri or SUB32ri of ESP immediately after this
763 // instruction, merge the two instructions.
764 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
767 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
772 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
775 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
776 MachineBasicBlock &MBB) const {
777 const MachineFrameInfo *MFI = MF.getFrameInfo();
778 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
779 MachineBasicBlock::iterator MBBI = prior(MBB.end());
780 unsigned RetOpcode = MBBI->getOpcode();
785 case X86::TCRETURNdi:
786 case X86::TCRETURNri:
787 case X86::TCRETURNri64:
788 case X86::TCRETURNdi64:
792 case X86::TAILJMPm: break; // These are ok
794 assert(0 && "Can only insert epilog into returning blocks");
797 // Get the number of bytes to allocate from the FrameInfo
798 uint64_t StackSize = MFI->getStackSize();
799 uint64_t MaxAlign = MFI->getMaxAlignment();
800 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
801 uint64_t NumBytes = 0;
804 // Calculate required stack adjustment
805 uint64_t FrameSize = StackSize - SlotSize;
806 if (needsStackRealignment(MF))
807 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
809 NumBytes = FrameSize - CSSize;
812 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
814 NumBytes = StackSize - CSSize;
816 // Skip the callee-saved pop instructions.
817 MachineBasicBlock::iterator LastCSPop = MBBI;
818 while (MBBI != MBB.begin()) {
819 MachineBasicBlock::iterator PI = prior(MBBI);
820 unsigned Opc = PI->getOpcode();
821 if (Opc != X86::POP32r && Opc != X86::POP64r &&
822 !PI->getDesc().isTerminator())
827 // If there is an ADD32ri or SUB32ri of ESP immediately before this
828 // instruction, merge the two instructions.
829 if (NumBytes || MFI->hasVarSizedObjects())
830 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
832 // If dynamic alloca is used, then reset esp to point to the last callee-saved
833 // slot before popping them off! Same applies for the case, when stack was
835 if (needsStackRealignment(MF)) {
836 // We cannot use LEA here, because stack pointer was realigned. We need to
837 // deallocate local frame back
839 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
840 MBBI = prior(LastCSPop);
844 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
845 StackPtr).addReg(FramePtr);
846 } else if (MFI->hasVarSizedObjects()) {
848 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
849 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
851 MBB.insert(MBBI, MI);
853 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
857 // adjust stack pointer back: ESP += numbytes
859 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
862 // We're returning from function via eh_return.
863 if (RetOpcode == X86::EH_RETURN) {
864 MBBI = prior(MBB.end());
865 MachineOperand &DestAddr = MBBI->getOperand(0);
866 assert(DestAddr.isRegister() && "Offset should be in register!");
867 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
868 addReg(DestAddr.getReg());
869 // Tail call return: adjust the stack pointer and jump to callee
870 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
871 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
872 MBBI = prior(MBB.end());
873 MachineOperand &JumpTarget = MBBI->getOperand(0);
874 MachineOperand &StackAdjust = MBBI->getOperand(1);
875 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
877 // Adjust stack pointer.
878 int StackAdj = StackAdjust.getImm();
879 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
881 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
882 // Incoporate the retaddr area.
883 Offset = StackAdj-MaxTCDelta;
884 assert(Offset >= 0 && "Offset should never be negative");
886 // Check for possible merge with preceeding ADD instruction.
887 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
888 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
890 // Jump to label or value in register.
891 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
892 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
893 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
894 else if (RetOpcode== X86::TCRETURNri64) {
895 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
897 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
898 // Delete the pseudo instruction TCRETURN.
900 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
901 (X86FI->getTCReturnAddrDelta() < 0)) {
902 // Add the return addr area delta back since we are not tail calling.
903 int delta = -1*X86FI->getTCReturnAddrDelta();
904 MBBI = prior(MBB.end());
905 // Check for possible merge with preceeding ADD instruction.
906 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
907 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
911 unsigned X86RegisterInfo::getRARegister() const {
913 return X86::RIP; // Should have dwarf #16
915 return X86::EIP; // Should have dwarf #8
918 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
919 return hasFP(MF) ? FramePtr : StackPtr;
922 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
924 // Calculate amount of bytes used for return address storing
925 int stackGrowth = (Is64Bit ? -8 : -4);
927 // Initial state of the frame pointer is esp+4.
928 MachineLocation Dst(MachineLocation::VirtualFP);
929 MachineLocation Src(StackPtr, stackGrowth);
930 Moves.push_back(MachineMove(0, Dst, Src));
932 // Add return address to move list
933 MachineLocation CSDst(StackPtr, stackGrowth);
934 MachineLocation CSSrc(getRARegister());
935 Moves.push_back(MachineMove(0, CSDst, CSSrc));
938 unsigned X86RegisterInfo::getEHExceptionRegister() const {
939 assert(0 && "What is the exception register");
943 unsigned X86RegisterInfo::getEHHandlerRegister() const {
944 assert(0 && "What is the exception handler register");
949 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
956 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
958 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
960 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
962 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
968 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
970 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
972 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
974 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
976 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
978 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
980 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
982 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
984 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
986 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
988 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
990 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
992 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
994 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
996 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
998 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1004 default: return Reg;
1005 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1007 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1009 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1011 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1013 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1015 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1017 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1019 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1021 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1023 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1025 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1027 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1029 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1031 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1033 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1035 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1040 default: return Reg;
1041 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1043 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1045 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1047 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1049 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1051 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1053 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1055 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1057 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1059 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1061 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1063 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1065 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1067 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1069 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1071 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1076 default: return Reg;
1077 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1079 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1081 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1083 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1085 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1087 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1089 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1091 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1093 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1095 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1097 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1099 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1101 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1103 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1105 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1107 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1116 #include "X86GenRegisterInfo.inc"
1119 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1121 MSAC() : MachineFunctionPass((intptr_t)&ID) {}
1123 virtual bool runOnMachineFunction(MachineFunction &MF) {
1124 MachineFrameInfo *FFI = MF.getFrameInfo();
1125 MachineRegisterInfo &RI = MF.getRegInfo();
1127 // Calculate max stack alignment of all already allocated stack objects.
1128 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1130 // Be over-conservative: scan over all vreg defs and find, whether vector
1131 // registers are used. If yes - there is probability, that vector register
1132 // will be spilled and thus stack needs to be aligned properly.
1133 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1134 RegNum < RI.getLastVirtReg(); ++RegNum)
1135 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1137 FFI->setMaxAlignment(MaxAlign);
1142 virtual const char *getPassName() const {
1143 return "X86 Maximal Stack Alignment Calculator";
1151 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }