1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/MachineValueType.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
47 ForceStackAlign("force-align-stack",
48 cl::desc("Force align the stack to the minimum alignment"
49 " needed for the function."),
50 cl::init(false), cl::Hidden);
53 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
56 X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI)
58 (STI.is64Bit() ? X86::RIP : X86::EIP),
59 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false),
60 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true),
61 (STI.is64Bit() ? X86::RIP : X86::EIP)),
63 X86_MC::InitLLVM2SEHRegisterMapping(this);
65 // Cache some information.
66 Is64Bit = Subtarget.is64Bit();
67 IsWin64 = Subtarget.isTargetWin64();
71 StackPtr = (Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64()) ?
73 FramePtr = (Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64()) ?
80 // Use a callee-saved register as the base pointer. These registers must
81 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
82 // requires GOT in the EBX register before function calls via PLT GOT pointer.
83 BasePtr = Is64Bit ? X86::RBX : X86::ESI;
87 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
88 // ExeDepsFixer and PostRAScheduler require liveness.
93 X86RegisterInfo::getSEHRegNum(unsigned i) const {
94 return getEncodingValue(i);
97 const TargetRegisterClass *
98 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
100 // The sub_8bit sub-register index is more constrained in 32-bit mode.
101 // It behaves just like the sub_8bit_hi index.
102 if (!Is64Bit && Idx == X86::sub_8bit)
103 Idx = X86::sub_8bit_hi;
105 // Forward to TableGen's default version.
106 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
109 const TargetRegisterClass *
110 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
111 const TargetRegisterClass *B,
112 unsigned SubIdx) const {
113 // The sub_8bit sub-register index is more constrained in 32-bit mode.
114 if (!Is64Bit && SubIdx == X86::sub_8bit) {
115 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
119 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
122 const TargetRegisterClass*
123 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
124 // Don't allow super-classes of GR8_NOREX. This class is only used after
125 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
126 // to the full GR8 register class in 64-bit mode, so we cannot allow the
127 // reigster class inflation.
129 // The GR8_NOREX class is always used in a way that won't be constrained to a
130 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
132 if (RC == &X86::GR8_NOREXRegClass)
135 const TargetRegisterClass *Super = RC;
136 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
138 switch (Super->getID()) {
139 case X86::GR8RegClassID:
140 case X86::GR16RegClassID:
141 case X86::GR32RegClassID:
142 case X86::GR64RegClassID:
143 case X86::FR32RegClassID:
144 case X86::FR64RegClassID:
145 case X86::RFP32RegClassID:
146 case X86::RFP64RegClassID:
147 case X86::RFP80RegClassID:
148 case X86::VR128RegClassID:
149 case X86::VR256RegClassID:
150 // Don't return a super-class that would shrink the spill size.
151 // That can happen with the vector and float classes.
152 if (Super->getSize() == RC->getSize())
160 const TargetRegisterClass *
161 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
162 unsigned Kind) const {
164 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
165 case 0: // Normal GPRs.
166 if (Subtarget.isTarget64BitLP64())
167 return &X86::GR64RegClass;
168 return &X86::GR32RegClass;
169 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
170 if (Subtarget.isTarget64BitLP64())
171 return &X86::GR64_NOSPRegClass;
172 return &X86::GR32_NOSPRegClass;
173 case 2: // Available for tailcall (not callee-saved GPRs).
174 if (Subtarget.isTargetWin64())
175 return &X86::GR64_TCW64RegClass;
176 else if (Subtarget.is64Bit())
177 return &X86::GR64_TCRegClass;
179 const Function *F = MF.getFunction();
180 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
182 return &X86::GR32RegClass;
183 return &X86::GR32_TCRegClass;
187 const TargetRegisterClass *
188 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
189 if (RC == &X86::CCRRegClass) {
191 return &X86::GR64RegClass;
193 return &X86::GR32RegClass;
199 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
200 MachineFunction &MF) const {
201 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
203 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
204 switch (RC->getID()) {
207 case X86::GR32RegClassID:
209 case X86::GR64RegClassID:
211 case X86::VR128RegClassID:
212 return Subtarget.is64Bit() ? 10 : 4;
213 case X86::VR64RegClassID:
219 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
220 bool HasAVX = Subtarget.hasAVX();
221 bool HasAVX512 = Subtarget.hasAVX512();
223 assert(MF && "MachineFunction required");
224 switch (MF->getFunction()->getCallingConv()) {
225 case CallingConv::GHC:
226 case CallingConv::HiPE:
227 return CSR_NoRegs_SaveList;
228 case CallingConv::AnyReg:
230 return CSR_64_AllRegs_AVX_SaveList;
231 return CSR_64_AllRegs_SaveList;
232 case CallingConv::PreserveMost:
233 return CSR_64_RT_MostRegs_SaveList;
234 case CallingConv::PreserveAll:
236 return CSR_64_RT_AllRegs_AVX_SaveList;
237 return CSR_64_RT_AllRegs_SaveList;
238 case CallingConv::Intel_OCL_BI: {
239 if (HasAVX512 && IsWin64)
240 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
241 if (HasAVX512 && Is64Bit)
242 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
243 if (HasAVX && IsWin64)
244 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
245 if (HasAVX && Is64Bit)
246 return CSR_64_Intel_OCL_BI_AVX_SaveList;
247 if (!HasAVX && !IsWin64 && Is64Bit)
248 return CSR_64_Intel_OCL_BI_SaveList;
251 case CallingConv::Cold:
253 return CSR_64_MostRegs_SaveList;
259 bool CallsEHReturn = MF->getMMI().callsEHReturn();
262 return CSR_Win64_SaveList;
264 return CSR_64EHRet_SaveList;
265 return CSR_64_SaveList;
268 return CSR_32EHRet_SaveList;
269 return CSR_32_SaveList;
273 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
274 bool HasAVX = Subtarget.hasAVX();
275 bool HasAVX512 = Subtarget.hasAVX512();
278 case CallingConv::GHC:
279 case CallingConv::HiPE:
280 return CSR_NoRegs_RegMask;
281 case CallingConv::AnyReg:
283 return CSR_64_AllRegs_AVX_RegMask;
284 return CSR_64_AllRegs_RegMask;
285 case CallingConv::PreserveMost:
286 return CSR_64_RT_MostRegs_RegMask;
287 case CallingConv::PreserveAll:
289 return CSR_64_RT_AllRegs_AVX_RegMask;
290 return CSR_64_RT_AllRegs_RegMask;
291 case CallingConv::Intel_OCL_BI: {
292 if (HasAVX512 && IsWin64)
293 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
294 if (HasAVX512 && Is64Bit)
295 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
296 if (HasAVX && IsWin64)
297 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
298 if (HasAVX && Is64Bit)
299 return CSR_64_Intel_OCL_BI_AVX_RegMask;
300 if (!HasAVX && !IsWin64 && Is64Bit)
301 return CSR_64_Intel_OCL_BI_RegMask;
304 case CallingConv::Cold:
306 return CSR_64_MostRegs_RegMask;
312 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
316 return CSR_Win64_RegMask;
317 return CSR_64_RegMask;
319 return CSR_32_RegMask;
323 X86RegisterInfo::getNoPreservedMask() const {
324 return CSR_NoRegs_RegMask;
327 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
328 BitVector Reserved(getNumRegs());
329 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
331 // Set the stack-pointer register and its aliases as reserved.
332 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
336 // Set the instruction pointer register and its aliases as reserved.
337 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
341 // Set the frame-pointer register and its aliases as reserved if needed.
342 if (TFI->hasFP(MF)) {
343 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
348 // Set the base-pointer register and its aliases as reserved if needed.
349 if (hasBasePointer(MF)) {
350 CallingConv::ID CC = MF.getFunction()->getCallingConv();
351 const uint32_t* RegMask = getCallPreservedMask(CC);
352 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
354 "Stack realignment in presence of dynamic allocas is not supported with"
355 "this calling convention.");
357 for (MCSubRegIterator I(getBaseRegister(), this, /*IncludeSelf=*/true);
362 // Mark the segment registers as reserved.
363 Reserved.set(X86::CS);
364 Reserved.set(X86::SS);
365 Reserved.set(X86::DS);
366 Reserved.set(X86::ES);
367 Reserved.set(X86::FS);
368 Reserved.set(X86::GS);
370 // Mark the floating point stack registers as reserved.
371 for (unsigned n = 0; n != 8; ++n)
372 Reserved.set(X86::ST0 + n);
374 // Reserve the registers that only exist in 64-bit mode.
376 // These 8-bit registers are part of the x86-64 extension even though their
377 // super-registers are old 32-bits.
378 Reserved.set(X86::SIL);
379 Reserved.set(X86::DIL);
380 Reserved.set(X86::BPL);
381 Reserved.set(X86::SPL);
383 for (unsigned n = 0; n != 8; ++n) {
385 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
389 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
393 if (!Is64Bit || !Subtarget.hasAVX512()) {
394 for (unsigned n = 16; n != 32; ++n) {
395 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
403 //===----------------------------------------------------------------------===//
404 // Stack Frame Processing methods
405 //===----------------------------------------------------------------------===//
407 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
408 const MachineFrameInfo *MFI = MF.getFrameInfo();
410 if (!EnableBasePointer)
413 // When we need stack realignment, we can't address the stack from the frame
414 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
415 // can't address variables from the stack pointer. MS inline asm can
416 // reference locals while also adjusting the stack pointer. When we can't
417 // use both the SP and the FP, we need a separate base pointer register.
418 bool CantUseFP = needsStackRealignment(MF);
420 MFI->hasVarSizedObjects() || MFI->hasInlineAsmWithSPAdjust();
421 return CantUseFP && CantUseSP;
424 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
425 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
428 const MachineFrameInfo *MFI = MF.getFrameInfo();
429 const MachineRegisterInfo *MRI = &MF.getRegInfo();
431 // Stack realignment requires a frame pointer. If we already started
432 // register allocation with frame pointer elimination, it is too late now.
433 if (!MRI->canReserveReg(FramePtr))
436 // If a base pointer is necessary. Check that it isn't too late to reserve
438 if (MFI->hasVarSizedObjects())
439 return MRI->canReserveReg(BasePtr);
443 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
444 const MachineFrameInfo *MFI = MF.getFrameInfo();
445 const Function *F = MF.getFunction();
446 unsigned StackAlign = MF.getTarget()
449 ->getStackAlignment();
450 bool requiresRealignment =
451 ((MFI->getMaxAlignment() > StackAlign) ||
452 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
453 Attribute::StackAlignment));
455 // If we've requested that we force align the stack do so now.
457 return canRealignStack(MF);
459 return requiresRealignment && canRealignStack(MF);
462 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
463 unsigned Reg, int &FrameIdx) const {
464 // Since X86 defines assignCalleeSavedSpillSlots which always return true
465 // this function neither used nor tested.
466 llvm_unreachable("Unused function on X86. Otherwise need a test case.");
470 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
471 int SPAdj, unsigned FIOperandNum,
472 RegScavenger *RS) const {
473 assert(SPAdj == 0 && "Unexpected");
475 MachineInstr &MI = *II;
476 MachineFunction &MF = *MI.getParent()->getParent();
477 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
478 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
481 unsigned Opc = MI.getOpcode();
482 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
483 if (hasBasePointer(MF))
484 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
485 else if (needsStackRealignment(MF))
486 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
490 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
492 // This must be part of a four operand memory reference. Replace the
493 // FrameIndex with base register with EBP. Add an offset to the offset.
494 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
496 // Now add the frame object offset to the offset from EBP.
499 // Tail call jmp happens after FP is popped.
500 const MachineFrameInfo *MFI = MF.getFrameInfo();
501 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
503 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
505 // The frame index format for stackmaps and patchpoints is different from the
506 // X86 format. It only has a FI and an offset.
507 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
508 assert(BasePtr == FramePtr && "Expected the FP as base register");
509 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
510 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
514 if (MI.getOperand(FIOperandNum+3).isImm()) {
515 // Offset is a 32-bit integer.
516 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
517 int Offset = FIOffset + Imm;
518 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
519 "Requesting 64-bit offset in 32-bit immediate!");
520 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
522 // Offset is symbolic. This is extremely rare.
523 uint64_t Offset = FIOffset +
524 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
525 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
529 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
530 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
531 return TFI->hasFP(MF) ? FramePtr : StackPtr;
535 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
538 default: llvm_unreachable("Unexpected VT");
542 default: return getX86SubSuperRegister(Reg, MVT::i64);
543 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
545 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
547 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
549 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
551 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
553 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
555 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
557 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
562 default: llvm_unreachable("Unexpected register");
563 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
565 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
567 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
569 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
571 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
573 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
575 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
577 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
579 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
581 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
583 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
585 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
587 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
589 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
591 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
593 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
599 default: llvm_unreachable("Unexpected register");
600 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
602 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
604 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
606 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
608 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
610 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
612 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
614 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
616 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
618 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
620 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
622 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
624 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
626 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
628 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
630 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
635 default: llvm_unreachable("Unexpected register");
636 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
638 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
640 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
642 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
644 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
646 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
648 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
650 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
652 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
654 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
656 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
658 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
660 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
662 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
664 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
666 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
671 default: llvm_unreachable("Unexpected register");
672 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
674 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
676 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
678 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
680 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
682 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
684 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
686 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
688 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
690 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
692 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
694 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
696 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
698 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
700 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
702 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
708 unsigned get512BitSuperRegister(unsigned Reg) {
709 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
710 return X86::ZMM0 + (Reg - X86::XMM0);
711 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
712 return X86::ZMM0 + (Reg - X86::YMM0);
713 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
715 llvm_unreachable("Unexpected SIMD register");