1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
70 /// specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
75 if (!Subtarget->is64Bit()) {
76 if (Subtarget->isTargetDarwin()) {
78 Flavour = DWARFFlavour::X86_32_DarwinEH;
80 Flavour = DWARFFlavour::X86_32_Generic;
81 } else if (Subtarget->isTargetCygMing()) {
82 // Unsupported by now, just quick fallback
83 Flavour = DWARFFlavour::X86_32_Generic;
85 Flavour = DWARFFlavour::X86_32_Generic;
89 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
92 /// getX86RegNum - This function maps LLVM register identifiers to their X86
93 /// specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8: case X86::MM0:
132 case X86::XMM1: case X86::XMM9: case X86::MM1:
134 case X86::XMM2: case X86::XMM10: case X86::MM2:
136 case X86::XMM3: case X86::XMM11: case X86::MM3:
138 case X86::XMM4: case X86::XMM12: case X86::MM4:
140 case X86::XMM5: case X86::XMM13: case X86::MM5:
142 case X86::XMM6: case X86::XMM14: case X86::MM6:
144 case X86::XMM7: case X86::XMM15: case X86::MM7:
161 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
162 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
167 const TargetRegisterClass *
168 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
169 const TargetRegisterClass *B,
170 unsigned SubIdx) const {
174 if (B == &X86::GR8RegClass) {
175 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
177 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
178 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
179 A == &X86::GR64_NOREXRegClass ||
180 A == &X86::GR64_NOSPRegClass ||
181 A == &X86::GR64_NOREX_NOSPRegClass)
182 return &X86::GR64_ABCDRegClass;
183 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
184 A == &X86::GR32_NOREXRegClass ||
185 A == &X86::GR32_NOSPRegClass)
186 return &X86::GR32_ABCDRegClass;
187 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
188 A == &X86::GR16_NOREXRegClass)
189 return &X86::GR16_ABCDRegClass;
190 } else if (B == &X86::GR8_NOREXRegClass) {
191 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
192 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
193 return &X86::GR64_NOREXRegClass;
194 else if (A == &X86::GR64_ABCDRegClass)
195 return &X86::GR64_ABCDRegClass;
196 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
197 A == &X86::GR32_NOSPRegClass)
198 return &X86::GR32_NOREXRegClass;
199 else if (A == &X86::GR32_ABCDRegClass)
200 return &X86::GR32_ABCDRegClass;
201 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
202 return &X86::GR16_NOREXRegClass;
203 else if (A == &X86::GR16_ABCDRegClass)
204 return &X86::GR16_ABCDRegClass;
207 case X86::sub_8bit_hi:
208 if (B == &X86::GR8_ABCD_HRegClass) {
209 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
210 A == &X86::GR64_NOREXRegClass ||
211 A == &X86::GR64_NOSPRegClass ||
212 A == &X86::GR64_NOREX_NOSPRegClass)
213 return &X86::GR64_ABCDRegClass;
214 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
215 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
216 return &X86::GR32_ABCDRegClass;
217 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
218 A == &X86::GR16_NOREXRegClass)
219 return &X86::GR16_ABCDRegClass;
223 if (B == &X86::GR16RegClass) {
224 if (A->getSize() == 4 || A->getSize() == 8)
226 } else if (B == &X86::GR16_ABCDRegClass) {
227 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
228 A == &X86::GR64_NOREXRegClass ||
229 A == &X86::GR64_NOSPRegClass ||
230 A == &X86::GR64_NOREX_NOSPRegClass)
231 return &X86::GR64_ABCDRegClass;
232 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
233 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
234 return &X86::GR32_ABCDRegClass;
235 } else if (B == &X86::GR16_NOREXRegClass) {
236 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
237 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
238 return &X86::GR64_NOREXRegClass;
239 else if (A == &X86::GR64_ABCDRegClass)
240 return &X86::GR64_ABCDRegClass;
241 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
242 A == &X86::GR32_NOSPRegClass)
243 return &X86::GR32_NOREXRegClass;
244 else if (A == &X86::GR32_ABCDRegClass)
245 return &X86::GR64_ABCDRegClass;
249 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
250 if (A->getSize() == 8)
252 } else if (B == &X86::GR32_ABCDRegClass) {
253 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
254 A == &X86::GR64_NOREXRegClass ||
255 A == &X86::GR64_NOSPRegClass ||
256 A == &X86::GR64_NOREX_NOSPRegClass)
257 return &X86::GR64_ABCDRegClass;
258 } else if (B == &X86::GR32_NOREXRegClass) {
259 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
260 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
261 return &X86::GR64_NOREXRegClass;
262 else if (A == &X86::GR64_ABCDRegClass)
263 return &X86::GR64_ABCDRegClass;
267 if (B == &X86::FR32RegClass)
271 if (B == &X86::FR64RegClass)
275 if (B == &X86::VR128RegClass)
282 const TargetRegisterClass *
283 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
285 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
286 case 0: // Normal GPRs.
287 if (TM.getSubtarget<X86Subtarget>().is64Bit())
288 return &X86::GR64RegClass;
289 return &X86::GR32RegClass;
290 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
291 if (TM.getSubtarget<X86Subtarget>().is64Bit())
292 return &X86::GR64_NOSPRegClass;
293 return &X86::GR32_NOSPRegClass;
297 const TargetRegisterClass *
298 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
299 if (RC == &X86::CCRRegClass) {
301 return &X86::GR64RegClass;
303 return &X86::GR32RegClass;
309 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
310 bool callsEHReturn = false;
311 bool ghcCall = false;
314 callsEHReturn = MF->getMMI().callsEHReturn();
315 const Function *F = MF->getFunction();
316 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
319 static const unsigned GhcCalleeSavedRegs[] = {
323 static const unsigned CalleeSavedRegs32Bit[] = {
324 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
327 static const unsigned CalleeSavedRegs32EHRet[] = {
328 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
331 static const unsigned CalleeSavedRegs64Bit[] = {
332 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
335 static const unsigned CalleeSavedRegs64EHRet[] = {
336 X86::RAX, X86::RDX, X86::RBX, X86::R12,
337 X86::R13, X86::R14, X86::R15, X86::RBP, 0
340 static const unsigned CalleeSavedRegsWin64[] = {
341 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
342 X86::R12, X86::R13, X86::R14, X86::R15,
343 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
344 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
345 X86::XMM14, X86::XMM15, 0
349 return GhcCalleeSavedRegs;
350 } else if (Is64Bit) {
352 return CalleeSavedRegsWin64;
354 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
356 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
360 const TargetRegisterClass* const*
361 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
362 bool callsEHReturn = false;
364 callsEHReturn = MF->getMMI().callsEHReturn();
366 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
367 &X86::GR32RegClass, &X86::GR32RegClass,
368 &X86::GR32RegClass, &X86::GR32RegClass, 0
370 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
371 &X86::GR32RegClass, &X86::GR32RegClass,
372 &X86::GR32RegClass, &X86::GR32RegClass,
373 &X86::GR32RegClass, &X86::GR32RegClass, 0
375 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
376 &X86::GR64RegClass, &X86::GR64RegClass,
377 &X86::GR64RegClass, &X86::GR64RegClass,
378 &X86::GR64RegClass, &X86::GR64RegClass, 0
380 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
381 &X86::GR64RegClass, &X86::GR64RegClass,
382 &X86::GR64RegClass, &X86::GR64RegClass,
383 &X86::GR64RegClass, &X86::GR64RegClass,
384 &X86::GR64RegClass, &X86::GR64RegClass, 0
386 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
387 &X86::GR64RegClass, &X86::GR64RegClass,
388 &X86::GR64RegClass, &X86::GR64RegClass,
389 &X86::GR64RegClass, &X86::GR64RegClass,
390 &X86::GR64RegClass, &X86::GR64RegClass,
391 &X86::VR128RegClass, &X86::VR128RegClass,
392 &X86::VR128RegClass, &X86::VR128RegClass,
393 &X86::VR128RegClass, &X86::VR128RegClass,
394 &X86::VR128RegClass, &X86::VR128RegClass,
395 &X86::VR128RegClass, &X86::VR128RegClass, 0
400 return CalleeSavedRegClassesWin64;
402 return (callsEHReturn ?
403 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
405 return (callsEHReturn ?
406 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
410 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
411 BitVector Reserved(getNumRegs());
412 // Set the stack-pointer register and its aliases as reserved.
413 Reserved.set(X86::RSP);
414 Reserved.set(X86::ESP);
415 Reserved.set(X86::SP);
416 Reserved.set(X86::SPL);
418 // Set the instruction pointer register and its aliases as reserved.
419 Reserved.set(X86::RIP);
420 Reserved.set(X86::EIP);
421 Reserved.set(X86::IP);
423 // Set the frame-pointer register and its aliases as reserved if needed.
425 Reserved.set(X86::RBP);
426 Reserved.set(X86::EBP);
427 Reserved.set(X86::BP);
428 Reserved.set(X86::BPL);
431 // Mark the x87 stack registers as reserved, since they don't behave normally
432 // with respect to liveness. We don't fully model the effects of x87 stack
433 // pushes and pops after stackification.
434 Reserved.set(X86::ST0);
435 Reserved.set(X86::ST1);
436 Reserved.set(X86::ST2);
437 Reserved.set(X86::ST3);
438 Reserved.set(X86::ST4);
439 Reserved.set(X86::ST5);
440 Reserved.set(X86::ST6);
441 Reserved.set(X86::ST7);
445 //===----------------------------------------------------------------------===//
446 // Stack Frame Processing methods
447 //===----------------------------------------------------------------------===//
449 /// hasFP - Return true if the specified function should have a dedicated frame
450 /// pointer register. This is true if the function has variable sized allocas
451 /// or if frame pointer elimination is disabled.
452 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
453 const MachineFrameInfo *MFI = MF.getFrameInfo();
454 const MachineModuleInfo &MMI = MF.getMMI();
456 return (DisableFramePointerElim(MF) ||
457 needsStackRealignment(MF) ||
458 MFI->hasVarSizedObjects() ||
459 MFI->isFrameAddressTaken() ||
460 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
461 MMI.callsUnwindInit());
464 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
465 const MachineFrameInfo *MFI = MF.getFrameInfo();
466 return (RealignStack &&
467 !MFI->hasVarSizedObjects());
470 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
471 const MachineFrameInfo *MFI = MF.getFrameInfo();
472 const Function *F = MF.getFunction();
473 bool requiresRealignment =
474 RealignStack && ((MFI->getMaxAlignment() > StackAlign) ||
475 F->hasFnAttr(Attribute::StackAlignment));
477 // FIXME: Currently we don't support stack realignment for functions with
478 // variable-sized allocas.
479 // FIXME: Temporary disable the error - it seems to be too conservative.
480 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
482 "Stack realignment in presense of dynamic allocas is not supported");
484 return (requiresRealignment && !MFI->hasVarSizedObjects());
487 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
488 return !MF.getFrameInfo()->hasVarSizedObjects();
491 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
492 int &FrameIdx) const {
493 if (Reg == FramePtr && hasFP(MF)) {
494 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
501 X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
502 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
503 const MachineFrameInfo *MFI = MF.getFrameInfo();
504 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
505 uint64_t StackSize = MFI->getStackSize();
507 if (needsStackRealignment(MF)) {
509 // Skip the saved EBP.
512 unsigned Align = MFI->getObjectAlignment(FI);
513 assert((-(Offset + StackSize)) % Align == 0);
515 return Offset + StackSize;
517 // FIXME: Support tail calls
520 return Offset + StackSize;
522 // Skip the saved EBP.
525 // Skip the RETADDR move area
526 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
527 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
528 if (TailCallReturnAddrDelta < 0)
529 Offset -= TailCallReturnAddrDelta;
535 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
538 return X86::SUB64ri8;
539 return X86::SUB64ri32;
542 return X86::SUB32ri8;
547 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
550 return X86::ADD64ri8;
551 return X86::ADD64ri32;
554 return X86::ADD32ri8;
559 void X86RegisterInfo::
560 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
561 MachineBasicBlock::iterator I) const {
562 if (!hasReservedCallFrame(MF)) {
563 // If the stack pointer can be changed after prologue, turn the
564 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
565 // adjcallstackdown instruction into 'add ESP, <amt>'
566 // TODO: consider using push / pop instead of sub + store / add
567 MachineInstr *Old = I;
568 uint64_t Amount = Old->getOperand(0).getImm();
570 // We need to keep the stack aligned properly. To do this, we round the
571 // amount of space needed for the outgoing arguments up to the next
572 // alignment boundary.
573 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
575 MachineInstr *New = 0;
576 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
577 New = BuildMI(MF, Old->getDebugLoc(),
578 TII.get(getSUBriOpcode(Is64Bit, Amount)),
583 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
585 // Factor out the amount the callee already popped.
586 uint64_t CalleeAmt = Old->getOperand(1).getImm();
590 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
591 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
598 // The EFLAGS implicit def is dead.
599 New->getOperand(3).setIsDead();
601 // Replace the pseudo instruction with a new instruction.
605 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
606 // If we are performing frame pointer elimination and if the callee pops
607 // something off the stack pointer, add it back. We do this until we have
608 // more advanced stack pointer tracking ability.
609 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
610 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
611 MachineInstr *Old = I;
613 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
618 // The EFLAGS implicit def is dead.
619 New->getOperand(3).setIsDead();
628 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
629 int SPAdj, FrameIndexValue *Value,
630 RegScavenger *RS) const{
631 assert(SPAdj == 0 && "Unexpected");
634 MachineInstr &MI = *II;
635 MachineFunction &MF = *MI.getParent()->getParent();
637 while (!MI.getOperand(i).isFI()) {
639 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
642 int FrameIndex = MI.getOperand(i).getIndex();
645 unsigned Opc = MI.getOpcode();
646 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
647 if (needsStackRealignment(MF))
648 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
652 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
654 // This must be part of a four operand memory reference. Replace the
655 // FrameIndex with base register with EBP. Add an offset to the offset.
656 MI.getOperand(i).ChangeToRegister(BasePtr, false);
658 // Now add the frame object offset to the offset from EBP.
661 // Tail call jmp happens after FP is popped.
662 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
663 const MachineFrameInfo *MFI = MF.getFrameInfo();
664 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI.getOffsetOfLocalArea();
666 FIOffset = getFrameIndexOffset(MF, FrameIndex);
668 if (MI.getOperand(i+3).isImm()) {
669 // Offset is a 32-bit integer.
670 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
671 MI.getOperand(i + 3).ChangeToImmediate(Offset);
673 // Offset is symbolic. This is extremely rare.
674 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
675 MI.getOperand(i+3).setOffset(Offset);
681 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
682 RegScavenger *RS) const {
683 MachineFrameInfo *MFI = MF.getFrameInfo();
685 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
686 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
688 if (TailCallReturnAddrDelta < 0) {
689 // create RETURNADDR area
698 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
699 (-1U*SlotSize)+TailCallReturnAddrDelta,
704 assert((TailCallReturnAddrDelta <= 0) &&
705 "The Delta should always be zero or negative");
706 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
708 // Create a frame entry for the EBP register that must be saved.
709 int FrameIdx = MFI->CreateFixedObject(SlotSize,
711 TFI.getOffsetOfLocalArea() +
712 TailCallReturnAddrDelta,
714 assert(FrameIdx == MFI->getObjectIndexBegin() &&
715 "Slot for EBP register must be last in order to be found!");
720 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
721 /// stack pointer by a constant value.
723 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
724 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
725 const TargetInstrInfo &TII) {
726 bool isSub = NumBytes < 0;
727 uint64_t Offset = isSub ? -NumBytes : NumBytes;
728 unsigned Opc = isSub ?
729 getSUBriOpcode(Is64Bit, Offset) :
730 getADDriOpcode(Is64Bit, Offset);
731 uint64_t Chunk = (1LL << 31) - 1;
732 DebugLoc DL = MBB.findDebugLoc(MBBI);
735 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
737 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
740 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
745 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
747 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
748 unsigned StackPtr, uint64_t *NumBytes = NULL) {
749 if (MBBI == MBB.begin()) return;
751 MachineBasicBlock::iterator PI = prior(MBBI);
752 unsigned Opc = PI->getOpcode();
753 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
754 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
755 PI->getOperand(0).getReg() == StackPtr) {
757 *NumBytes += PI->getOperand(2).getImm();
759 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
760 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
761 PI->getOperand(0).getReg() == StackPtr) {
763 *NumBytes -= PI->getOperand(2).getImm();
768 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
770 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
771 MachineBasicBlock::iterator &MBBI,
772 unsigned StackPtr, uint64_t *NumBytes = NULL) {
773 // FIXME: THIS ISN'T RUN!!!
776 if (MBBI == MBB.end()) return;
778 MachineBasicBlock::iterator NI = llvm::next(MBBI);
779 if (NI == MBB.end()) return;
781 unsigned Opc = NI->getOpcode();
782 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
783 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
784 NI->getOperand(0).getReg() == StackPtr) {
786 *NumBytes -= NI->getOperand(2).getImm();
789 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
790 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
791 NI->getOperand(0).getReg() == StackPtr) {
793 *NumBytes += NI->getOperand(2).getImm();
799 /// mergeSPUpdates - Checks the instruction before/after the passed
800 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
801 /// stack adjustment is returned as a positive value for ADD and a negative for
803 static int mergeSPUpdates(MachineBasicBlock &MBB,
804 MachineBasicBlock::iterator &MBBI,
806 bool doMergeWithPrevious) {
807 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
808 (!doMergeWithPrevious && MBBI == MBB.end()))
811 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
812 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
813 unsigned Opc = PI->getOpcode();
816 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
817 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
818 PI->getOperand(0).getReg() == StackPtr){
819 Offset += PI->getOperand(2).getImm();
821 if (!doMergeWithPrevious) MBBI = NI;
822 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
823 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
824 PI->getOperand(0).getReg() == StackPtr) {
825 Offset -= PI->getOperand(2).getImm();
827 if (!doMergeWithPrevious) MBBI = NI;
833 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
835 unsigned FramePtr) const {
836 MachineFrameInfo *MFI = MF.getFrameInfo();
837 MachineModuleInfo &MMI = MF.getMMI();
839 // Add callee saved registers to move list.
840 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
841 if (CSI.empty()) return;
843 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
844 const TargetData *TD = MF.getTarget().getTargetData();
845 bool HasFP = hasFP(MF);
847 // Calculate amount of bytes used for return address storing.
849 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
850 TargetFrameInfo::StackGrowsUp ?
851 TD->getPointerSize() : -TD->getPointerSize());
853 // FIXME: This is dirty hack. The code itself is pretty mess right now.
854 // It should be rewritten from scratch and generalized sometimes.
856 // Determine maximum offset (minumum due to stack growth).
857 int64_t MaxOffset = 0;
858 for (std::vector<CalleeSavedInfo>::const_iterator
859 I = CSI.begin(), E = CSI.end(); I != E; ++I)
860 MaxOffset = std::min(MaxOffset,
861 MFI->getObjectOffset(I->getFrameIdx()));
863 // Calculate offsets.
864 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
865 for (std::vector<CalleeSavedInfo>::const_iterator
866 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
867 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
868 unsigned Reg = I->getReg();
869 Offset = MaxOffset - Offset + saveAreaOffset;
871 // Don't output a new machine move if we're re-saving the frame
872 // pointer. This happens when the PrologEpilogInserter has inserted an extra
873 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
874 // generates one when frame pointers are used. If we generate a "machine
875 // move" for this extra "PUSH", the linker will lose track of the fact that
876 // the frame pointer should have the value of the first "PUSH" when it's
879 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
880 // another bug. I.e., one where we generate a prolog like this:
888 // The immediate re-push of EBP is unnecessary. At the least, it's an
889 // optimization bug. EBP can be used as a scratch register in certain
890 // cases, but probably not when we have a frame pointer.
891 if (HasFP && FramePtr == Reg)
894 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
895 MachineLocation CSSrc(Reg);
896 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
900 /// emitPrologue - Push callee-saved registers onto the stack, which
901 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
902 /// space for local variables. Also emit labels used by the exception handler to
903 /// generate the exception handling frames.
904 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
905 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
906 MachineBasicBlock::iterator MBBI = MBB.begin();
907 MachineFrameInfo *MFI = MF.getFrameInfo();
908 const Function *Fn = MF.getFunction();
909 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
910 MachineModuleInfo &MMI = MF.getMMI();
911 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
912 bool needsFrameMoves = MMI.hasDebugInfo() ||
913 !Fn->doesNotThrow() || UnwindTablesMandatory;
914 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
915 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
916 bool HasFP = hasFP(MF);
919 // Add RETADDR move area to callee saved frame size.
920 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
921 if (TailCallReturnAddrDelta < 0)
922 X86FI->setCalleeSavedFrameSize(
923 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
925 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
926 // function, and use up to 128 bytes of stack space, don't have a frame
927 // pointer, calls, or dynamic alloca then we do not need to adjust the
928 // stack pointer (we fit in the Red Zone).
929 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
930 !needsStackRealignment(MF) &&
931 !MFI->hasVarSizedObjects() && // No dynamic alloca.
932 !MFI->adjustsStack() && // No calls.
933 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
934 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
935 if (HasFP) MinSize += SlotSize;
936 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
937 MFI->setStackSize(StackSize);
938 } else if (Subtarget->isTargetWin64()) {
939 // We need to always allocate 32 bytes as register spill area.
940 // FIXME: We might reuse these 32 bytes for leaf functions.
942 MFI->setStackSize(StackSize);
945 // Insert stack pointer adjustment for later moving of return addr. Only
946 // applies to tail call optimized functions where the callee argument stack
947 // size is bigger than the callers.
948 if (TailCallReturnAddrDelta < 0) {
950 BuildMI(MBB, MBBI, DL,
951 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
954 .addImm(-TailCallReturnAddrDelta);
955 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
958 // Mapping for machine moves:
960 // DST: VirtualFP AND
961 // SRC: VirtualFP => DW_CFA_def_cfa_offset
962 // ELSE => DW_CFA_def_cfa
964 // SRC: VirtualFP AND
965 // DST: Register => DW_CFA_def_cfa_register
968 // OFFSET < 0 => DW_CFA_offset_extended_sf
969 // REG < 64 => DW_CFA_offset + Reg
970 // ELSE => DW_CFA_offset_extended
972 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
973 const TargetData *TD = MF.getTarget().getTargetData();
974 uint64_t NumBytes = 0;
975 int stackGrowth = -TD->getPointerSize();
978 // Calculate required stack adjustment.
979 uint64_t FrameSize = StackSize - SlotSize;
980 if (needsStackRealignment(MF))
981 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
983 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
985 // Get the offset of the stack slot for the EBP register, which is
986 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
987 // Update the frame offset adjustment.
988 MFI->setOffsetAdjustment(-NumBytes);
990 // Save EBP/RBP into the appropriate stack slot.
991 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
992 .addReg(FramePtr, RegState::Kill);
994 if (needsFrameMoves) {
995 // Mark the place where EBP/RBP was saved.
996 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
997 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
999 // Define the current CFA rule to use the provided offset.
1001 MachineLocation SPDst(MachineLocation::VirtualFP);
1002 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
1003 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
1005 // FIXME: Verify & implement for FP
1006 MachineLocation SPDst(StackPtr);
1007 MachineLocation SPSrc(StackPtr, stackGrowth);
1008 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
1011 // Change the rule for the FramePtr to be an "offset" rule.
1012 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
1013 MachineLocation FPSrc(FramePtr);
1014 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1017 // Update EBP with the new base value...
1018 BuildMI(MBB, MBBI, DL,
1019 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1022 if (needsFrameMoves) {
1023 // Mark effective beginning of when frame pointer becomes valid.
1024 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1025 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
1027 // Define the current CFA to use the EBP/RBP register.
1028 MachineLocation FPDst(FramePtr);
1029 MachineLocation FPSrc(MachineLocation::VirtualFP);
1030 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1033 // Mark the FramePtr as live-in in every block except the entry.
1034 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
1036 I->addLiveIn(FramePtr);
1039 if (needsStackRealignment(MF)) {
1041 BuildMI(MBB, MBBI, DL,
1042 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1043 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1045 // The EFLAGS implicit def is dead.
1046 MI->getOperand(3).setIsDead();
1049 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1052 // Skip the callee-saved push instructions.
1053 bool PushedRegs = false;
1054 int StackOffset = 2 * stackGrowth;
1056 while (MBBI != MBB.end() &&
1057 (MBBI->getOpcode() == X86::PUSH32r ||
1058 MBBI->getOpcode() == X86::PUSH64r)) {
1062 if (!HasFP && needsFrameMoves) {
1063 // Mark callee-saved push instruction.
1064 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1065 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
1067 // Define the current CFA rule to use the provided offset.
1068 unsigned Ptr = StackSize ?
1069 MachineLocation::VirtualFP : StackPtr;
1070 MachineLocation SPDst(Ptr);
1071 MachineLocation SPSrc(Ptr, StackOffset);
1072 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1073 StackOffset += stackGrowth;
1077 DL = MBB.findDebugLoc(MBBI);
1079 // Adjust stack pointer: ESP -= numbytes.
1080 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1081 // Check, whether EAX is livein for this function.
1082 bool isEAXAlive = false;
1083 for (MachineRegisterInfo::livein_iterator
1084 II = MF.getRegInfo().livein_begin(),
1085 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1086 unsigned Reg = II->first;
1087 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1088 Reg == X86::AH || Reg == X86::AL);
1091 // Function prologue calls _alloca to probe the stack when allocating more
1092 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1093 // to ensure that the guard pages used by the OS virtual memory manager are
1094 // allocated in correct sequence.
1096 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1098 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1099 .addExternalSymbol("_alloca")
1100 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1103 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1104 .addReg(X86::EAX, RegState::Kill);
1106 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1107 // allocated bytes for EAX.
1108 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1109 .addImm(NumBytes - 4);
1110 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1111 .addExternalSymbol("_alloca")
1112 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1115 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1117 StackPtr, false, NumBytes - 4);
1118 MBB.insert(MBBI, MI);
1120 } else if (NumBytes) {
1121 // If there is an SUB32ri of ESP immediately before this instruction, merge
1122 // the two. This can be the case when tail call elimination is enabled and
1123 // the callee has more arguments then the caller.
1124 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1126 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1127 // instruction, merge the two instructions.
1128 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1131 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1134 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1135 // Mark end of stack pointer adjustment.
1136 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1137 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
1139 if (!HasFP && NumBytes) {
1140 // Define the current CFA rule to use the provided offset.
1142 MachineLocation SPDst(MachineLocation::VirtualFP);
1143 MachineLocation SPSrc(MachineLocation::VirtualFP,
1144 -StackSize + stackGrowth);
1145 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1147 // FIXME: Verify & implement for FP
1148 MachineLocation SPDst(StackPtr);
1149 MachineLocation SPSrc(StackPtr, stackGrowth);
1150 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1154 // Emit DWARF info specifying the offsets of the callee-saved registers.
1156 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
1160 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1161 MachineBasicBlock &MBB) const {
1162 const MachineFrameInfo *MFI = MF.getFrameInfo();
1163 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1164 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1165 unsigned RetOpcode = MBBI->getOpcode();
1166 DebugLoc DL = MBBI->getDebugLoc();
1168 switch (RetOpcode) {
1170 llvm_unreachable("Can only insert epilog into returning blocks");
1173 case X86::TCRETURNdi:
1174 case X86::TCRETURNri:
1175 case X86::TCRETURNmi:
1176 case X86::TCRETURNdi64:
1177 case X86::TCRETURNri64:
1178 case X86::TCRETURNmi64:
1179 case X86::EH_RETURN:
1180 case X86::EH_RETURN64:
1181 break; // These are ok
1184 // Get the number of bytes to allocate from the FrameInfo.
1185 uint64_t StackSize = MFI->getStackSize();
1186 uint64_t MaxAlign = MFI->getMaxAlignment();
1187 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1188 uint64_t NumBytes = 0;
1191 // Calculate required stack adjustment.
1192 uint64_t FrameSize = StackSize - SlotSize;
1193 if (needsStackRealignment(MF))
1194 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1196 NumBytes = FrameSize - CSSize;
1199 BuildMI(MBB, MBBI, DL,
1200 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1202 NumBytes = StackSize - CSSize;
1205 // Skip the callee-saved pop instructions.
1206 MachineBasicBlock::iterator LastCSPop = MBBI;
1207 while (MBBI != MBB.begin()) {
1208 MachineBasicBlock::iterator PI = prior(MBBI);
1209 unsigned Opc = PI->getOpcode();
1211 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1212 !PI->getDesc().isTerminator())
1218 DL = MBBI->getDebugLoc();
1220 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1221 // instruction, merge the two instructions.
1222 if (NumBytes || MFI->hasVarSizedObjects())
1223 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1225 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1226 // slot before popping them off! Same applies for the case, when stack was
1228 if (needsStackRealignment(MF)) {
1229 // We cannot use LEA here, because stack pointer was realigned. We need to
1230 // deallocate local frame back.
1232 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1233 MBBI = prior(LastCSPop);
1236 BuildMI(MBB, MBBI, DL,
1237 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1238 StackPtr).addReg(FramePtr);
1239 } else if (MFI->hasVarSizedObjects()) {
1241 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1243 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1244 FramePtr, false, -CSSize);
1245 MBB.insert(MBBI, MI);
1247 BuildMI(MBB, MBBI, DL,
1248 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1251 } else if (NumBytes) {
1252 // Adjust stack pointer back: ESP += numbytes.
1253 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1256 // We're returning from function via eh_return.
1257 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1258 MBBI = prior(MBB.end());
1259 MachineOperand &DestAddr = MBBI->getOperand(0);
1260 assert(DestAddr.isReg() && "Offset should be in register!");
1261 BuildMI(MBB, MBBI, DL,
1262 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1263 StackPtr).addReg(DestAddr.getReg());
1264 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1265 RetOpcode == X86::TCRETURNmi ||
1266 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1267 RetOpcode == X86::TCRETURNmi64) {
1268 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1269 // Tail call return: adjust the stack pointer and jump to callee.
1270 MBBI = prior(MBB.end());
1271 MachineOperand &JumpTarget = MBBI->getOperand(0);
1272 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1273 assert(StackAdjust.isImm() && "Expecting immediate value.");
1275 // Adjust stack pointer.
1276 int StackAdj = StackAdjust.getImm();
1277 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1279 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1281 // Incoporate the retaddr area.
1282 Offset = StackAdj-MaxTCDelta;
1283 assert(Offset >= 0 && "Offset should never be negative");
1286 // Check for possible merge with preceeding ADD instruction.
1287 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1288 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1291 // Jump to label or value in register.
1292 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1293 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1294 ? X86::TAILJMPd : X86::TAILJMPd64)).
1295 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1296 JumpTarget.getTargetFlags());
1297 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1298 MachineInstrBuilder MIB =
1299 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1300 ? X86::TAILJMPm : X86::TAILJMPm64));
1301 for (unsigned i = 0; i != 5; ++i)
1302 MIB.addOperand(MBBI->getOperand(i));
1303 } else if (RetOpcode == X86::TCRETURNri64) {
1304 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1306 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1309 MachineInstr *NewMI = prior(MBBI);
1310 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1311 NewMI->addOperand(MBBI->getOperand(i));
1313 // Delete the pseudo instruction TCRETURN.
1315 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1316 (X86FI->getTCReturnAddrDelta() < 0)) {
1317 // Add the return addr area delta back since we are not tail calling.
1318 int delta = -1*X86FI->getTCReturnAddrDelta();
1319 MBBI = prior(MBB.end());
1321 // Check for possible merge with preceeding ADD instruction.
1322 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1323 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1327 unsigned X86RegisterInfo::getRARegister() const {
1328 return Is64Bit ? X86::RIP // Should have dwarf #16.
1329 : X86::EIP; // Should have dwarf #8.
1332 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1333 return hasFP(MF) ? FramePtr : StackPtr;
1337 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1338 // Calculate amount of bytes used for return address storing
1339 int stackGrowth = (Is64Bit ? -8 : -4);
1341 // Initial state of the frame pointer is esp+stackGrowth.
1342 MachineLocation Dst(MachineLocation::VirtualFP);
1343 MachineLocation Src(StackPtr, stackGrowth);
1344 Moves.push_back(MachineMove(0, Dst, Src));
1346 // Add return address to move list
1347 MachineLocation CSDst(StackPtr, stackGrowth);
1348 MachineLocation CSSrc(getRARegister());
1349 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1352 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1353 llvm_unreachable("What is the exception register");
1357 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1358 llvm_unreachable("What is the exception handler register");
1363 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1364 switch (VT.getSimpleVT().SimpleTy) {
1365 default: return Reg;
1370 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1372 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1374 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1376 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1382 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1384 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1386 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1388 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1390 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1392 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1394 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1396 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1398 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1400 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1402 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1404 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1406 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1408 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1410 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1412 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1418 default: return Reg;
1419 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1421 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1423 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1425 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1427 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1429 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1431 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1433 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1435 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1437 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1439 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1441 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1443 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1445 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1447 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1449 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1454 default: return Reg;
1455 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1457 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1459 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1461 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1463 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1465 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1467 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1469 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1471 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1473 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1475 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1477 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1479 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1481 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1483 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1485 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1490 default: return Reg;
1491 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1493 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1495 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1497 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1499 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1501 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1503 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1505 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1507 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1509 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1511 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1513 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1515 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1517 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1519 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1521 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1530 #include "X86GenRegisterInfo.inc"
1533 struct MSAH : public MachineFunctionPass {
1535 MSAH() : MachineFunctionPass(&ID) {}
1537 virtual bool runOnMachineFunction(MachineFunction &MF) {
1538 const X86TargetMachine *TM =
1539 static_cast<const X86TargetMachine *>(&MF.getTarget());
1540 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
1541 MachineRegisterInfo &RI = MF.getRegInfo();
1542 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1543 unsigned StackAlignment = X86RI->getStackAlignment();
1545 // Be over-conservative: scan over all vreg defs and find whether vector
1546 // registers are used. If yes, there is a possibility that vector register
1547 // will be spilled and thus require dynamic stack realignment.
1548 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1549 RegNum < RI.getLastVirtReg(); ++RegNum)
1550 if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) {
1551 FuncInfo->setReserveFP(true);
1559 virtual const char *getPassName() const {
1560 return "X86 Maximal Stack Alignment Check";
1563 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1564 AU.setPreservesCFG();
1565 MachineFunctionPass::getAnalysisUsage(AU);
1573 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }