1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
68 // getDwarfRegNum - This function maps LLVM register identifiers to the
69 // Dwarf specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
74 if (!Subtarget->is64Bit()) {
75 if (Subtarget->isTargetDarwin()) {
77 Flavour = DWARFFlavour::X86_32_DarwinEH;
79 Flavour = DWARFFlavour::X86_32_Generic;
80 } else if (Subtarget->isTargetCygMing()) {
81 // Unsupported by now, just quick fallback
82 Flavour = DWARFFlavour::X86_32_Generic;
84 Flavour = DWARFFlavour::X86_32_Generic;
88 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
91 // getX86RegNum - This function maps LLVM register identifiers to their X86
92 // specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8: case X86::MM0:
132 case X86::XMM1: case X86::XMM9: case X86::MM1:
134 case X86::XMM2: case X86::XMM10: case X86::MM2:
136 case X86::XMM3: case X86::XMM11: case X86::MM3:
138 case X86::XMM4: case X86::XMM12: case X86::MM4:
140 case X86::XMM5: case X86::XMM13: case X86::MM5:
142 case X86::XMM6: case X86::XMM14: case X86::MM6:
144 case X86::XMM7: case X86::XMM15: case X86::MM7:
148 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
149 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
154 const TargetRegisterClass *
155 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
156 if (RC == &X86::CCRRegClass) {
158 return &X86::GR64RegClass;
160 return &X86::GR32RegClass;
166 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
167 bool callsEHReturn = false;
170 const MachineFrameInfo *MFI = MF->getFrameInfo();
171 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
172 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
175 static const unsigned CalleeSavedRegs32Bit[] = {
176 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
179 static const unsigned CalleeSavedRegs32EHRet[] = {
180 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
183 static const unsigned CalleeSavedRegs64Bit[] = {
184 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
187 static const unsigned CalleeSavedRegs64EHRet[] = {
188 X86::RAX, X86::RDX, X86::RBX, X86::R12,
189 X86::R13, X86::R14, X86::R15, X86::RBP, 0
192 static const unsigned CalleeSavedRegsWin64[] = {
193 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
194 X86::R12, X86::R13, X86::R14, X86::R15,
195 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
196 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
197 X86::XMM14, X86::XMM15, 0
202 return CalleeSavedRegsWin64;
204 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
206 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
210 const TargetRegisterClass* const*
211 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
212 bool callsEHReturn = false;
215 const MachineFrameInfo *MFI = MF->getFrameInfo();
216 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
217 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
220 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
221 &X86::GR32RegClass, &X86::GR32RegClass,
222 &X86::GR32RegClass, &X86::GR32RegClass, 0
224 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
225 &X86::GR32RegClass, &X86::GR32RegClass,
226 &X86::GR32RegClass, &X86::GR32RegClass,
227 &X86::GR32RegClass, &X86::GR32RegClass, 0
229 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
230 &X86::GR64RegClass, &X86::GR64RegClass,
231 &X86::GR64RegClass, &X86::GR64RegClass,
232 &X86::GR64RegClass, &X86::GR64RegClass, 0
234 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
235 &X86::GR64RegClass, &X86::GR64RegClass,
236 &X86::GR64RegClass, &X86::GR64RegClass,
237 &X86::GR64RegClass, &X86::GR64RegClass,
238 &X86::GR64RegClass, &X86::GR64RegClass, 0
240 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
241 &X86::GR64RegClass, &X86::GR64RegClass,
242 &X86::GR64RegClass, &X86::GR64RegClass,
243 &X86::GR64RegClass, &X86::GR64RegClass,
244 &X86::GR64RegClass, &X86::GR64RegClass,
245 &X86::VR128RegClass, &X86::VR128RegClass,
246 &X86::VR128RegClass, &X86::VR128RegClass,
247 &X86::VR128RegClass, &X86::VR128RegClass,
248 &X86::VR128RegClass, &X86::VR128RegClass,
249 &X86::VR128RegClass, &X86::VR128RegClass, 0
254 return CalleeSavedRegClassesWin64;
256 return (callsEHReturn ?
257 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
259 return (callsEHReturn ?
260 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
264 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
265 BitVector Reserved(getNumRegs());
266 Reserved.set(X86::RSP);
267 Reserved.set(X86::ESP);
268 Reserved.set(X86::SP);
269 Reserved.set(X86::SPL);
271 Reserved.set(X86::RBP);
272 Reserved.set(X86::EBP);
273 Reserved.set(X86::BP);
274 Reserved.set(X86::BPL);
279 //===----------------------------------------------------------------------===//
280 // Stack Frame Processing methods
281 //===----------------------------------------------------------------------===//
283 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
284 unsigned MaxAlign = 0;
285 for (int i = FFI->getObjectIndexBegin(),
286 e = FFI->getObjectIndexEnd(); i != e; ++i) {
287 if (FFI->isDeadObjectIndex(i))
289 unsigned Align = FFI->getObjectAlignment(i);
290 MaxAlign = std::max(MaxAlign, Align);
296 // hasFP - Return true if the specified function should have a dedicated frame
297 // pointer register. This is true if the function has variable sized allocas or
298 // if frame pointer elimination is disabled.
300 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
301 const MachineFrameInfo *MFI = MF.getFrameInfo();
302 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
304 return (NoFramePointerElim ||
305 needsStackRealignment(MF) ||
306 MFI->hasVarSizedObjects() ||
307 MFI->isFrameAddressTaken() ||
308 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
309 (MMI && MMI->callsUnwindInit()));
312 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
313 const MachineFrameInfo *MFI = MF.getFrameInfo();;
315 // FIXME: Currently we don't support stack realignment for functions with
316 // variable-sized allocas
317 return (RealignStack &&
318 (MFI->getMaxAlignment() > StackAlign &&
319 !MFI->hasVarSizedObjects()));
322 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
323 return !MF.getFrameInfo()->hasVarSizedObjects();
327 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
328 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
329 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
331 if (needsStackRealignment(MF)) {
333 // Skip the saved EBP
336 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
337 assert( (-(Offset + StackSize)) % Align == 0);
338 return Offset + StackSize;
341 // FIXME: Support tail calls
344 return Offset + StackSize;
346 // Skip the saved EBP
349 // Skip the RETADDR move area
350 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
351 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
352 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
358 void X86RegisterInfo::
359 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
360 MachineBasicBlock::iterator I) const {
361 if (!hasReservedCallFrame(MF)) {
362 // If the stack pointer can be changed after prologue, turn the
363 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
364 // adjcallstackdown instruction into 'add ESP, <amt>'
365 // TODO: consider using push / pop instead of sub + store / add
366 MachineInstr *Old = I;
367 uint64_t Amount = Old->getOperand(0).getImm();
369 // We need to keep the stack aligned properly. To do this, we round the
370 // amount of space needed for the outgoing arguments up to the next
371 // alignment boundary.
372 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
374 MachineInstr *New = 0;
375 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
376 New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
377 StackPtr).addReg(StackPtr).addImm(Amount);
379 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
380 // factor out the amount the callee already popped.
381 uint64_t CalleeAmt = Old->getOperand(1).getImm();
384 unsigned Opc = (Amount < 128) ?
385 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
386 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
387 New = BuildMI(MF, TII.get(Opc), StackPtr)
388 .addReg(StackPtr).addImm(Amount);
392 // Replace the pseudo instruction with a new instruction...
393 if (New) MBB.insert(I, New);
395 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
396 // If we are performing frame pointer elimination and if the callee pops
397 // something off the stack pointer, add it back. We do this until we have
398 // more advanced stack pointer tracking ability.
399 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
400 unsigned Opc = (CalleeAmt < 128) ?
401 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
402 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
404 BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
412 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
413 int SPAdj, RegScavenger *RS) const{
414 assert(SPAdj == 0 && "Unexpected");
417 MachineInstr &MI = *II;
418 MachineFunction &MF = *MI.getParent()->getParent();
419 while (!MI.getOperand(i).isFI()) {
421 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
424 int FrameIndex = MI.getOperand(i).getIndex();
427 if (needsStackRealignment(MF))
428 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
430 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
432 // This must be part of a four operand memory reference. Replace the
433 // FrameIndex with base register with EBP. Add an offset to the offset.
434 MI.getOperand(i).ChangeToRegister(BasePtr, false);
436 // Now add the frame object offset to the offset from EBP. Offset is a
438 int Offset = getFrameIndexOffset(MF, FrameIndex) +
439 (int)(MI.getOperand(i+3).getImm());
441 MI.getOperand(i+3).ChangeToImmediate(Offset);
445 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
446 RegScavenger *RS) const {
447 MachineFrameInfo *FFI = MF.getFrameInfo();
449 // Calculate and set max stack object alignment early, so we can decide
450 // whether we will need stack realignment (and thus FP).
451 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
452 calculateMaxStackAlignment(FFI));
454 FFI->setMaxAlignment(MaxAlign);
458 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
459 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
460 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
461 if (TailCallReturnAddrDelta < 0) {
462 // create RETURNADDR area
472 CreateFixedObject(-TailCallReturnAddrDelta,
473 (-1*SlotSize)+TailCallReturnAddrDelta);
476 assert((TailCallReturnAddrDelta <= 0) &&
477 "The Delta should always be zero or negative");
478 // Create a frame entry for the EBP register that must be saved.
479 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
481 TailCallReturnAddrDelta);
482 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
483 "Slot for EBP register must be last in order to be found!");
487 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
488 /// stack pointer by a constant value.
490 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
491 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
492 const TargetInstrInfo &TII) {
493 bool isSub = NumBytes < 0;
494 uint64_t Offset = isSub ? -NumBytes : NumBytes;
497 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
498 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
500 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
501 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
502 uint64_t Chunk = (1LL << 31) - 1;
505 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
506 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
511 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
513 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
514 unsigned StackPtr, uint64_t *NumBytes = NULL) {
515 if (MBBI == MBB.begin()) return;
517 MachineBasicBlock::iterator PI = prior(MBBI);
518 unsigned Opc = PI->getOpcode();
519 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
520 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
521 PI->getOperand(0).getReg() == StackPtr) {
523 *NumBytes += PI->getOperand(2).getImm();
525 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
526 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
527 PI->getOperand(0).getReg() == StackPtr) {
529 *NumBytes -= PI->getOperand(2).getImm();
534 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
536 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
537 MachineBasicBlock::iterator &MBBI,
538 unsigned StackPtr, uint64_t *NumBytes = NULL) {
541 if (MBBI == MBB.end()) return;
543 MachineBasicBlock::iterator NI = next(MBBI);
544 if (NI == MBB.end()) return;
546 unsigned Opc = NI->getOpcode();
547 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
548 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
549 NI->getOperand(0).getReg() == StackPtr) {
551 *NumBytes -= NI->getOperand(2).getImm();
554 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
555 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
556 NI->getOperand(0).getReg() == StackPtr) {
558 *NumBytes += NI->getOperand(2).getImm();
564 /// mergeSPUpdates - Checks the instruction before/after the passed
565 /// instruction. If it is an ADD/SUB instruction it is deleted
566 /// argument and the stack adjustment is returned as a positive value for ADD
567 /// and a negative for SUB.
568 static int mergeSPUpdates(MachineBasicBlock &MBB,
569 MachineBasicBlock::iterator &MBBI,
571 bool doMergeWithPrevious) {
573 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
574 (!doMergeWithPrevious && MBBI == MBB.end()))
579 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
580 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
581 unsigned Opc = PI->getOpcode();
582 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
583 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
584 PI->getOperand(0).getReg() == StackPtr){
585 Offset += PI->getOperand(2).getImm();
587 if (!doMergeWithPrevious) MBBI = NI;
588 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
589 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
590 PI->getOperand(0).getReg() == StackPtr) {
591 Offset -= PI->getOperand(2).getImm();
593 if (!doMergeWithPrevious) MBBI = NI;
599 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
600 unsigned FrameLabelId,
601 unsigned ReadyLabelId) const {
602 MachineFrameInfo *MFI = MF.getFrameInfo();
603 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
607 uint64_t StackSize = MFI->getStackSize();
608 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
609 const TargetData *TD = MF.getTarget().getTargetData();
611 // Calculate amount of bytes used for return address storing
613 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
614 TargetFrameInfo::StackGrowsUp ?
615 TD->getPointerSize() : -TD->getPointerSize());
618 // Show update of SP.
621 MachineLocation SPDst(MachineLocation::VirtualFP);
622 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
623 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
625 MachineLocation SPDst(MachineLocation::VirtualFP);
626 MachineLocation SPSrc(MachineLocation::VirtualFP,
627 -StackSize+stackGrowth);
628 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
631 //FIXME: Verify & implement for FP
632 MachineLocation SPDst(StackPtr);
633 MachineLocation SPSrc(StackPtr, stackGrowth);
634 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
637 // Add callee saved registers to move list.
638 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
640 // FIXME: This is dirty hack. The code itself is pretty mess right now.
641 // It should be rewritten from scratch and generalized sometimes.
643 // Determine maximum offset (minumum due to stack growth)
644 int64_t MaxOffset = 0;
645 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
646 MaxOffset = std::min(MaxOffset,
647 MFI->getObjectOffset(CSI[I].getFrameIdx()));
650 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
651 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
652 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
653 unsigned Reg = CSI[I].getReg();
654 Offset = (MaxOffset-Offset+saveAreaOffset);
655 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
656 MachineLocation CSSrc(Reg);
657 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
662 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
663 MachineLocation FPSrc(FramePtr);
664 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
667 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
668 MachineLocation FPSrc(MachineLocation::VirtualFP);
669 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
673 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
674 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
675 MachineFrameInfo *MFI = MF.getFrameInfo();
676 const Function* Fn = MF.getFunction();
677 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
678 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
679 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
680 MachineBasicBlock::iterator MBBI = MBB.begin();
681 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
682 !Fn->doesNotThrow() ||
683 UnwindTablesMandatory;
684 // Prepare for frame info.
685 unsigned FrameLabelId = 0;
687 // Get the number of bytes to allocate from the FrameInfo.
688 uint64_t StackSize = MFI->getStackSize();
689 // Get desired stack alignment
690 uint64_t MaxAlign = MFI->getMaxAlignment();
692 // Add RETADDR move area to callee saved frame size.
693 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
694 if (TailCallReturnAddrDelta < 0)
695 X86FI->setCalleeSavedFrameSize(
696 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
698 // Insert stack pointer adjustment for later moving of return addr. Only
699 // applies to tail call optimized functions where the callee argument stack
700 // size is bigger than the callers.
701 if (TailCallReturnAddrDelta < 0) {
702 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
703 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
706 uint64_t NumBytes = 0;
708 // Calculate required stack adjustment
709 uint64_t FrameSize = StackSize - SlotSize;
710 if (needsStackRealignment(MF))
711 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
713 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
715 // Get the offset of the stack slot for the EBP register... which is
716 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
717 // Update the frame offset adjustment.
718 MFI->setOffsetAdjustment(-NumBytes);
720 // Save EBP into the appropriate stack slot...
721 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
724 if (needsFrameMoves) {
725 // Mark effective beginning of when frame pointer becomes valid.
726 FrameLabelId = MMI->NextLabelID();
727 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
730 // Update EBP with the new base value...
731 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
735 if (needsStackRealignment(MF))
737 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
738 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
740 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
742 unsigned ReadyLabelId = 0;
743 if (needsFrameMoves) {
744 // Mark effective beginning of when frame pointer is ready.
745 ReadyLabelId = MMI->NextLabelID();
746 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
749 // Skip the callee-saved push instructions.
750 while (MBBI != MBB.end() &&
751 (MBBI->getOpcode() == X86::PUSH32r ||
752 MBBI->getOpcode() == X86::PUSH64r))
755 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
756 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
757 // Check, whether EAX is livein for this function
758 bool isEAXAlive = false;
759 for (MachineRegisterInfo::livein_iterator
760 II = MF.getRegInfo().livein_begin(),
761 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
762 unsigned Reg = II->first;
763 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
764 Reg == X86::AH || Reg == X86::AL);
767 // Function prologue calls _alloca to probe the stack when allocating
768 // more than 4k bytes in one go. Touching the stack at 4K increments is
769 // necessary to ensure that the guard pages used by the OS virtual memory
770 // manager are allocated in correct sequence.
772 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
773 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
774 .addExternalSymbol("_alloca");
777 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
778 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
779 // allocated bytes for EAX.
780 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
781 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
782 .addExternalSymbol("_alloca");
784 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
785 StackPtr, false, NumBytes-4);
786 MBB.insert(MBBI, MI);
789 // If there is an SUB32ri of ESP immediately before this instruction,
790 // merge the two. This can be the case when tail call elimination is
791 // enabled and the callee has more arguments then the caller.
792 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
793 // If there is an ADD32ri or SUB32ri of ESP immediately after this
794 // instruction, merge the two instructions.
795 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
798 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
803 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
806 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
807 MachineBasicBlock &MBB) const {
808 const MachineFrameInfo *MFI = MF.getFrameInfo();
809 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
810 MachineBasicBlock::iterator MBBI = prior(MBB.end());
811 unsigned RetOpcode = MBBI->getOpcode();
816 case X86::TCRETURNdi:
817 case X86::TCRETURNri:
818 case X86::TCRETURNri64:
819 case X86::TCRETURNdi64:
821 case X86::EH_RETURN64:
824 case X86::TAILJMPm: break; // These are ok
826 assert(0 && "Can only insert epilog into returning blocks");
829 // Get the number of bytes to allocate from the FrameInfo
830 uint64_t StackSize = MFI->getStackSize();
831 uint64_t MaxAlign = MFI->getMaxAlignment();
832 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
833 uint64_t NumBytes = 0;
836 // Calculate required stack adjustment
837 uint64_t FrameSize = StackSize - SlotSize;
838 if (needsStackRealignment(MF))
839 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
841 NumBytes = FrameSize - CSSize;
844 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
846 NumBytes = StackSize - CSSize;
848 // Skip the callee-saved pop instructions.
849 MachineBasicBlock::iterator LastCSPop = MBBI;
850 while (MBBI != MBB.begin()) {
851 MachineBasicBlock::iterator PI = prior(MBBI);
852 unsigned Opc = PI->getOpcode();
853 if (Opc != X86::POP32r && Opc != X86::POP64r && !PI->getDesc().isReturn())
858 // If there is an ADD32ri or SUB32ri of ESP immediately before this
859 // instruction, merge the two instructions.
860 if (NumBytes || MFI->hasVarSizedObjects())
861 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
863 // If dynamic alloca is used, then reset esp to point to the last callee-saved
864 // slot before popping them off! Same applies for the case, when stack was
866 if (needsStackRealignment(MF)) {
867 // We cannot use LEA here, because stack pointer was realigned. We need to
868 // deallocate local frame back
870 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
871 MBBI = prior(LastCSPop);
875 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
876 StackPtr).addReg(FramePtr);
877 } else if (MFI->hasVarSizedObjects()) {
879 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
880 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
881 FramePtr, false, -CSSize);
882 MBB.insert(MBBI, MI);
884 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
885 StackPtr).addReg(FramePtr);
888 // adjust stack pointer back: ESP += numbytes
890 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
893 // We're returning from function via eh_return.
894 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
895 MBBI = prior(MBB.end());
896 MachineOperand &DestAddr = MBBI->getOperand(0);
897 assert(DestAddr.isReg() && "Offset should be in register!");
899 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
900 StackPtr).addReg(DestAddr.getReg());
901 // Tail call return: adjust the stack pointer and jump to callee
902 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
903 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
904 MBBI = prior(MBB.end());
905 MachineOperand &JumpTarget = MBBI->getOperand(0);
906 MachineOperand &StackAdjust = MBBI->getOperand(1);
907 assert(StackAdjust.isImm() && "Expecting immediate value.");
909 // Adjust stack pointer.
910 int StackAdj = StackAdjust.getImm();
911 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
913 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
914 // Incoporate the retaddr area.
915 Offset = StackAdj-MaxTCDelta;
916 assert(Offset >= 0 && "Offset should never be negative");
918 // Check for possible merge with preceeding ADD instruction.
919 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
920 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
922 // Jump to label or value in register.
923 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
924 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
925 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
926 else if (RetOpcode== X86::TCRETURNri64) {
927 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
929 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
930 // Delete the pseudo instruction TCRETURN.
932 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
933 (X86FI->getTCReturnAddrDelta() < 0)) {
934 // Add the return addr area delta back since we are not tail calling.
935 int delta = -1*X86FI->getTCReturnAddrDelta();
936 MBBI = prior(MBB.end());
937 // Check for possible merge with preceeding ADD instruction.
938 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
939 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
943 unsigned X86RegisterInfo::getRARegister() const {
945 return X86::RIP; // Should have dwarf #16
947 return X86::EIP; // Should have dwarf #8
950 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
951 return hasFP(MF) ? FramePtr : StackPtr;
954 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
956 // Calculate amount of bytes used for return address storing
957 int stackGrowth = (Is64Bit ? -8 : -4);
959 // Initial state of the frame pointer is esp+4.
960 MachineLocation Dst(MachineLocation::VirtualFP);
961 MachineLocation Src(StackPtr, stackGrowth);
962 Moves.push_back(MachineMove(0, Dst, Src));
964 // Add return address to move list
965 MachineLocation CSDst(StackPtr, stackGrowth);
966 MachineLocation CSSrc(getRARegister());
967 Moves.push_back(MachineMove(0, CSDst, CSSrc));
970 unsigned X86RegisterInfo::getEHExceptionRegister() const {
971 assert(0 && "What is the exception register");
975 unsigned X86RegisterInfo::getEHHandlerRegister() const {
976 assert(0 && "What is the exception handler register");
981 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
982 switch (VT.getSimpleVT()) {
988 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
990 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
992 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
994 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1000 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1002 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1004 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1006 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1008 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1010 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1012 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1014 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1016 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1018 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1020 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1022 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1024 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1026 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1028 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1030 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1036 default: return Reg;
1037 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1039 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1041 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1043 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1045 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1047 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1049 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1051 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1053 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1055 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1057 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1059 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1061 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1063 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1065 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1067 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1072 default: return Reg;
1073 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1075 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1077 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1079 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1081 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1083 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1085 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1087 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1089 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1091 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1093 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1095 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1097 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1099 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1101 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1103 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1108 default: return Reg;
1109 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1111 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1113 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1115 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1117 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1119 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1121 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1123 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1125 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1127 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1129 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1131 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1133 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1135 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1137 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1139 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1148 #include "X86GenRegisterInfo.inc"
1151 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1153 MSAC() : MachineFunctionPass(&ID) {}
1155 virtual bool runOnMachineFunction(MachineFunction &MF) {
1156 MachineFrameInfo *FFI = MF.getFrameInfo();
1157 MachineRegisterInfo &RI = MF.getRegInfo();
1159 // Calculate max stack alignment of all already allocated stack objects.
1160 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1162 // Be over-conservative: scan over all vreg defs and find, whether vector
1163 // registers are used. If yes - there is probability, that vector register
1164 // will be spilled and thus stack needs to be aligned properly.
1165 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1166 RegNum < RI.getLastVirtReg(); ++RegNum)
1167 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1169 FFI->setMaxAlignment(MaxAlign);
1174 virtual const char *getPassName() const {
1175 return "X86 Maximal Stack Alignment Calculator";
1183 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }