1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/Target/TargetAsmInfo.h"
30 #include "llvm/Target/TargetFrameInfo.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/ADT/BitVector.h"
36 #include "llvm/ADT/STLExtras.h"
41 NoFusing("disable-spill-fusing",
42 cl::desc("Disable fusing of spill code into instructions"));
44 PrintFailedFusing("print-failed-fuse-candidates",
45 cl::desc("Print instructions that the allocator wants to"
46 " fuse, but the X86 backend currently can't"),
50 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
51 const TargetInstrInfo &tii)
52 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
54 // Cache some information.
55 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
56 Is64Bit = Subtarget->is64Bit();
67 SmallVector<unsigned,16> AmbEntries;
68 static const unsigned OpTbl2Addr[][2] = {
69 { X86::ADC32ri, X86::ADC32mi },
70 { X86::ADC32ri8, X86::ADC32mi8 },
71 { X86::ADC32rr, X86::ADC32mr },
72 { X86::ADC64ri32, X86::ADC64mi32 },
73 { X86::ADC64ri8, X86::ADC64mi8 },
74 { X86::ADC64rr, X86::ADC64mr },
75 { X86::ADD16ri, X86::ADD16mi },
76 { X86::ADD16ri8, X86::ADD16mi8 },
77 { X86::ADD16rr, X86::ADD16mr },
78 { X86::ADD32ri, X86::ADD32mi },
79 { X86::ADD32ri8, X86::ADD32mi8 },
80 { X86::ADD32rr, X86::ADD32mr },
81 { X86::ADD64ri32, X86::ADD64mi32 },
82 { X86::ADD64ri8, X86::ADD64mi8 },
83 { X86::ADD64rr, X86::ADD64mr },
84 { X86::ADD8ri, X86::ADD8mi },
85 { X86::ADD8rr, X86::ADD8mr },
86 { X86::AND16ri, X86::AND16mi },
87 { X86::AND16ri8, X86::AND16mi8 },
88 { X86::AND16rr, X86::AND16mr },
89 { X86::AND32ri, X86::AND32mi },
90 { X86::AND32ri8, X86::AND32mi8 },
91 { X86::AND32rr, X86::AND32mr },
92 { X86::AND64ri32, X86::AND64mi32 },
93 { X86::AND64ri8, X86::AND64mi8 },
94 { X86::AND64rr, X86::AND64mr },
95 { X86::AND8ri, X86::AND8mi },
96 { X86::AND8rr, X86::AND8mr },
97 { X86::DEC16r, X86::DEC16m },
98 { X86::DEC32r, X86::DEC32m },
99 { X86::DEC64_16r, X86::DEC16m },
100 { X86::DEC64_32r, X86::DEC32m },
101 { X86::DEC64r, X86::DEC64m },
102 { X86::DEC8r, X86::DEC8m },
103 { X86::INC16r, X86::INC16m },
104 { X86::INC32r, X86::INC32m },
105 { X86::INC64_16r, X86::INC16m },
106 { X86::INC64_32r, X86::INC32m },
107 { X86::INC64r, X86::INC64m },
108 { X86::INC8r, X86::INC8m },
109 { X86::NEG16r, X86::NEG16m },
110 { X86::NEG32r, X86::NEG32m },
111 { X86::NEG64r, X86::NEG64m },
112 { X86::NEG8r, X86::NEG8m },
113 { X86::NOT16r, X86::NOT16m },
114 { X86::NOT32r, X86::NOT32m },
115 { X86::NOT64r, X86::NOT64m },
116 { X86::NOT8r, X86::NOT8m },
117 { X86::OR16ri, X86::OR16mi },
118 { X86::OR16ri8, X86::OR16mi8 },
119 { X86::OR16rr, X86::OR16mr },
120 { X86::OR32ri, X86::OR32mi },
121 { X86::OR32ri8, X86::OR32mi8 },
122 { X86::OR32rr, X86::OR32mr },
123 { X86::OR64ri32, X86::OR64mi32 },
124 { X86::OR64ri8, X86::OR64mi8 },
125 { X86::OR64rr, X86::OR64mr },
126 { X86::OR8ri, X86::OR8mi },
127 { X86::OR8rr, X86::OR8mr },
128 { X86::ROL16r1, X86::ROL16m1 },
129 { X86::ROL16rCL, X86::ROL16mCL },
130 { X86::ROL16ri, X86::ROL16mi },
131 { X86::ROL32r1, X86::ROL32m1 },
132 { X86::ROL32rCL, X86::ROL32mCL },
133 { X86::ROL32ri, X86::ROL32mi },
134 { X86::ROL64r1, X86::ROL64m1 },
135 { X86::ROL64rCL, X86::ROL64mCL },
136 { X86::ROL64ri, X86::ROL64mi },
137 { X86::ROL8r1, X86::ROL8m1 },
138 { X86::ROL8rCL, X86::ROL8mCL },
139 { X86::ROL8ri, X86::ROL8mi },
140 { X86::ROR16r1, X86::ROR16m1 },
141 { X86::ROR16rCL, X86::ROR16mCL },
142 { X86::ROR16ri, X86::ROR16mi },
143 { X86::ROR32r1, X86::ROR32m1 },
144 { X86::ROR32rCL, X86::ROR32mCL },
145 { X86::ROR32ri, X86::ROR32mi },
146 { X86::ROR64r1, X86::ROR64m1 },
147 { X86::ROR64rCL, X86::ROR64mCL },
148 { X86::ROR64ri, X86::ROR64mi },
149 { X86::ROR8r1, X86::ROR8m1 },
150 { X86::ROR8rCL, X86::ROR8mCL },
151 { X86::ROR8ri, X86::ROR8mi },
152 { X86::SAR16r1, X86::SAR16m1 },
153 { X86::SAR16rCL, X86::SAR16mCL },
154 { X86::SAR16ri, X86::SAR16mi },
155 { X86::SAR32r1, X86::SAR32m1 },
156 { X86::SAR32rCL, X86::SAR32mCL },
157 { X86::SAR32ri, X86::SAR32mi },
158 { X86::SAR64r1, X86::SAR64m1 },
159 { X86::SAR64rCL, X86::SAR64mCL },
160 { X86::SAR64ri, X86::SAR64mi },
161 { X86::SAR8r1, X86::SAR8m1 },
162 { X86::SAR8rCL, X86::SAR8mCL },
163 { X86::SAR8ri, X86::SAR8mi },
164 { X86::SBB32ri, X86::SBB32mi },
165 { X86::SBB32ri8, X86::SBB32mi8 },
166 { X86::SBB32rr, X86::SBB32mr },
167 { X86::SBB64ri32, X86::SBB64mi32 },
168 { X86::SBB64ri8, X86::SBB64mi8 },
169 { X86::SBB64rr, X86::SBB64mr },
170 { X86::SHL16r1, X86::SHL16m1 },
171 { X86::SHL16rCL, X86::SHL16mCL },
172 { X86::SHL16ri, X86::SHL16mi },
173 { X86::SHL32r1, X86::SHL32m1 },
174 { X86::SHL32rCL, X86::SHL32mCL },
175 { X86::SHL32ri, X86::SHL32mi },
176 { X86::SHL64r1, X86::SHL64m1 },
177 { X86::SHL64rCL, X86::SHL64mCL },
178 { X86::SHL64ri, X86::SHL64mi },
179 { X86::SHL8r1, X86::SHL8m1 },
180 { X86::SHL8rCL, X86::SHL8mCL },
181 { X86::SHL8ri, X86::SHL8mi },
182 { X86::SHLD16rrCL, X86::SHLD16mrCL },
183 { X86::SHLD16rri8, X86::SHLD16mri8 },
184 { X86::SHLD32rrCL, X86::SHLD32mrCL },
185 { X86::SHLD32rri8, X86::SHLD32mri8 },
186 { X86::SHLD64rrCL, X86::SHLD64mrCL },
187 { X86::SHLD64rri8, X86::SHLD64mri8 },
188 { X86::SHR16r1, X86::SHR16m1 },
189 { X86::SHR16rCL, X86::SHR16mCL },
190 { X86::SHR16ri, X86::SHR16mi },
191 { X86::SHR32r1, X86::SHR32m1 },
192 { X86::SHR32rCL, X86::SHR32mCL },
193 { X86::SHR32ri, X86::SHR32mi },
194 { X86::SHR64r1, X86::SHR64m1 },
195 { X86::SHR64rCL, X86::SHR64mCL },
196 { X86::SHR64ri, X86::SHR64mi },
197 { X86::SHR8r1, X86::SHR8m1 },
198 { X86::SHR8rCL, X86::SHR8mCL },
199 { X86::SHR8ri, X86::SHR8mi },
200 { X86::SHRD16rrCL, X86::SHRD16mrCL },
201 { X86::SHRD16rri8, X86::SHRD16mri8 },
202 { X86::SHRD32rrCL, X86::SHRD32mrCL },
203 { X86::SHRD32rri8, X86::SHRD32mri8 },
204 { X86::SHRD64rrCL, X86::SHRD64mrCL },
205 { X86::SHRD64rri8, X86::SHRD64mri8 },
206 { X86::SUB16ri, X86::SUB16mi },
207 { X86::SUB16ri8, X86::SUB16mi8 },
208 { X86::SUB16rr, X86::SUB16mr },
209 { X86::SUB32ri, X86::SUB32mi },
210 { X86::SUB32ri8, X86::SUB32mi8 },
211 { X86::SUB32rr, X86::SUB32mr },
212 { X86::SUB64ri32, X86::SUB64mi32 },
213 { X86::SUB64ri8, X86::SUB64mi8 },
214 { X86::SUB64rr, X86::SUB64mr },
215 { X86::SUB8ri, X86::SUB8mi },
216 { X86::SUB8rr, X86::SUB8mr },
217 { X86::XOR16ri, X86::XOR16mi },
218 { X86::XOR16ri8, X86::XOR16mi8 },
219 { X86::XOR16rr, X86::XOR16mr },
220 { X86::XOR32ri, X86::XOR32mi },
221 { X86::XOR32ri8, X86::XOR32mi8 },
222 { X86::XOR32rr, X86::XOR32mr },
223 { X86::XOR64ri32, X86::XOR64mi32 },
224 { X86::XOR64ri8, X86::XOR64mi8 },
225 { X86::XOR64rr, X86::XOR64mr },
226 { X86::XOR8ri, X86::XOR8mi },
227 { X86::XOR8rr, X86::XOR8mr }
230 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
231 unsigned RegOp = OpTbl2Addr[i][0];
232 unsigned MemOp = OpTbl2Addr[i][1];
233 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp)))
234 assert(false && "Duplicated entries?");
235 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, RegOp)))
236 AmbEntries.push_back(MemOp);
239 static const unsigned OpTbl0[][2] = {
240 { X86::CALL32r, X86::CALL32m },
241 { X86::CALL64r, X86::CALL64m },
242 { X86::CMP16ri, X86::CMP16mi },
243 { X86::CMP16ri8, X86::CMP16mi8 },
244 { X86::CMP32ri, X86::CMP32mi },
245 { X86::CMP32ri8, X86::CMP32mi8 },
246 { X86::CMP64ri32, X86::CMP64mi32 },
247 { X86::CMP64ri8, X86::CMP64mi8 },
248 { X86::CMP8ri, X86::CMP8mi },
249 { X86::DIV16r, X86::DIV16m },
250 { X86::DIV32r, X86::DIV32m },
251 { X86::DIV64r, X86::DIV64m },
252 { X86::DIV8r, X86::DIV8m },
253 { X86::FsMOVAPDrr, X86::MOVSDmr },
254 { X86::FsMOVAPSrr, X86::MOVSSmr },
255 { X86::IDIV16r, X86::IDIV16m },
256 { X86::IDIV32r, X86::IDIV32m },
257 { X86::IDIV64r, X86::IDIV64m },
258 { X86::IDIV8r, X86::IDIV8m },
259 { X86::IMUL16r, X86::IMUL16m },
260 { X86::IMUL32r, X86::IMUL32m },
261 { X86::IMUL64r, X86::IMUL64m },
262 { X86::IMUL8r, X86::IMUL8m },
263 { X86::JMP32r, X86::JMP32m },
264 { X86::JMP64r, X86::JMP64m },
265 { X86::MOV16ri, X86::MOV16mi },
266 { X86::MOV16rr, X86::MOV16mr },
267 { X86::MOV32ri, X86::MOV32mi },
268 { X86::MOV32rr, X86::MOV32mr },
269 { X86::MOV64ri32, X86::MOV64mi32 },
270 { X86::MOV64rr, X86::MOV64mr },
271 { X86::MOV8ri, X86::MOV8mi },
272 { X86::MOV8rr, X86::MOV8mr },
273 { X86::MOVAPDrr, X86::MOVAPDmr },
274 { X86::MOVAPSrr, X86::MOVAPSmr },
275 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
276 { X86::MOVPQIto64rr,X86::MOVPQIto64mr },
277 { X86::MOVPS2SSrr, X86::MOVPS2SSmr },
278 { X86::MOVSDrr, X86::MOVSDmr },
279 { X86::MOVSDto64rr, X86::MOVSDto64mr },
280 { X86::MOVSS2DIrr, X86::MOVSS2DImr },
281 { X86::MOVSSrr, X86::MOVSSmr },
282 { X86::MOVUPDrr, X86::MOVUPDmr },
283 { X86::MOVUPSrr, X86::MOVUPSmr },
284 { X86::MUL16r, X86::MUL16m },
285 { X86::MUL32r, X86::MUL32m },
286 { X86::MUL64r, X86::MUL64m },
287 { X86::MUL8r, X86::MUL8m },
288 { X86::SETAEr, X86::SETAEm },
289 { X86::SETAr, X86::SETAm },
290 { X86::SETBEr, X86::SETBEm },
291 { X86::SETBr, X86::SETBm },
292 { X86::SETEr, X86::SETEm },
293 { X86::SETGEr, X86::SETGEm },
294 { X86::SETGr, X86::SETGm },
295 { X86::SETLEr, X86::SETLEm },
296 { X86::SETLr, X86::SETLm },
297 { X86::SETNEr, X86::SETNEm },
298 { X86::SETNPr, X86::SETNPm },
299 { X86::SETNSr, X86::SETNSm },
300 { X86::SETPr, X86::SETPm },
301 { X86::SETSr, X86::SETSm },
302 { X86::TAILJMPr, X86::TAILJMPm },
303 { X86::TEST16ri, X86::TEST16mi },
304 { X86::TEST32ri, X86::TEST32mi },
305 { X86::TEST64ri32, X86::TEST64mi32 },
306 { X86::TEST8ri, X86::TEST8mi },
307 { X86::XCHG16rr, X86::XCHG16mr },
308 { X86::XCHG32rr, X86::XCHG32mr },
309 { X86::XCHG64rr, X86::XCHG64mr },
310 { X86::XCHG8rr, X86::XCHG8mr }
313 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
314 unsigned RegOp = OpTbl0[i][0];
315 unsigned MemOp = OpTbl0[i][1];
316 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp)))
317 assert(false && "Duplicated entries?");
318 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, RegOp)))
319 AmbEntries.push_back(MemOp);
322 static const unsigned OpTbl1[][2] = {
323 { X86::CMP16rr, X86::CMP16rm },
324 { X86::CMP32rr, X86::CMP32rm },
325 { X86::CMP64rr, X86::CMP64rm },
326 { X86::CMP8rr, X86::CMP8rm },
327 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
328 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
329 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
330 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
331 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
332 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
333 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
334 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
335 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
336 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
337 { X86::FsMOVAPDrr, X86::MOVSDrm },
338 { X86::FsMOVAPSrr, X86::MOVSSrm },
339 { X86::IMUL16rri, X86::IMUL16rmi },
340 { X86::IMUL16rri8, X86::IMUL16rmi8 },
341 { X86::IMUL32rri, X86::IMUL32rmi },
342 { X86::IMUL32rri8, X86::IMUL32rmi8 },
343 { X86::IMUL64rri32, X86::IMUL64rmi32 },
344 { X86::IMUL64rri8, X86::IMUL64rmi8 },
345 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
346 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
347 { X86::Int_COMISDrr, X86::Int_COMISDrm },
348 { X86::Int_COMISSrr, X86::Int_COMISSrm },
349 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
350 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
351 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
352 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
353 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
354 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
355 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
356 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
357 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
358 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
359 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
360 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
361 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
362 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
363 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
364 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
365 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
366 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
367 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
368 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
369 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
370 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
371 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
372 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
373 { X86::MOV16rr, X86::MOV16rm },
374 { X86::MOV32rr, X86::MOV32rm },
375 { X86::MOV64rr, X86::MOV64rm },
376 { X86::MOV64toPQIrr, X86::MOV64toPQIrm },
377 { X86::MOV64toSDrr, X86::MOV64toSDrm },
378 { X86::MOV8rr, X86::MOV8rm },
379 { X86::MOVAPDrr, X86::MOVAPDrm },
380 { X86::MOVAPSrr, X86::MOVAPSrm },
381 { X86::MOVDDUPrr, X86::MOVDDUPrm },
382 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
383 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
384 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
385 { X86::MOVSDrr, X86::MOVSDrm },
386 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
387 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
388 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
389 { X86::MOVSSrr, X86::MOVSSrm },
390 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
391 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
392 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
393 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
394 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
395 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
396 { X86::MOVUPDrr, X86::MOVUPDrm },
397 { X86::MOVUPSrr, X86::MOVUPSrm },
398 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
399 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
400 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
401 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
402 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
403 { X86::PSHUFDri, X86::PSHUFDmi },
404 { X86::PSHUFHWri, X86::PSHUFHWmi },
405 { X86::PSHUFLWri, X86::PSHUFLWmi },
406 { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
407 { X86::RCPPSr, X86::RCPPSm },
408 { X86::RCPPSr_Int, X86::RCPPSm_Int },
409 { X86::RSQRTPSr, X86::RSQRTPSm },
410 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
411 { X86::RSQRTSSr, X86::RSQRTSSm },
412 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
413 { X86::SQRTPDr, X86::SQRTPDm },
414 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
415 { X86::SQRTPSr, X86::SQRTPSm },
416 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
417 { X86::SQRTSDr, X86::SQRTSDm },
418 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
419 { X86::SQRTSSr, X86::SQRTSSm },
420 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
421 { X86::TEST16rr, X86::TEST16rm },
422 { X86::TEST32rr, X86::TEST32rm },
423 { X86::TEST64rr, X86::TEST64rm },
424 { X86::TEST8rr, X86::TEST8rm },
425 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
426 { X86::UCOMISDrr, X86::UCOMISDrm },
427 { X86::UCOMISSrr, X86::UCOMISSrm },
428 { X86::XCHG16rr, X86::XCHG16rm },
429 { X86::XCHG32rr, X86::XCHG32rm },
430 { X86::XCHG64rr, X86::XCHG64rm },
431 { X86::XCHG8rr, X86::XCHG8rm }
434 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
435 unsigned RegOp = OpTbl1[i][0];
436 unsigned MemOp = OpTbl1[i][1];
437 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp)))
438 assert(false && "Duplicated entries?");
439 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, RegOp)))
440 AmbEntries.push_back(MemOp);
443 static const unsigned OpTbl2[][2] = {
444 { X86::ADC32rr, X86::ADC32rm },
445 { X86::ADC64rr, X86::ADC64rm },
446 { X86::ADD16rr, X86::ADD16rm },
447 { X86::ADD32rr, X86::ADD32rm },
448 { X86::ADD64rr, X86::ADD64rm },
449 { X86::ADD8rr, X86::ADD8rm },
450 { X86::ADDPDrr, X86::ADDPDrm },
451 { X86::ADDPSrr, X86::ADDPSrm },
452 { X86::ADDSDrr, X86::ADDSDrm },
453 { X86::ADDSSrr, X86::ADDSSrm },
454 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
455 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
456 { X86::AND16rr, X86::AND16rm },
457 { X86::AND32rr, X86::AND32rm },
458 { X86::AND64rr, X86::AND64rm },
459 { X86::AND8rr, X86::AND8rm },
460 { X86::ANDNPDrr, X86::ANDNPDrm },
461 { X86::ANDNPSrr, X86::ANDNPSrm },
462 { X86::ANDPDrr, X86::ANDPDrm },
463 { X86::ANDPSrr, X86::ANDPSrm },
464 { X86::CMOVA16rr, X86::CMOVA16rm },
465 { X86::CMOVA32rr, X86::CMOVA32rm },
466 { X86::CMOVA64rr, X86::CMOVA64rm },
467 { X86::CMOVAE16rr, X86::CMOVAE16rm },
468 { X86::CMOVAE32rr, X86::CMOVAE32rm },
469 { X86::CMOVAE64rr, X86::CMOVAE64rm },
470 { X86::CMOVB16rr, X86::CMOVB16rm },
471 { X86::CMOVB32rr, X86::CMOVB32rm },
472 { X86::CMOVB64rr, X86::CMOVB64rm },
473 { X86::CMOVBE16rr, X86::CMOVBE16rm },
474 { X86::CMOVBE32rr, X86::CMOVBE32rm },
475 { X86::CMOVBE64rr, X86::CMOVBE64rm },
476 { X86::CMOVE16rr, X86::CMOVE16rm },
477 { X86::CMOVE32rr, X86::CMOVE32rm },
478 { X86::CMOVE64rr, X86::CMOVE64rm },
479 { X86::CMOVG16rr, X86::CMOVG16rm },
480 { X86::CMOVG32rr, X86::CMOVG32rm },
481 { X86::CMOVG64rr, X86::CMOVG64rm },
482 { X86::CMOVGE16rr, X86::CMOVGE16rm },
483 { X86::CMOVGE32rr, X86::CMOVGE32rm },
484 { X86::CMOVGE64rr, X86::CMOVGE64rm },
485 { X86::CMOVL16rr, X86::CMOVL16rm },
486 { X86::CMOVL32rr, X86::CMOVL32rm },
487 { X86::CMOVL64rr, X86::CMOVL64rm },
488 { X86::CMOVLE16rr, X86::CMOVLE16rm },
489 { X86::CMOVLE32rr, X86::CMOVLE32rm },
490 { X86::CMOVLE64rr, X86::CMOVLE64rm },
491 { X86::CMOVNE16rr, X86::CMOVNE16rm },
492 { X86::CMOVNE32rr, X86::CMOVNE32rm },
493 { X86::CMOVNE64rr, X86::CMOVNE64rm },
494 { X86::CMOVNP16rr, X86::CMOVNP16rm },
495 { X86::CMOVNP32rr, X86::CMOVNP32rm },
496 { X86::CMOVNP64rr, X86::CMOVNP64rm },
497 { X86::CMOVNS16rr, X86::CMOVNS16rm },
498 { X86::CMOVNS32rr, X86::CMOVNS32rm },
499 { X86::CMOVNS64rr, X86::CMOVNS64rm },
500 { X86::CMOVP16rr, X86::CMOVP16rm },
501 { X86::CMOVP32rr, X86::CMOVP32rm },
502 { X86::CMOVP64rr, X86::CMOVP64rm },
503 { X86::CMOVS16rr, X86::CMOVS16rm },
504 { X86::CMOVS32rr, X86::CMOVS32rm },
505 { X86::CMOVS64rr, X86::CMOVS64rm },
506 { X86::CMPPDrri, X86::CMPPDrmi },
507 { X86::CMPPSrri, X86::CMPPSrmi },
508 { X86::CMPSDrr, X86::CMPSDrm },
509 { X86::CMPSSrr, X86::CMPSSrm },
510 { X86::DIVPDrr, X86::DIVPDrm },
511 { X86::DIVPSrr, X86::DIVPSrm },
512 { X86::DIVSDrr, X86::DIVSDrm },
513 { X86::DIVSSrr, X86::DIVSSrm },
514 { X86::HADDPDrr, X86::HADDPDrm },
515 { X86::HADDPSrr, X86::HADDPSrm },
516 { X86::HSUBPDrr, X86::HSUBPDrm },
517 { X86::HSUBPSrr, X86::HSUBPSrm },
518 { X86::IMUL16rr, X86::IMUL16rm },
519 { X86::IMUL32rr, X86::IMUL32rm },
520 { X86::IMUL64rr, X86::IMUL64rm },
521 { X86::MAXPDrr, X86::MAXPDrm },
522 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
523 { X86::MAXPSrr, X86::MAXPSrm },
524 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
525 { X86::MAXSDrr, X86::MAXSDrm },
526 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
527 { X86::MAXSSrr, X86::MAXSSrm },
528 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
529 { X86::MINPDrr, X86::MINPDrm },
530 { X86::MINPDrr_Int, X86::MINPDrm_Int },
531 { X86::MINPSrr, X86::MINPSrm },
532 { X86::MINPSrr_Int, X86::MINPSrm_Int },
533 { X86::MINSDrr, X86::MINSDrm },
534 { X86::MINSDrr_Int, X86::MINSDrm_Int },
535 { X86::MINSSrr, X86::MINSSrm },
536 { X86::MINSSrr_Int, X86::MINSSrm_Int },
537 { X86::MULPDrr, X86::MULPDrm },
538 { X86::MULPSrr, X86::MULPSrm },
539 { X86::MULSDrr, X86::MULSDrm },
540 { X86::MULSSrr, X86::MULSSrm },
541 { X86::OR16rr, X86::OR16rm },
542 { X86::OR32rr, X86::OR32rm },
543 { X86::OR64rr, X86::OR64rm },
544 { X86::OR8rr, X86::OR8rm },
545 { X86::ORPDrr, X86::ORPDrm },
546 { X86::ORPSrr, X86::ORPSrm },
547 { X86::PACKSSDWrr, X86::PACKSSDWrm },
548 { X86::PACKSSWBrr, X86::PACKSSWBrm },
549 { X86::PACKUSWBrr, X86::PACKUSWBrm },
550 { X86::PADDBrr, X86::PADDBrm },
551 { X86::PADDDrr, X86::PADDDrm },
552 { X86::PADDQrr, X86::PADDQrm },
553 { X86::PADDSBrr, X86::PADDSBrm },
554 { X86::PADDSWrr, X86::PADDSWrm },
555 { X86::PADDWrr, X86::PADDWrm },
556 { X86::PANDNrr, X86::PANDNrm },
557 { X86::PANDrr, X86::PANDrm },
558 { X86::PAVGBrr, X86::PAVGBrm },
559 { X86::PAVGWrr, X86::PAVGWrm },
560 { X86::PCMPEQBrr, X86::PCMPEQBrm },
561 { X86::PCMPEQDrr, X86::PCMPEQDrm },
562 { X86::PCMPEQWrr, X86::PCMPEQWrm },
563 { X86::PCMPGTBrr, X86::PCMPGTBrm },
564 { X86::PCMPGTDrr, X86::PCMPGTDrm },
565 { X86::PCMPGTWrr, X86::PCMPGTWrm },
566 { X86::PINSRWrri, X86::PINSRWrmi },
567 { X86::PMADDWDrr, X86::PMADDWDrm },
568 { X86::PMAXSWrr, X86::PMAXSWrm },
569 { X86::PMAXUBrr, X86::PMAXUBrm },
570 { X86::PMINSWrr, X86::PMINSWrm },
571 { X86::PMINUBrr, X86::PMINUBrm },
572 { X86::PMULHUWrr, X86::PMULHUWrm },
573 { X86::PMULHWrr, X86::PMULHWrm },
574 { X86::PMULLWrr, X86::PMULLWrm },
575 { X86::PMULUDQrr, X86::PMULUDQrm },
576 { X86::PORrr, X86::PORrm },
577 { X86::PSADBWrr, X86::PSADBWrm },
578 { X86::PSLLDrr, X86::PSLLDrm },
579 { X86::PSLLQrr, X86::PSLLQrm },
580 { X86::PSLLWrr, X86::PSLLWrm },
581 { X86::PSRADrr, X86::PSRADrm },
582 { X86::PSRAWrr, X86::PSRAWrm },
583 { X86::PSRLDrr, X86::PSRLDrm },
584 { X86::PSRLQrr, X86::PSRLQrm },
585 { X86::PSRLWrr, X86::PSRLWrm },
586 { X86::PSUBBrr, X86::PSUBBrm },
587 { X86::PSUBDrr, X86::PSUBDrm },
588 { X86::PSUBSBrr, X86::PSUBSBrm },
589 { X86::PSUBSWrr, X86::PSUBSWrm },
590 { X86::PSUBWrr, X86::PSUBWrm },
591 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
592 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
593 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
594 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
595 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
596 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
597 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
598 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
599 { X86::PXORrr, X86::PXORrm },
600 { X86::SBB32rr, X86::SBB32rm },
601 { X86::SBB64rr, X86::SBB64rm },
602 { X86::SHUFPDrri, X86::SHUFPDrmi },
603 { X86::SHUFPSrri, X86::SHUFPSrmi },
604 { X86::SUB16rr, X86::SUB16rm },
605 { X86::SUB32rr, X86::SUB32rm },
606 { X86::SUB64rr, X86::SUB64rm },
607 { X86::SUB8rr, X86::SUB8rm },
608 { X86::SUBPDrr, X86::SUBPDrm },
609 { X86::SUBPSrr, X86::SUBPSrm },
610 { X86::SUBSDrr, X86::SUBSDrm },
611 { X86::SUBSSrr, X86::SUBSSrm },
612 // FIXME: TEST*rr -> swapped operand of TEST*mr.
613 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
614 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
615 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
616 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
617 { X86::XOR16rr, X86::XOR16rm },
618 { X86::XOR32rr, X86::XOR32rm },
619 { X86::XOR64rr, X86::XOR64rm },
620 { X86::XOR8rr, X86::XOR8rm },
621 { X86::XORPDrr, X86::XORPDrm },
622 { X86::XORPSrr, X86::XORPSrm }
625 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
626 unsigned RegOp = OpTbl2[i][0];
627 unsigned MemOp = OpTbl2[i][1];
628 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp)))
629 assert(false && "Duplicated entries?");
630 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, RegOp)))
631 AmbEntries.push_back(MemOp);
634 // Remove ambiguous entries.
635 for (unsigned i = 0, e = AmbEntries.size(); i != e; ++i)
636 MemOp2RegOpTable.erase((unsigned*)AmbEntries[i]);
639 // getX86RegNum - This function maps LLVM register identifiers to their X86
640 // specific numbering, which is used in various places encoding instructions.
642 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
644 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
645 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
646 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
647 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
648 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
650 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
652 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
654 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
657 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
659 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
661 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
663 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
665 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
667 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
669 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
671 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
674 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
675 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
676 return RegNo-X86::ST0;
678 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
679 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
680 return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM0);
681 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
682 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
683 return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM8);
686 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
687 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
692 bool X86RegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
693 MachineBasicBlock::iterator MI,
694 const std::vector<CalleeSavedInfo> &CSI) const {
698 MachineFunction &MF = *MBB.getParent();
699 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
700 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
701 unsigned Opc = Is64Bit ? X86::PUSH64r : X86::PUSH32r;
702 for (unsigned i = CSI.size(); i != 0; --i) {
703 unsigned Reg = CSI[i-1].getReg();
704 // Add the callee-saved register as live-in. It's killed at the spill.
706 BuildMI(MBB, MI, TII.get(Opc)).addReg(Reg);
711 bool X86RegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
712 MachineBasicBlock::iterator MI,
713 const std::vector<CalleeSavedInfo> &CSI) const {
717 unsigned Opc = Is64Bit ? X86::POP64r : X86::POP32r;
718 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
719 unsigned Reg = CSI[i].getReg();
720 BuildMI(MBB, MI, TII.get(Opc), Reg);
725 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
726 MachineBasicBlock::iterator MI,
727 unsigned SrcReg, int FrameIdx,
728 const TargetRegisterClass *RC) const {
730 if (RC == &X86::GR64RegClass) {
732 } else if (RC == &X86::GR32RegClass) {
734 } else if (RC == &X86::GR16RegClass) {
736 } else if (RC == &X86::GR8RegClass) {
738 } else if (RC == &X86::GR32_RegClass) {
740 } else if (RC == &X86::GR16_RegClass) {
742 } else if (RC == &X86::RFP80RegClass) {
743 Opc = X86::ST_FpP80m; // pops
744 } else if (RC == &X86::RFP64RegClass) {
746 } else if (RC == &X86::RFP32RegClass) {
748 } else if (RC == &X86::FR32RegClass) {
750 } else if (RC == &X86::FR64RegClass) {
752 } else if (RC == &X86::VR128RegClass) {
754 } else if (RC == &X86::VR64RegClass) {
755 Opc = X86::MMX_MOVQ64mr;
757 assert(0 && "Unknown regclass");
760 addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
761 .addReg(SrcReg, false, false, true);
764 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
765 MachineBasicBlock::iterator MI,
766 unsigned DestReg, int FrameIdx,
767 const TargetRegisterClass *RC) const{
769 if (RC == &X86::GR64RegClass) {
771 } else if (RC == &X86::GR32RegClass) {
773 } else if (RC == &X86::GR16RegClass) {
775 } else if (RC == &X86::GR8RegClass) {
777 } else if (RC == &X86::GR32_RegClass) {
779 } else if (RC == &X86::GR16_RegClass) {
781 } else if (RC == &X86::RFP80RegClass) {
783 } else if (RC == &X86::RFP64RegClass) {
785 } else if (RC == &X86::RFP32RegClass) {
787 } else if (RC == &X86::FR32RegClass) {
789 } else if (RC == &X86::FR64RegClass) {
791 } else if (RC == &X86::VR128RegClass) {
793 } else if (RC == &X86::VR64RegClass) {
794 Opc = X86::MMX_MOVQ64rm;
796 assert(0 && "Unknown regclass");
799 addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
802 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
803 MachineBasicBlock::iterator MI,
804 unsigned DestReg, unsigned SrcReg,
805 const TargetRegisterClass *DestRC,
806 const TargetRegisterClass *SrcRC) const {
807 if (DestRC != SrcRC) {
808 // Moving EFLAGS to / from another register requires a push and a pop.
809 if (SrcRC == &X86::CCRRegClass) {
810 assert(SrcReg == X86::EFLAGS);
811 if (DestRC == &X86::GR64RegClass) {
812 BuildMI(MBB, MI, TII.get(X86::PUSHFQ));
813 BuildMI(MBB, MI, TII.get(X86::POP64r), DestReg);
815 } else if (DestRC == &X86::GR32RegClass) {
816 BuildMI(MBB, MI, TII.get(X86::PUSHFD));
817 BuildMI(MBB, MI, TII.get(X86::POP32r), DestReg);
820 } else if (DestRC == &X86::CCRRegClass) {
821 assert(DestReg == X86::EFLAGS);
822 if (SrcRC == &X86::GR64RegClass) {
823 BuildMI(MBB, MI, TII.get(X86::PUSH64r)).addReg(SrcReg);
824 BuildMI(MBB, MI, TII.get(X86::POPFQ));
826 } else if (SrcRC == &X86::GR32RegClass) {
827 BuildMI(MBB, MI, TII.get(X86::PUSH32r)).addReg(SrcReg);
828 BuildMI(MBB, MI, TII.get(X86::POPFD));
832 cerr << "Not yet supported!";
837 if (DestRC == &X86::GR64RegClass) {
839 } else if (DestRC == &X86::GR32RegClass) {
841 } else if (DestRC == &X86::GR16RegClass) {
843 } else if (DestRC == &X86::GR8RegClass) {
845 } else if (DestRC == &X86::GR32_RegClass) {
847 } else if (DestRC == &X86::GR16_RegClass) {
849 } else if (DestRC == &X86::RFP32RegClass) {
850 Opc = X86::MOV_Fp3232;
851 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
852 Opc = X86::MOV_Fp6464;
853 } else if (DestRC == &X86::RFP80RegClass) {
854 Opc = X86::MOV_Fp8080;
855 } else if (DestRC == &X86::FR32RegClass) {
856 Opc = X86::FsMOVAPSrr;
857 } else if (DestRC == &X86::FR64RegClass) {
858 Opc = X86::FsMOVAPDrr;
859 } else if (DestRC == &X86::VR128RegClass) {
861 } else if (DestRC == &X86::VR64RegClass) {
862 Opc = X86::MMX_MOVQ64rr;
864 assert(0 && "Unknown regclass");
867 BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
870 const TargetRegisterClass *
871 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
872 if (RC == &X86::CCRRegClass)
874 return &X86::GR64RegClass;
876 return &X86::GR32RegClass;
880 void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
881 MachineBasicBlock::iterator I,
883 const MachineInstr *Orig) const {
884 // MOV32r0 etc. are implemented with xor which clobbers condition code.
885 // Re-materialize them as movri instructions to avoid side effects.
886 switch (Orig->getOpcode()) {
888 BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
891 BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
894 BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
897 BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
900 MachineInstr *MI = Orig->clone();
901 MI->getOperand(0).setReg(DestReg);
908 static const MachineInstrBuilder &FuseInstrAddOperand(MachineInstrBuilder &MIB,
909 MachineOperand &MO) {
911 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
912 else if (MO.isImmediate())
913 MIB = MIB.addImm(MO.getImm());
914 else if (MO.isFrameIndex())
915 MIB = MIB.addFrameIndex(MO.getFrameIndex());
916 else if (MO.isGlobalAddress())
917 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
918 else if (MO.isConstantPoolIndex())
919 MIB = MIB.addConstantPoolIndex(MO.getConstantPoolIndex(), MO.getOffset());
920 else if (MO.isJumpTableIndex())
921 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
922 else if (MO.isExternalSymbol())
923 MIB = MIB.addExternalSymbol(MO.getSymbolName());
925 assert(0 && "Unknown operand for FuseInst!");
930 static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
931 SmallVector<MachineOperand,4> &MOs,
932 MachineInstr *MI, const TargetInstrInfo &TII) {
933 unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
935 // Create the base instruction with the memory operand as the first part.
936 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
937 unsigned NumAddrOps = MOs.size();
938 for (unsigned i = 0; i != NumAddrOps; ++i)
939 MIB = FuseInstrAddOperand(MIB, MOs[i]);
940 if (NumAddrOps < 4) // FrameIndex only
941 MIB.addImm(1).addReg(0).addImm(0);
943 // Loop over the rest of the ri operands, converting them over.
944 for (unsigned i = 0; i != NumOps; ++i) {
945 MachineOperand &MO = MI->getOperand(i+2);
946 MIB = FuseInstrAddOperand(MIB, MO);
951 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
952 SmallVector<MachineOperand,4> &MOs,
953 MachineInstr *MI, const TargetInstrInfo &TII) {
954 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
956 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
957 MachineOperand &MO = MI->getOperand(i);
959 assert(MO.isRegister() && "Expected to fold into reg operand!");
960 unsigned NumAddrOps = MOs.size();
961 for (unsigned i = 0; i != NumAddrOps; ++i)
962 MIB = FuseInstrAddOperand(MIB, MOs[i]);
963 if (NumAddrOps < 4) // FrameIndex only
964 MIB.addImm(1).addReg(0).addImm(0);
966 MIB = FuseInstrAddOperand(MIB, MO);
972 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
973 SmallVector<MachineOperand,4> &MOs,
975 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
977 unsigned NumAddrOps = MOs.size();
978 for (unsigned i = 0; i != NumAddrOps; ++i)
979 MIB = FuseInstrAddOperand(MIB, MOs[i]);
980 if (NumAddrOps < 4) // FrameIndex only
981 MIB.addImm(1).addReg(0).addImm(0);
982 return MIB.addImm(0);
986 X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
987 SmallVector<MachineOperand,4> &MOs) const {
988 // Table (and size) to search
989 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
990 bool isTwoAddrFold = false;
991 unsigned NumOps = TII.getNumOperands(MI->getOpcode());
992 bool isTwoAddr = NumOps > 1 &&
993 MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
995 MachineInstr *NewMI = NULL;
996 // Folding a memory location into the two-address part of a two-address
997 // instruction is different than folding it other places. It requires
998 // replacing the *two* registers with the memory location.
999 if (isTwoAddr && NumOps >= 2 && i < 2 &&
1000 MI->getOperand(0).isRegister() &&
1001 MI->getOperand(1).isRegister() &&
1002 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
1003 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1004 isTwoAddrFold = true;
1005 } else if (i == 0) { // If operand 0
1006 if (MI->getOpcode() == X86::MOV16r0)
1007 NewMI = MakeM0Inst(TII, X86::MOV16mi, MOs, MI);
1008 else if (MI->getOpcode() == X86::MOV32r0)
1009 NewMI = MakeM0Inst(TII, X86::MOV32mi, MOs, MI);
1010 else if (MI->getOpcode() == X86::MOV64r0)
1011 NewMI = MakeM0Inst(TII, X86::MOV64mi32, MOs, MI);
1012 else if (MI->getOpcode() == X86::MOV8r0)
1013 NewMI = MakeM0Inst(TII, X86::MOV8mi, MOs, MI);
1015 NewMI->copyKillDeadInfo(MI);
1019 OpcodeTablePtr = &RegOp2MemOpTable0;
1020 } else if (i == 1) {
1021 OpcodeTablePtr = &RegOp2MemOpTable1;
1022 } else if (i == 2) {
1023 OpcodeTablePtr = &RegOp2MemOpTable2;
1026 // If table selected...
1027 if (OpcodeTablePtr) {
1028 // Find the Opcode to fuse
1029 DenseMap<unsigned*, unsigned>::iterator I =
1030 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
1031 if (I != OpcodeTablePtr->end()) {
1033 NewMI = FuseTwoAddrInst(I->second, MOs, MI, TII);
1035 NewMI = FuseInst(I->second, i, MOs, MI, TII);
1036 NewMI->copyKillDeadInfo(MI);
1042 if (PrintFailedFusing)
1043 cerr << "We failed to fuse ("
1044 << ((i == 1) ? "r" : "s") << "): " << *MI;
1049 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
1050 int FrameIndex) const {
1051 // Check switch flag
1052 if (NoFusing) return NULL;
1053 SmallVector<MachineOperand,4> MOs;
1054 MOs.push_back(MachineOperand::CreateFrameIndex(FrameIndex));
1055 return foldMemoryOperand(MI, OpNum, MOs);
1058 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
1059 MachineInstr *LoadMI) const {
1060 // Check switch flag
1061 if (NoFusing) return NULL;
1062 SmallVector<MachineOperand,4> MOs;
1063 unsigned NumOps = TII.getNumOperands(LoadMI->getOpcode());
1064 for (unsigned i = NumOps - 4; i != NumOps; ++i)
1065 MOs.push_back(LoadMI->getOperand(i));
1066 return foldMemoryOperand(MI, OpNum, MOs);
1070 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
1071 static const unsigned CalleeSavedRegs32Bit[] = {
1072 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
1075 static const unsigned CalleeSavedRegs32EHRet[] = {
1076 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
1079 static const unsigned CalleeSavedRegs64Bit[] = {
1080 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1084 return CalleeSavedRegs64Bit;
1087 MachineFrameInfo *MFI = MF->getFrameInfo();
1088 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1089 if (MMI && MMI->callsEHReturn())
1090 return CalleeSavedRegs32EHRet;
1092 return CalleeSavedRegs32Bit;
1096 const TargetRegisterClass* const*
1097 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
1098 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
1099 &X86::GR32RegClass, &X86::GR32RegClass,
1100 &X86::GR32RegClass, &X86::GR32RegClass, 0
1102 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
1103 &X86::GR32RegClass, &X86::GR32RegClass,
1104 &X86::GR32RegClass, &X86::GR32RegClass,
1105 &X86::GR32RegClass, &X86::GR32RegClass, 0
1107 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
1108 &X86::GR64RegClass, &X86::GR64RegClass,
1109 &X86::GR64RegClass, &X86::GR64RegClass,
1110 &X86::GR64RegClass, &X86::GR64RegClass, 0
1114 return CalleeSavedRegClasses64Bit;
1117 MachineFrameInfo *MFI = MF->getFrameInfo();
1118 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1119 if (MMI && MMI->callsEHReturn())
1120 return CalleeSavedRegClasses32EHRet;
1122 return CalleeSavedRegClasses32Bit;
1127 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
1128 BitVector Reserved(getNumRegs());
1129 Reserved.set(X86::RSP);
1130 Reserved.set(X86::ESP);
1131 Reserved.set(X86::SP);
1132 Reserved.set(X86::SPL);
1134 Reserved.set(X86::RBP);
1135 Reserved.set(X86::EBP);
1136 Reserved.set(X86::BP);
1137 Reserved.set(X86::BPL);
1142 //===----------------------------------------------------------------------===//
1143 // Stack Frame Processing methods
1144 //===----------------------------------------------------------------------===//
1146 // hasFP - Return true if the specified function should have a dedicated frame
1147 // pointer register. This is true if the function has variable sized allocas or
1148 // if frame pointer elimination is disabled.
1150 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
1151 MachineFrameInfo *MFI = MF.getFrameInfo();
1152 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1154 return (NoFramePointerElim ||
1155 MFI->hasVarSizedObjects() ||
1156 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
1157 (MMI && MMI->callsUnwindInit()));
1160 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
1161 return !MF.getFrameInfo()->hasVarSizedObjects();
1164 void X86RegisterInfo::
1165 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1166 MachineBasicBlock::iterator I) const {
1167 if (!hasReservedCallFrame(MF)) {
1168 // If the stack pointer can be changed after prologue, turn the
1169 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1170 // adjcallstackdown instruction into 'add ESP, <amt>'
1171 // TODO: consider using push / pop instead of sub + store / add
1172 MachineInstr *Old = I;
1173 uint64_t Amount = Old->getOperand(0).getImm();
1175 // We need to keep the stack aligned properly. To do this, we round the
1176 // amount of space needed for the outgoing arguments up to the next
1177 // alignment boundary.
1178 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1179 Amount = (Amount+Align-1)/Align*Align;
1181 MachineInstr *New = 0;
1182 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
1183 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
1184 .addReg(StackPtr).addImm(Amount);
1186 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
1187 // factor out the amount the callee already popped.
1188 uint64_t CalleeAmt = Old->getOperand(1).getImm();
1189 Amount -= CalleeAmt;
1191 unsigned Opc = (Amount < 128) ?
1192 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1193 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1194 New = BuildMI(TII.get(Opc), StackPtr)
1195 .addReg(StackPtr).addImm(Amount);
1199 // Replace the pseudo instruction with a new instruction...
1200 if (New) MBB.insert(I, New);
1202 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
1203 // If we are performing frame pointer elimination and if the callee pops
1204 // something off the stack pointer, add it back. We do this until we have
1205 // more advanced stack pointer tracking ability.
1206 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
1207 unsigned Opc = (CalleeAmt < 128) ?
1208 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1209 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1211 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
1219 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1220 int SPAdj, RegScavenger *RS) const{
1221 assert(SPAdj == 0 && "Unexpected");
1224 MachineInstr &MI = *II;
1225 MachineFunction &MF = *MI.getParent()->getParent();
1226 while (!MI.getOperand(i).isFrameIndex()) {
1228 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1231 int FrameIndex = MI.getOperand(i).getFrameIndex();
1232 // This must be part of a four operand memory reference. Replace the
1233 // FrameIndex with base register with EBP. Add an offset to the offset.
1234 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
1236 // Now add the frame object offset to the offset from EBP.
1237 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
1238 MI.getOperand(i+3).getImm()+SlotSize;
1241 Offset += MF.getFrameInfo()->getStackSize();
1243 Offset += SlotSize; // Skip the saved EBP
1245 MI.getOperand(i+3).ChangeToImmediate(Offset);
1249 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
1251 // Create a frame entry for the EBP register that must be saved.
1252 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
1253 (int)SlotSize * -2);
1254 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
1255 "Slot for EBP register must be last in order to be found!");
1259 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
1260 /// stack pointer by a constant value.
1262 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1263 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
1264 const TargetInstrInfo &TII) {
1265 bool isSub = NumBytes < 0;
1266 uint64_t Offset = isSub ? -NumBytes : NumBytes;
1267 unsigned Opc = isSub
1269 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1270 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
1272 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1273 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
1274 uint64_t Chunk = (1LL << 31) - 1;
1277 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
1278 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
1283 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
1284 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1285 MachineFrameInfo *MFI = MF.getFrameInfo();
1286 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1287 const Function* Fn = MF.getFunction();
1288 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
1289 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1290 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1291 MachineBasicBlock::iterator MBBI = MBB.begin();
1293 // Prepare for frame info.
1294 unsigned FrameLabelId = 0;
1296 // Get the number of bytes to allocate from the FrameInfo
1297 uint64_t StackSize = MFI->getStackSize();
1298 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1301 // Get the offset of the stack slot for the EBP register... which is
1302 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1303 // Update the frame offset adjustment.
1304 MFI->setOffsetAdjustment(SlotSize-NumBytes);
1306 // Save EBP into the appropriate stack slot...
1307 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1309 NumBytes -= SlotSize;
1311 if (MMI && MMI->needsFrameInfo()) {
1312 // Mark effective beginning of when frame pointer becomes valid.
1313 FrameLabelId = MMI->NextLabelID();
1314 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
1317 // Update EBP with the new base value...
1318 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1322 unsigned ReadyLabelId = 0;
1323 if (MMI && MMI->needsFrameInfo()) {
1324 // Mark effective beginning of when frame pointer is ready.
1325 ReadyLabelId = MMI->NextLabelID();
1326 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
1329 // Skip the callee-saved push instructions.
1330 while (MBBI != MBB.end() &&
1331 (MBBI->getOpcode() == X86::PUSH32r ||
1332 MBBI->getOpcode() == X86::PUSH64r))
1335 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
1336 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1337 // Check, whether EAX is livein for this function
1338 bool isEAXAlive = false;
1339 for (MachineFunction::livein_iterator II = MF.livein_begin(),
1340 EE = MF.livein_end(); (II != EE) && !isEAXAlive; ++II) {
1341 unsigned Reg = II->first;
1342 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1343 Reg == X86::AH || Reg == X86::AL);
1346 // Function prologue calls _alloca to probe the stack when allocating
1347 // more than 4k bytes in one go. Touching the stack at 4K increments is
1348 // necessary to ensure that the guard pages used by the OS virtual memory
1349 // manager are allocated in correct sequence.
1351 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
1352 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
1353 .addExternalSymbol("_alloca");
1356 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
1357 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1358 // allocated bytes for EAX.
1359 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
1360 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
1361 .addExternalSymbol("_alloca");
1363 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
1364 StackPtr, NumBytes-4);
1365 MBB.insert(MBBI, MI);
1368 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1369 // instruction, merge the two instructions.
1370 if (MBBI != MBB.end()) {
1371 MachineBasicBlock::iterator NI = next(MBBI);
1372 unsigned Opc = MBBI->getOpcode();
1373 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1374 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1375 MBBI->getOperand(0).getReg() == StackPtr) {
1376 NumBytes -= MBBI->getOperand(2).getImm();
1379 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1380 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1381 MBBI->getOperand(0).getReg() == StackPtr) {
1382 NumBytes += MBBI->getOperand(2).getImm();
1389 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1393 if (MMI && MMI->needsFrameInfo()) {
1394 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1395 const TargetData *TD = MF.getTarget().getTargetData();
1397 // Calculate amount of bytes used for return address storing
1399 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
1400 TargetFrameInfo::StackGrowsUp ?
1401 TD->getPointerSize() : -TD->getPointerSize());
1404 // Show update of SP.
1407 MachineLocation SPDst(MachineLocation::VirtualFP);
1408 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
1409 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1411 MachineLocation SPDst(MachineLocation::VirtualFP);
1412 MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize+stackGrowth);
1413 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1416 //FIXME: Verify & implement for FP
1417 MachineLocation SPDst(StackPtr);
1418 MachineLocation SPSrc(StackPtr, stackGrowth);
1419 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1422 // Add callee saved registers to move list.
1423 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1425 // FIXME: This is dirty hack. The code itself is pretty mess right now.
1426 // It should be rewritten from scratch and generalized sometimes.
1428 // Determine maximum offset (minumum due to stack growth)
1429 int64_t MaxOffset = 0;
1430 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
1431 MaxOffset = std::min(MaxOffset,
1432 MFI->getObjectOffset(CSI[I].getFrameIdx()));
1434 // Calculate offsets
1435 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
1436 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1437 unsigned Reg = CSI[I].getReg();
1438 Offset = (MaxOffset-Offset+3*stackGrowth);
1439 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1440 MachineLocation CSSrc(Reg);
1441 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1446 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
1447 MachineLocation FPSrc(FramePtr);
1448 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1451 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
1452 MachineLocation FPSrc(MachineLocation::VirtualFP);
1453 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1456 // If it's main() on Cygwin\Mingw32 we should align stack as well
1457 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1458 Subtarget->isTargetCygMing()) {
1459 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
1460 .addReg(X86::ESP).addImm(-Align);
1463 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(Align);
1464 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1468 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1469 MachineBasicBlock &MBB) const {
1470 const MachineFrameInfo *MFI = MF.getFrameInfo();
1471 const Function* Fn = MF.getFunction();
1472 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1473 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
1474 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1475 unsigned RetOpcode = MBBI->getOpcode();
1477 switch (RetOpcode) {
1480 case X86::EH_RETURN:
1483 case X86::TAILJMPm: break; // These are ok
1485 assert(0 && "Can only insert epilog into returning blocks");
1488 // Get the number of bytes to allocate from the FrameInfo
1489 uint64_t StackSize = MFI->getStackSize();
1490 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1491 uint64_t NumBytes = StackSize - CSSize;
1495 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1496 NumBytes -= SlotSize;
1499 // Skip the callee-saved pop instructions.
1500 while (MBBI != MBB.begin()) {
1501 MachineBasicBlock::iterator PI = prior(MBBI);
1502 unsigned Opc = PI->getOpcode();
1503 if (Opc != X86::POP32r && Opc != X86::POP64r && !TII.isTerminatorInstr(Opc))
1508 if (NumBytes || MFI->hasVarSizedObjects()) {
1509 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1510 // instruction, merge the two instructions.
1511 if (MBBI != MBB.begin()) {
1512 MachineBasicBlock::iterator PI = prior(MBBI);
1513 unsigned Opc = PI->getOpcode();
1514 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1515 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1516 PI->getOperand(0).getReg() == StackPtr) {
1517 NumBytes += PI->getOperand(2).getImm();
1519 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1520 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1521 PI->getOperand(0).getReg() == StackPtr) {
1522 NumBytes -= PI->getOperand(2).getImm();
1528 // If dynamic alloca is used, then reset esp to point to the last
1529 // callee-saved slot before popping them off!
1530 // Also, if it's main() on Cygwin/Mingw32 we aligned stack in the prologue, - revert
1531 // stack changes back. Note: we're assuming, that frame pointer was forced
1533 if (MFI->hasVarSizedObjects() ||
1534 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1535 Subtarget->isTargetCygMing())) {
1536 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1538 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
1540 MBB.insert(MBBI, MI);
1542 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1548 // adjust stack pointer back: ESP += numbytes
1550 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1552 // We're returning from function via eh_return.
1553 if (RetOpcode == X86::EH_RETURN) {
1554 MBBI = prior(MBB.end());
1555 MachineOperand &DestAddr = MBBI->getOperand(0);
1556 assert(DestAddr.isRegister() && "Offset should be in register!");
1557 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1558 addReg(DestAddr.getReg());
1562 unsigned X86RegisterInfo::getRARegister() const {
1564 return X86::RIP; // Should have dwarf #16
1566 return X86::EIP; // Should have dwarf #8
1569 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1570 return hasFP(MF) ? FramePtr : StackPtr;
1573 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1575 // Calculate amount of bytes used for return address storing
1576 int stackGrowth = (Is64Bit ? -8 : -4);
1578 // Initial state of the frame pointer is esp+4.
1579 MachineLocation Dst(MachineLocation::VirtualFP);
1580 MachineLocation Src(StackPtr, stackGrowth);
1581 Moves.push_back(MachineMove(0, Dst, Src));
1583 // Add return address to move list
1584 MachineLocation CSDst(StackPtr, stackGrowth);
1585 MachineLocation CSSrc(getRARegister());
1586 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1589 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1590 assert(0 && "What is the exception register");
1594 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1595 assert(0 && "What is the exception handler register");
1600 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
1602 default: return Reg;
1607 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1609 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1611 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1613 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1619 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1621 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1623 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1625 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1627 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1629 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1631 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1633 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1635 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1637 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1639 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1641 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1643 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1645 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1647 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1649 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1655 default: return Reg;
1656 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1658 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1660 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1662 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1664 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1666 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1668 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1670 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1672 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1674 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1676 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1678 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1680 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1682 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1684 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1686 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1691 default: return Reg;
1692 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1694 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1696 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1698 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1700 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1702 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1704 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1706 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1708 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1710 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1712 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1714 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1716 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1718 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1720 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1722 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1727 default: return Reg;
1728 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1730 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1732 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1734 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1736 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1738 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1740 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1742 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1744 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1746 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1748 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1750 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1752 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1754 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1756 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1758 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1767 #include "X86GenRegisterInfo.inc"