1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
48 ForceStackAlign("force-align-stack",
49 cl::desc("Force align the stack to the minimum alignment"
50 " needed for the function."),
51 cl::init(false), cl::Hidden);
54 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
57 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
58 const TargetInstrInfo &tii)
59 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
60 ? X86::RIP : X86::EIP,
61 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
62 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
64 X86_MC::InitLLVM2SEHRegisterMapping(this);
66 // Cache some information.
67 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
68 Is64Bit = Subtarget->is64Bit();
69 IsWin64 = Subtarget->isTargetWin64();
84 /// getCompactUnwindRegNum - This function maps the register to the number for
85 /// compact unwind encoding. Return -1 if the register isn't valid.
86 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
87 switch (getLLVMRegNum(RegNum, isEH)) {
88 case X86::EBX: case X86::RBX: return 1;
89 case X86::ECX: case X86::R12: return 2;
90 case X86::EDX: case X86::R13: return 3;
91 case X86::EDI: case X86::R14: return 4;
92 case X86::ESI: case X86::R15: return 5;
93 case X86::EBP: case X86::RBP: return 6;
100 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
101 // Only enable when post-RA scheduling is enabled and this is needed.
102 return TM.getSubtargetImpl()->postRAScheduler();
106 X86RegisterInfo::getSEHRegNum(unsigned i) const {
107 int reg = X86_MC::getX86RegNum(i);
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
110 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
111 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
112 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
113 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
114 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
115 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
116 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
117 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
118 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
119 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
120 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
126 const TargetRegisterClass *
127 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
128 unsigned Idx) const {
129 // The sub_8bit sub-register index is more constrained in 32-bit mode.
130 // It behaves just like the sub_8bit_hi index.
131 if (!Is64Bit && Idx == X86::sub_8bit)
132 Idx = X86::sub_8bit_hi;
134 // Forward to TableGen's default version.
135 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
138 const TargetRegisterClass *
139 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
140 const TargetRegisterClass *B,
141 unsigned SubIdx) const {
142 // The sub_8bit sub-register index is more constrained in 32-bit mode.
143 if (!Is64Bit && SubIdx == X86::sub_8bit) {
144 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
148 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
151 const TargetRegisterClass*
152 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
153 // Don't allow super-classes of GR8_NOREX. This class is only used after
154 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
155 // to the full GR8 register class in 64-bit mode, so we cannot allow the
156 // reigster class inflation.
158 // The GR8_NOREX class is always used in a way that won't be constrained to a
159 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
161 if (RC == &X86::GR8_NOREXRegClass)
164 const TargetRegisterClass *Super = RC;
165 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
167 switch (Super->getID()) {
168 case X86::GR8RegClassID:
169 case X86::GR16RegClassID:
170 case X86::GR32RegClassID:
171 case X86::GR64RegClassID:
172 case X86::FR32RegClassID:
173 case X86::FR64RegClassID:
174 case X86::RFP32RegClassID:
175 case X86::RFP64RegClassID:
176 case X86::RFP80RegClassID:
177 case X86::VR128RegClassID:
178 case X86::VR256RegClassID:
179 // Don't return a super-class that would shrink the spill size.
180 // That can happen with the vector and float classes.
181 if (Super->getSize() == RC->getSize())
189 const TargetRegisterClass *
190 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
193 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
194 case 0: // Normal GPRs.
195 if (TM.getSubtarget<X86Subtarget>().is64Bit())
196 return &X86::GR64RegClass;
197 return &X86::GR32RegClass;
198 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
199 if (TM.getSubtarget<X86Subtarget>().is64Bit())
200 return &X86::GR64_NOSPRegClass;
201 return &X86::GR32_NOSPRegClass;
202 case 2: // Available for tailcall (not callee-saved GPRs).
203 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
204 return &X86::GR64_TCW64RegClass;
205 if (TM.getSubtarget<X86Subtarget>().is64Bit())
206 return &X86::GR64_TCRegClass;
207 return &X86::GR32_TCRegClass;
211 const TargetRegisterClass *
212 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
213 if (RC == &X86::CCRRegClass) {
215 return &X86::GR64RegClass;
217 return &X86::GR32RegClass;
223 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
224 MachineFunction &MF) const {
225 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
227 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
228 switch (RC->getID()) {
231 case X86::GR32RegClassID:
233 case X86::GR64RegClassID:
235 case X86::VR128RegClassID:
236 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
237 case X86::VR64RegClassID:
243 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
244 bool callsEHReturn = false;
245 bool ghcCall = false;
248 callsEHReturn = MF->getMMI().callsEHReturn();
249 const Function *F = MF->getFunction();
250 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
254 return CSR_NoRegs_SaveList;
257 return CSR_Win64_SaveList;
259 return CSR_64EHRet_SaveList;
260 return CSR_64_SaveList;
263 return CSR_32EHRet_SaveList;
264 return CSR_32_SaveList;
268 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
269 if (CC == CallingConv::GHC)
270 return CSR_NoRegs_RegMask;
272 return CSR_32_RegMask;
274 return CSR_Win64_RegMask;
275 return CSR_64_RegMask;
278 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
279 BitVector Reserved(getNumRegs());
280 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
282 // Set the stack-pointer register and its aliases as reserved.
283 Reserved.set(X86::RSP);
284 for (MCSubRegIterator I(X86::RSP, this); I.isValid(); ++I)
287 // Set the instruction pointer register and its aliases as reserved.
288 Reserved.set(X86::RIP);
289 for (MCSubRegIterator I(X86::RIP, this); I.isValid(); ++I)
292 // Set the frame-pointer register and its aliases as reserved if needed.
293 if (TFI->hasFP(MF)) {
294 Reserved.set(X86::RBP);
295 for (MCSubRegIterator I(X86::RBP, this); I.isValid(); ++I)
299 // Set the base-pointer register and its aliases as reserved if needed.
300 if (hasBasePointer(MF)) {
301 CallingConv::ID CC = MF.getFunction()->getCallingConv();
302 const uint32_t* RegMask = getCallPreservedMask(CC);
303 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
305 "Stack realignment in presence of dynamic allocas is not supported with"
306 "this calling convention.");
308 Reserved.set(getBaseRegister());
309 for (MCSubRegIterator I(getBaseRegister(), this); I.isValid(); ++I)
313 // Mark the segment registers as reserved.
314 Reserved.set(X86::CS);
315 Reserved.set(X86::SS);
316 Reserved.set(X86::DS);
317 Reserved.set(X86::ES);
318 Reserved.set(X86::FS);
319 Reserved.set(X86::GS);
321 // Mark the floating point stack registers as reserved.
322 Reserved.set(X86::ST0);
323 Reserved.set(X86::ST1);
324 Reserved.set(X86::ST2);
325 Reserved.set(X86::ST3);
326 Reserved.set(X86::ST4);
327 Reserved.set(X86::ST5);
328 Reserved.set(X86::ST6);
329 Reserved.set(X86::ST7);
331 // Reserve the registers that only exist in 64-bit mode.
333 // These 8-bit registers are part of the x86-64 extension even though their
334 // super-registers are old 32-bits.
335 Reserved.set(X86::SIL);
336 Reserved.set(X86::DIL);
337 Reserved.set(X86::BPL);
338 Reserved.set(X86::SPL);
340 for (unsigned n = 0; n != 8; ++n) {
342 static const uint16_t GPR64[] = {
343 X86::R8, X86::R9, X86::R10, X86::R11,
344 X86::R12, X86::R13, X86::R14, X86::R15
346 for (MCRegAliasIterator AI(GPR64[n], this, true); AI.isValid(); ++AI)
350 assert(X86::XMM15 == X86::XMM8+7);
351 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
359 //===----------------------------------------------------------------------===//
360 // Stack Frame Processing methods
361 //===----------------------------------------------------------------------===//
363 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
364 const MachineFrameInfo *MFI = MF.getFrameInfo();
366 if (!EnableBasePointer)
369 // When we need stack realignment and there are dynamic allocas, we can't
370 // reference off of the stack pointer, so we reserve a base pointer.
371 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
377 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
378 const MachineFrameInfo *MFI = MF.getFrameInfo();
379 const MachineRegisterInfo *MRI = &MF.getRegInfo();
380 if (!MF.getTarget().Options.RealignStack)
383 // Stack realignment requires a frame pointer. If we already started
384 // register allocation with frame pointer elimination, it is too late now.
385 if (!MRI->canReserveReg(FramePtr))
388 // If a base pointer is necessary. Check that it isn't too late to reserve
390 if (MFI->hasVarSizedObjects())
391 return MRI->canReserveReg(BasePtr);
395 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
396 const MachineFrameInfo *MFI = MF.getFrameInfo();
397 const Function *F = MF.getFunction();
398 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
399 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
400 F->hasFnAttr(Attribute::StackAlignment));
402 // If we've requested that we force align the stack do so now.
404 return canRealignStack(MF);
406 return requiresRealignment && canRealignStack(MF);
409 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
410 unsigned Reg, int &FrameIdx) const {
411 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
413 if (Reg == FramePtr && TFI->hasFP(MF)) {
414 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
420 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
423 return X86::SUB64ri8;
424 return X86::SUB64ri32;
427 return X86::SUB32ri8;
432 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
435 return X86::ADD64ri8;
436 return X86::ADD64ri32;
439 return X86::ADD32ri8;
444 void X86RegisterInfo::
445 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
446 MachineBasicBlock::iterator I) const {
447 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
448 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
449 int Opcode = I->getOpcode();
450 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
451 DebugLoc DL = I->getDebugLoc();
452 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
453 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
456 if (!reseveCallFrame) {
457 // If the stack pointer can be changed after prologue, turn the
458 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
459 // adjcallstackdown instruction into 'add ESP, <amt>'
460 // TODO: consider using push / pop instead of sub + store / add
464 // We need to keep the stack aligned properly. To do this, we round the
465 // amount of space needed for the outgoing arguments up to the next
466 // alignment boundary.
467 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
468 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
470 MachineInstr *New = 0;
471 if (Opcode == TII.getCallFrameSetupOpcode()) {
472 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
477 assert(Opcode == TII.getCallFrameDestroyOpcode());
479 // Factor out the amount the callee already popped.
483 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
484 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
485 .addReg(StackPtr).addImm(Amount);
490 // The EFLAGS implicit def is dead.
491 New->getOperand(3).setIsDead();
493 // Replace the pseudo instruction with a new instruction.
500 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
501 // If we are performing frame pointer elimination and if the callee pops
502 // something off the stack pointer, add it back. We do this until we have
503 // more advanced stack pointer tracking ability.
504 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
505 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
506 .addReg(StackPtr).addImm(CalleeAmt);
508 // The EFLAGS implicit def is dead.
509 New->getOperand(3).setIsDead();
511 // We are not tracking the stack pointer adjustment by the callee, so make
512 // sure we restore the stack pointer immediately after the call, there may
513 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
514 MachineBasicBlock::iterator B = MBB.begin();
515 while (I != B && !llvm::prior(I)->isCall())
522 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
523 int SPAdj, RegScavenger *RS) const{
524 assert(SPAdj == 0 && "Unexpected");
527 MachineInstr &MI = *II;
528 MachineFunction &MF = *MI.getParent()->getParent();
529 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
531 while (!MI.getOperand(i).isFI()) {
533 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
536 int FrameIndex = MI.getOperand(i).getIndex();
539 unsigned Opc = MI.getOpcode();
540 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
541 if (hasBasePointer(MF))
542 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
543 else if (needsStackRealignment(MF))
544 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
548 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
550 // This must be part of a four operand memory reference. Replace the
551 // FrameIndex with base register with EBP. Add an offset to the offset.
552 MI.getOperand(i).ChangeToRegister(BasePtr, false);
554 // Now add the frame object offset to the offset from EBP.
557 // Tail call jmp happens after FP is popped.
558 const MachineFrameInfo *MFI = MF.getFrameInfo();
559 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
561 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
563 if (MI.getOperand(i+3).isImm()) {
564 // Offset is a 32-bit integer.
565 int Imm = (int)(MI.getOperand(i + 3).getImm());
566 int Offset = FIOffset + Imm;
567 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
568 "Requesting 64-bit offset in 32-bit immediate!");
569 MI.getOperand(i + 3).ChangeToImmediate(Offset);
571 // Offset is symbolic. This is extremely rare.
572 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
573 MI.getOperand(i+3).setOffset(Offset);
577 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
578 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
579 return TFI->hasFP(MF) ? FramePtr : StackPtr;
582 unsigned X86RegisterInfo::getEHExceptionRegister() const {
583 llvm_unreachable("What is the exception register");
586 unsigned X86RegisterInfo::getEHHandlerRegister() const {
587 llvm_unreachable("What is the exception handler register");
591 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
592 switch (VT.getSimpleVT().SimpleTy) {
597 default: return getX86SubSuperRegister(Reg, MVT::i64, High);
598 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
600 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
602 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
604 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
610 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
612 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
614 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
616 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
618 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
620 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
622 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
624 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
626 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
628 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
630 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
632 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
634 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
636 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
638 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
640 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
647 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
649 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
651 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
653 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
655 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
657 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
659 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
661 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
663 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
665 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
667 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
669 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
671 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
673 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
675 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
677 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
683 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
685 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
687 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
689 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
691 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
693 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
695 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
697 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
699 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
701 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
703 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
705 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
707 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
709 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
711 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
713 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
717 // For 64-bit mode if we've requested a "high" register and the
718 // Q or r constraints we want one of these high registers or
719 // just the register name otherwise.
722 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
724 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
726 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
728 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
735 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
737 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
739 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
741 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
743 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
745 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
747 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
749 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
751 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
753 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
755 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
757 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
759 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
761 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
763 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
765 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
773 struct MSAH : public MachineFunctionPass {
775 MSAH() : MachineFunctionPass(ID) {}
777 virtual bool runOnMachineFunction(MachineFunction &MF) {
778 const X86TargetMachine *TM =
779 static_cast<const X86TargetMachine *>(&MF.getTarget());
780 const TargetFrameLowering *TFI = TM->getFrameLowering();
781 MachineRegisterInfo &RI = MF.getRegInfo();
782 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
783 unsigned StackAlignment = TFI->getStackAlignment();
785 // Be over-conservative: scan over all vreg defs and find whether vector
786 // registers are used. If yes, there is a possibility that vector register
787 // will be spilled and thus require dynamic stack realignment.
788 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
789 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
790 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
791 FuncInfo->setForceFramePointer(true);
799 virtual const char *getPassName() const {
800 return "X86 Maximal Stack Alignment Check";
803 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
804 AU.setPreservesCFG();
805 MachineFunctionPass::getAnalysisUsage(AU);
813 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }