1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
48 ForceStackAlign("force-align-stack",
49 cl::desc("Force align the stack to the minimum alignment"
50 " needed for the function."),
51 cl::init(false), cl::Hidden);
53 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
54 const TargetInstrInfo &tii)
55 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
56 ? X86::RIP : X86::EIP,
57 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
58 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
60 X86_MC::InitLLVM2SEHRegisterMapping(this);
62 // Cache some information.
63 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
64 Is64Bit = Subtarget->is64Bit();
65 IsWin64 = Subtarget->isTargetWin64();
78 /// getCompactUnwindRegNum - This function maps the register to the number for
79 /// compact unwind encoding. Return -1 if the register isn't valid.
80 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
81 switch (getLLVMRegNum(RegNum, isEH)) {
82 case X86::EBX: case X86::RBX: return 1;
83 case X86::ECX: case X86::R12: return 2;
84 case X86::EDX: case X86::R13: return 3;
85 case X86::EDI: case X86::R14: return 4;
86 case X86::ESI: case X86::R15: return 5;
87 case X86::EBP: case X86::RBP: return 6;
94 X86RegisterInfo::getSEHRegNum(unsigned i) const {
95 int reg = X86_MC::getX86RegNum(i);
97 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
98 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
99 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
100 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
101 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
102 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
103 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
104 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
105 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
106 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
107 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
108 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
114 const TargetRegisterClass *
115 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
116 unsigned Idx) const {
117 // The sub_8bit sub-register index is more constrained in 32-bit mode.
118 // It behaves just like the sub_8bit_hi index.
119 if (!Is64Bit && Idx == X86::sub_8bit)
120 Idx = X86::sub_8bit_hi;
122 // Forward to TableGen's default version.
123 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
126 const TargetRegisterClass *
127 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
128 const TargetRegisterClass *B,
129 unsigned SubIdx) const {
130 // The sub_8bit sub-register index is more constrained in 32-bit mode.
131 if (!Is64Bit && SubIdx == X86::sub_8bit) {
132 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
136 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
139 const TargetRegisterClass*
140 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
141 // Don't allow super-classes of GR8_NOREX. This class is only used after
142 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
143 // to the full GR8 register class in 64-bit mode, so we cannot allow the
144 // reigster class inflation.
146 // The GR8_NOREX class is always used in a way that won't be constrained to a
147 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
149 if (RC == X86::GR8_NOREXRegisterClass)
152 const TargetRegisterClass *Super = RC;
153 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
155 switch (Super->getID()) {
156 case X86::GR8RegClassID:
157 case X86::GR16RegClassID:
158 case X86::GR32RegClassID:
159 case X86::GR64RegClassID:
160 case X86::FR32RegClassID:
161 case X86::FR64RegClassID:
162 case X86::RFP32RegClassID:
163 case X86::RFP64RegClassID:
164 case X86::RFP80RegClassID:
165 case X86::VR128RegClassID:
166 case X86::VR256RegClassID:
167 // Don't return a super-class that would shrink the spill size.
168 // That can happen with the vector and float classes.
169 if (Super->getSize() == RC->getSize())
177 const TargetRegisterClass *
178 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
180 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
181 case 0: // Normal GPRs.
182 if (TM.getSubtarget<X86Subtarget>().is64Bit())
183 return &X86::GR64RegClass;
184 return &X86::GR32RegClass;
185 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
186 if (TM.getSubtarget<X86Subtarget>().is64Bit())
187 return &X86::GR64_NOSPRegClass;
188 return &X86::GR32_NOSPRegClass;
189 case 2: // Available for tailcall (not callee-saved GPRs).
190 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
191 return &X86::GR64_TCW64RegClass;
192 if (TM.getSubtarget<X86Subtarget>().is64Bit())
193 return &X86::GR64_TCRegClass;
194 return &X86::GR32_TCRegClass;
198 const TargetRegisterClass *
199 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
200 if (RC == &X86::CCRRegClass) {
202 return &X86::GR64RegClass;
204 return &X86::GR32RegClass;
210 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
211 MachineFunction &MF) const {
212 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
214 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
215 switch (RC->getID()) {
218 case X86::GR32RegClassID:
220 case X86::GR64RegClassID:
222 case X86::VR128RegClassID:
223 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
224 case X86::VR64RegClassID:
230 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
231 bool callsEHReturn = false;
232 bool ghcCall = false;
235 callsEHReturn = MF->getMMI().callsEHReturn();
236 const Function *F = MF->getFunction();
237 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
240 static const unsigned GhcCalleeSavedRegs[] = {
244 static const unsigned CalleeSavedRegs32Bit[] = {
245 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
248 static const unsigned CalleeSavedRegs32EHRet[] = {
249 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
252 static const unsigned CalleeSavedRegs64Bit[] = {
253 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
256 static const unsigned CalleeSavedRegs64EHRet[] = {
257 X86::RAX, X86::RDX, X86::RBX, X86::R12,
258 X86::R13, X86::R14, X86::R15, X86::RBP, 0
261 static const unsigned CalleeSavedRegsWin64[] = {
262 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
263 X86::R12, X86::R13, X86::R14, X86::R15,
264 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
265 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
266 X86::XMM14, X86::XMM15, 0
270 return GhcCalleeSavedRegs;
271 } else if (Is64Bit) {
273 return CalleeSavedRegsWin64;
275 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
277 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
281 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
282 BitVector Reserved(getNumRegs());
283 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
285 // Set the stack-pointer register and its aliases as reserved.
286 Reserved.set(X86::RSP);
287 Reserved.set(X86::ESP);
288 Reserved.set(X86::SP);
289 Reserved.set(X86::SPL);
291 // Set the instruction pointer register and its aliases as reserved.
292 Reserved.set(X86::RIP);
293 Reserved.set(X86::EIP);
294 Reserved.set(X86::IP);
296 // Set the frame-pointer register and its aliases as reserved if needed.
297 if (TFI->hasFP(MF)) {
298 Reserved.set(X86::RBP);
299 Reserved.set(X86::EBP);
300 Reserved.set(X86::BP);
301 Reserved.set(X86::BPL);
304 // Mark the segment registers as reserved.
305 Reserved.set(X86::CS);
306 Reserved.set(X86::SS);
307 Reserved.set(X86::DS);
308 Reserved.set(X86::ES);
309 Reserved.set(X86::FS);
310 Reserved.set(X86::GS);
312 // Reserve the registers that only exist in 64-bit mode.
314 // These 8-bit registers are part of the x86-64 extension even though their
315 // super-registers are old 32-bits.
316 Reserved.set(X86::SIL);
317 Reserved.set(X86::DIL);
318 Reserved.set(X86::BPL);
319 Reserved.set(X86::SPL);
321 for (unsigned n = 0; n != 8; ++n) {
323 const unsigned GPR64[] = {
324 X86::R8, X86::R9, X86::R10, X86::R11,
325 X86::R12, X86::R13, X86::R14, X86::R15
327 for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
331 assert(X86::XMM15 == X86::XMM8+7);
332 for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
341 //===----------------------------------------------------------------------===//
342 // Stack Frame Processing methods
343 //===----------------------------------------------------------------------===//
345 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
346 const MachineFrameInfo *MFI = MF.getFrameInfo();
347 return (MF.getTarget().Options.RealignStack &&
348 !MFI->hasVarSizedObjects());
351 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
352 const MachineFrameInfo *MFI = MF.getFrameInfo();
353 const Function *F = MF.getFunction();
354 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
355 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
356 F->hasFnAttr(Attribute::StackAlignment));
358 // FIXME: Currently we don't support stack realignment for functions with
359 // variable-sized allocas.
360 // FIXME: It's more complicated than this...
361 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
363 "Stack realignment in presence of dynamic allocas is not supported");
365 // If we've requested that we force align the stack do so now.
367 return canRealignStack(MF);
369 return requiresRealignment && canRealignStack(MF);
372 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
373 unsigned Reg, int &FrameIdx) const {
374 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
376 if (Reg == FramePtr && TFI->hasFP(MF)) {
377 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
383 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
386 return X86::SUB64ri8;
387 return X86::SUB64ri32;
390 return X86::SUB32ri8;
395 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
398 return X86::ADD64ri8;
399 return X86::ADD64ri32;
402 return X86::ADD32ri8;
407 void X86RegisterInfo::
408 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
409 MachineBasicBlock::iterator I) const {
410 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
411 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
412 int Opcode = I->getOpcode();
413 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
414 DebugLoc DL = I->getDebugLoc();
415 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
416 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
419 if (!reseveCallFrame) {
420 // If the stack pointer can be changed after prologue, turn the
421 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
422 // adjcallstackdown instruction into 'add ESP, <amt>'
423 // TODO: consider using push / pop instead of sub + store / add
427 // We need to keep the stack aligned properly. To do this, we round the
428 // amount of space needed for the outgoing arguments up to the next
429 // alignment boundary.
430 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
431 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
433 MachineInstr *New = 0;
434 if (Opcode == TII.getCallFrameSetupOpcode()) {
435 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
440 assert(Opcode == TII.getCallFrameDestroyOpcode());
442 // Factor out the amount the callee already popped.
446 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
447 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
448 .addReg(StackPtr).addImm(Amount);
453 // The EFLAGS implicit def is dead.
454 New->getOperand(3).setIsDead();
456 // Replace the pseudo instruction with a new instruction.
463 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
464 // If we are performing frame pointer elimination and if the callee pops
465 // something off the stack pointer, add it back. We do this until we have
466 // more advanced stack pointer tracking ability.
467 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
468 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
469 .addReg(StackPtr).addImm(CalleeAmt);
471 // The EFLAGS implicit def is dead.
472 New->getOperand(3).setIsDead();
474 // We are not tracking the stack pointer adjustment by the callee, so make
475 // sure we restore the stack pointer immediately after the call, there may
476 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
477 MachineBasicBlock::iterator B = MBB.begin();
478 while (I != B && !llvm::prior(I)->isCall())
485 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
486 int SPAdj, RegScavenger *RS) const{
487 assert(SPAdj == 0 && "Unexpected");
490 MachineInstr &MI = *II;
491 MachineFunction &MF = *MI.getParent()->getParent();
492 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
494 while (!MI.getOperand(i).isFI()) {
496 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
499 int FrameIndex = MI.getOperand(i).getIndex();
502 unsigned Opc = MI.getOpcode();
503 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
504 if (needsStackRealignment(MF))
505 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
509 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
511 // This must be part of a four operand memory reference. Replace the
512 // FrameIndex with base register with EBP. Add an offset to the offset.
513 MI.getOperand(i).ChangeToRegister(BasePtr, false);
515 // Now add the frame object offset to the offset from EBP.
518 // Tail call jmp happens after FP is popped.
519 const MachineFrameInfo *MFI = MF.getFrameInfo();
520 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
522 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
524 if (MI.getOperand(i+3).isImm()) {
525 // Offset is a 32-bit integer.
526 int Imm = (int)(MI.getOperand(i + 3).getImm());
527 int Offset = FIOffset + Imm;
528 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
529 "Requesting 64-bit offset in 32-bit immediate!");
530 MI.getOperand(i + 3).ChangeToImmediate(Offset);
532 // Offset is symbolic. This is extremely rare.
533 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
534 MI.getOperand(i+3).setOffset(Offset);
538 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
539 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
540 return TFI->hasFP(MF) ? FramePtr : StackPtr;
543 unsigned X86RegisterInfo::getEHExceptionRegister() const {
544 llvm_unreachable("What is the exception register");
548 unsigned X86RegisterInfo::getEHHandlerRegister() const {
549 llvm_unreachable("What is the exception handler register");
554 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
555 switch (VT.getSimpleVT().SimpleTy) {
560 default: return getX86SubSuperRegister(Reg, MVT::i64, High);
561 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
563 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
565 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
567 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
573 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
575 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
577 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
579 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
581 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
583 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
585 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
587 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
589 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
591 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
593 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
595 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
597 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
599 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
601 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
603 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
610 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
612 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
614 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
616 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
618 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
620 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
622 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
624 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
626 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
628 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
630 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
632 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
634 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
636 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
638 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
640 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
646 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
648 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
650 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
652 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
654 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
656 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
658 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
660 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
662 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
664 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
666 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
668 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
670 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
672 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
674 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
676 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
680 // For 64-bit mode if we've requested a "high" register and the
681 // Q or r constraints we want one of these high registers or
682 // just the register name otherwise.
685 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
687 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
689 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
691 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
698 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
700 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
702 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
704 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
706 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
708 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
710 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
712 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
714 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
716 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
718 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
720 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
722 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
724 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
726 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
728 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
738 struct MSAH : public MachineFunctionPass {
740 MSAH() : MachineFunctionPass(ID) {}
742 virtual bool runOnMachineFunction(MachineFunction &MF) {
743 const X86TargetMachine *TM =
744 static_cast<const X86TargetMachine *>(&MF.getTarget());
745 const TargetFrameLowering *TFI = TM->getFrameLowering();
746 MachineRegisterInfo &RI = MF.getRegInfo();
747 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
748 unsigned StackAlignment = TFI->getStackAlignment();
750 // Be over-conservative: scan over all vreg defs and find whether vector
751 // registers are used. If yes, there is a possibility that vector register
752 // will be spilled and thus require dynamic stack realignment.
753 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
754 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
755 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
756 FuncInfo->setForceFramePointer(true);
764 virtual const char *getPassName() const {
765 return "X86 Maximal Stack Alignment Check";
768 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
769 AU.setPreservesCFG();
770 MachineFunctionPass::getAnalysisUsage(AU);
778 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }