1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45 const TargetInstrInfo &tii)
46 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47 X86::ADJCALLSTACKDOWN64 :
48 X86::ADJCALLSTACKDOWN32,
49 tm.getSubtarget<X86Subtarget>().is64Bit() ?
50 X86::ADJCALLSTACKUP64 :
51 X86::ADJCALLSTACKUP32),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
56 IsWin64 = Subtarget->isTargetWin64();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
70 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
71 /// specific numbering, used in debug info and exception tables.
72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74 unsigned Flavour = DWARFFlavour::X86_64;
76 if (!Subtarget->is64Bit()) {
77 if (Subtarget->isTargetDarwin()) {
79 Flavour = DWARFFlavour::X86_32_DarwinEH;
81 Flavour = DWARFFlavour::X86_32_Generic;
82 } else if (Subtarget->isTargetCygMing()) {
83 // Unsupported by now, just quick fallback
84 Flavour = DWARFFlavour::X86_32_Generic;
86 Flavour = DWARFFlavour::X86_32_Generic;
90 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
93 /// getX86RegNum - This function maps LLVM register identifiers to their X86
94 /// specific numbering, which is used in various places encoding instructions.
95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
97 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
103 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
105 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
107 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
114 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
116 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
120 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
122 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
124 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129 return RegNo-X86::ST0;
131 case X86::XMM0: case X86::XMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9: case X86::MM1:
135 case X86::XMM2: case X86::XMM10: case X86::MM2:
137 case X86::XMM3: case X86::XMM11: case X86::MM3:
139 case X86::XMM4: case X86::XMM12: case X86::MM4:
141 case X86::XMM5: case X86::XMM13: case X86::MM5:
143 case X86::XMM6: case X86::XMM14: case X86::MM6:
145 case X86::XMM7: case X86::XMM15: case X86::MM7:
149 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
155 const TargetRegisterClass *
156 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157 const TargetRegisterClass *B,
158 unsigned SubIdx) const {
163 if (B == &X86::GR8RegClass) {
164 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
166 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168 A == &X86::GR64_NOREXRegClass ||
169 A == &X86::GR64_NOSPRegClass ||
170 A == &X86::GR64_NOREX_NOSPRegClass)
171 return &X86::GR64_ABCDRegClass;
172 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
173 A == &X86::GR32_NOREXRegClass ||
174 A == &X86::GR32_NOSPRegClass)
175 return &X86::GR32_ABCDRegClass;
176 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
177 A == &X86::GR16_NOREXRegClass)
178 return &X86::GR16_ABCDRegClass;
179 } else if (B == &X86::GR8_NOREXRegClass) {
180 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
181 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
182 return &X86::GR64_NOREXRegClass;
183 else if (A == &X86::GR64_ABCDRegClass)
184 return &X86::GR64_ABCDRegClass;
185 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
186 A == &X86::GR32_NOSPRegClass)
187 return &X86::GR32_NOREXRegClass;
188 else if (A == &X86::GR32_ABCDRegClass)
189 return &X86::GR32_ABCDRegClass;
190 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
191 return &X86::GR16_NOREXRegClass;
192 else if (A == &X86::GR16_ABCDRegClass)
193 return &X86::GR16_ABCDRegClass;
198 if (B == &X86::GR8_ABCD_HRegClass) {
199 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
200 A == &X86::GR64_NOREXRegClass ||
201 A == &X86::GR64_NOSPRegClass ||
202 A == &X86::GR64_NOREX_NOSPRegClass)
203 return &X86::GR64_ABCDRegClass;
204 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
205 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
206 return &X86::GR32_ABCDRegClass;
207 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
208 A == &X86::GR16_NOREXRegClass)
209 return &X86::GR16_ABCDRegClass;
214 if (B == &X86::GR16RegClass) {
215 if (A->getSize() == 4 || A->getSize() == 8)
217 } else if (B == &X86::GR16_ABCDRegClass) {
218 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
219 A == &X86::GR64_NOREXRegClass ||
220 A == &X86::GR64_NOSPRegClass ||
221 A == &X86::GR64_NOREX_NOSPRegClass)
222 return &X86::GR64_ABCDRegClass;
223 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
224 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
225 return &X86::GR32_ABCDRegClass;
226 } else if (B == &X86::GR16_NOREXRegClass) {
227 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
228 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
229 return &X86::GR64_NOREXRegClass;
230 else if (A == &X86::GR64_ABCDRegClass)
231 return &X86::GR64_ABCDRegClass;
232 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
233 A == &X86::GR32_NOSPRegClass)
234 return &X86::GR32_NOREXRegClass;
235 else if (A == &X86::GR32_ABCDRegClass)
236 return &X86::GR64_ABCDRegClass;
241 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
242 if (A->getSize() == 8)
244 } else if (B == &X86::GR32_ABCDRegClass) {
245 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
246 A == &X86::GR64_NOREXRegClass ||
247 A == &X86::GR64_NOSPRegClass ||
248 A == &X86::GR64_NOREX_NOSPRegClass)
249 return &X86::GR64_ABCDRegClass;
250 } else if (B == &X86::GR32_NOREXRegClass) {
251 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
252 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
253 return &X86::GR64_NOREXRegClass;
254 else if (A == &X86::GR64_ABCDRegClass)
255 return &X86::GR64_ABCDRegClass;
262 const TargetRegisterClass *
263 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
265 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
266 case 0: // Normal GPRs.
267 if (TM.getSubtarget<X86Subtarget>().is64Bit())
268 return &X86::GR64RegClass;
269 return &X86::GR32RegClass;
270 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
271 if (TM.getSubtarget<X86Subtarget>().is64Bit())
272 return &X86::GR64_NOSPRegClass;
273 return &X86::GR32_NOSPRegClass;
277 const TargetRegisterClass *
278 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
279 if (RC == &X86::CCRRegClass) {
281 return &X86::GR64RegClass;
283 return &X86::GR32RegClass;
289 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
290 bool callsEHReturn = false;
293 const MachineFrameInfo *MFI = MF->getFrameInfo();
294 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
295 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
298 static const unsigned CalleeSavedRegs32Bit[] = {
299 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
302 static const unsigned CalleeSavedRegs32EHRet[] = {
303 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
306 static const unsigned CalleeSavedRegs64Bit[] = {
307 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
310 static const unsigned CalleeSavedRegs64EHRet[] = {
311 X86::RAX, X86::RDX, X86::RBX, X86::R12,
312 X86::R13, X86::R14, X86::R15, X86::RBP, 0
315 static const unsigned CalleeSavedRegsWin64[] = {
316 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
317 X86::R12, X86::R13, X86::R14, X86::R15,
318 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
319 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
320 X86::XMM14, X86::XMM15, 0
325 return CalleeSavedRegsWin64;
327 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
329 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
333 const TargetRegisterClass* const*
334 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
335 bool callsEHReturn = false;
338 const MachineFrameInfo *MFI = MF->getFrameInfo();
339 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
340 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
343 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
344 &X86::GR32RegClass, &X86::GR32RegClass,
345 &X86::GR32RegClass, &X86::GR32RegClass, 0
347 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
348 &X86::GR32RegClass, &X86::GR32RegClass,
349 &X86::GR32RegClass, &X86::GR32RegClass,
350 &X86::GR32RegClass, &X86::GR32RegClass, 0
352 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
353 &X86::GR64RegClass, &X86::GR64RegClass,
354 &X86::GR64RegClass, &X86::GR64RegClass,
355 &X86::GR64RegClass, &X86::GR64RegClass, 0
357 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
358 &X86::GR64RegClass, &X86::GR64RegClass,
359 &X86::GR64RegClass, &X86::GR64RegClass,
360 &X86::GR64RegClass, &X86::GR64RegClass,
361 &X86::GR64RegClass, &X86::GR64RegClass, 0
363 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
364 &X86::GR64RegClass, &X86::GR64RegClass,
365 &X86::GR64RegClass, &X86::GR64RegClass,
366 &X86::GR64RegClass, &X86::GR64RegClass,
367 &X86::GR64RegClass, &X86::GR64RegClass,
368 &X86::VR128RegClass, &X86::VR128RegClass,
369 &X86::VR128RegClass, &X86::VR128RegClass,
370 &X86::VR128RegClass, &X86::VR128RegClass,
371 &X86::VR128RegClass, &X86::VR128RegClass,
372 &X86::VR128RegClass, &X86::VR128RegClass, 0
377 return CalleeSavedRegClassesWin64;
379 return (callsEHReturn ?
380 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
382 return (callsEHReturn ?
383 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
387 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
388 BitVector Reserved(getNumRegs());
389 // Set the stack-pointer register and its aliases as reserved.
390 Reserved.set(X86::RSP);
391 Reserved.set(X86::ESP);
392 Reserved.set(X86::SP);
393 Reserved.set(X86::SPL);
395 // Set the frame-pointer register and its aliases as reserved if needed.
397 Reserved.set(X86::RBP);
398 Reserved.set(X86::EBP);
399 Reserved.set(X86::BP);
400 Reserved.set(X86::BPL);
403 // Mark the x87 stack registers as reserved, since they don't behave normally
404 // with respect to liveness. We don't fully model the effects of x87 stack
405 // pushes and pops after stackification.
406 Reserved.set(X86::ST0);
407 Reserved.set(X86::ST1);
408 Reserved.set(X86::ST2);
409 Reserved.set(X86::ST3);
410 Reserved.set(X86::ST4);
411 Reserved.set(X86::ST5);
412 Reserved.set(X86::ST6);
413 Reserved.set(X86::ST7);
417 //===----------------------------------------------------------------------===//
418 // Stack Frame Processing methods
419 //===----------------------------------------------------------------------===//
421 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
422 unsigned MaxAlign = 0;
424 for (int i = FFI->getObjectIndexBegin(),
425 e = FFI->getObjectIndexEnd(); i != e; ++i) {
426 if (FFI->isDeadObjectIndex(i))
429 unsigned Align = FFI->getObjectAlignment(i);
430 MaxAlign = std::max(MaxAlign, Align);
436 /// hasFP - Return true if the specified function should have a dedicated frame
437 /// pointer register. This is true if the function has variable sized allocas
438 /// or if frame pointer elimination is disabled.
439 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
440 const MachineFrameInfo *MFI = MF.getFrameInfo();
441 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
443 return (NoFramePointerElim ||
444 needsStackRealignment(MF) ||
445 MFI->hasVarSizedObjects() ||
446 MFI->isFrameAddressTaken() ||
447 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
448 (MMI && MMI->callsUnwindInit()));
451 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
452 const MachineFrameInfo *MFI = MF.getFrameInfo();
454 // FIXME: Currently we don't support stack realignment for functions with
455 // variable-sized allocas
456 return (RealignStack &&
457 (MFI->getMaxAlignment() > StackAlign &&
458 !MFI->hasVarSizedObjects()));
461 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
462 return !MF.getFrameInfo()->hasVarSizedObjects();
465 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
466 int &FrameIdx) const {
467 if (Reg == FramePtr && hasFP(MF)) {
468 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
475 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
476 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
477 MachineFrameInfo *MFI = MF.getFrameInfo();
478 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
479 uint64_t StackSize = MFI->getStackSize();
481 if (needsStackRealignment(MF)) {
483 // Skip the saved EBP.
486 unsigned Align = MFI->getObjectAlignment(FI);
487 assert( (-(Offset + StackSize)) % Align == 0);
489 return Offset + StackSize;
491 // FIXME: Support tail calls
494 return Offset + StackSize;
496 // Skip the saved EBP.
499 // Skip the RETADDR move area
500 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
501 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
502 if (TailCallReturnAddrDelta < 0)
503 Offset -= TailCallReturnAddrDelta;
509 void X86RegisterInfo::
510 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
511 MachineBasicBlock::iterator I) const {
512 if (!hasReservedCallFrame(MF)) {
513 // If the stack pointer can be changed after prologue, turn the
514 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
515 // adjcallstackdown instruction into 'add ESP, <amt>'
516 // TODO: consider using push / pop instead of sub + store / add
517 MachineInstr *Old = I;
518 uint64_t Amount = Old->getOperand(0).getImm();
520 // We need to keep the stack aligned properly. To do this, we round the
521 // amount of space needed for the outgoing arguments up to the next
522 // alignment boundary.
523 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
525 MachineInstr *New = 0;
526 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
527 New = BuildMI(MF, Old->getDebugLoc(),
528 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
533 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
535 // Factor out the amount the callee already popped.
536 uint64_t CalleeAmt = Old->getOperand(1).getImm();
540 unsigned Opc = (Amount < 128) ?
541 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
542 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
543 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
550 // The EFLAGS implicit def is dead.
551 New->getOperand(3).setIsDead();
553 // Replace the pseudo instruction with a new instruction.
557 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
558 // If we are performing frame pointer elimination and if the callee pops
559 // something off the stack pointer, add it back. We do this until we have
560 // more advanced stack pointer tracking ability.
561 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
562 unsigned Opc = (CalleeAmt < 128) ?
563 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
564 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
565 MachineInstr *Old = I;
567 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
572 // The EFLAGS implicit def is dead.
573 New->getOperand(3).setIsDead();
582 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
583 int SPAdj, int *Value,
584 RegScavenger *RS) const{
585 assert(SPAdj == 0 && "Unexpected");
588 MachineInstr &MI = *II;
589 MachineFunction &MF = *MI.getParent()->getParent();
591 while (!MI.getOperand(i).isFI()) {
593 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
596 int FrameIndex = MI.getOperand(i).getIndex();
599 if (needsStackRealignment(MF))
600 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
602 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
604 // This must be part of a four operand memory reference. Replace the
605 // FrameIndex with base register with EBP. Add an offset to the offset.
606 MI.getOperand(i).ChangeToRegister(BasePtr, false);
608 // Now add the frame object offset to the offset from EBP.
609 if (MI.getOperand(i+3).isImm()) {
610 // Offset is a 32-bit integer.
611 int Offset = getFrameIndexOffset(MF, FrameIndex) +
612 (int)(MI.getOperand(i + 3).getImm());
614 MI.getOperand(i + 3).ChangeToImmediate(Offset);
616 // Offset is symbolic. This is extremely rare.
617 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
618 (uint64_t)MI.getOperand(i+3).getOffset();
619 MI.getOperand(i+3).setOffset(Offset);
625 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
626 RegScavenger *RS) const {
627 MachineFrameInfo *MFI = MF.getFrameInfo();
629 // Calculate and set max stack object alignment early, so we can decide
630 // whether we will need stack realignment (and thus FP).
631 unsigned MaxAlign = std::max(MFI->getMaxAlignment(),
632 calculateMaxStackAlignment(MFI));
634 MFI->setMaxAlignment(MaxAlign);
636 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
637 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
639 if (TailCallReturnAddrDelta < 0) {
640 // create RETURNADDR area
649 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
650 (-1U*SlotSize)+TailCallReturnAddrDelta);
654 assert((TailCallReturnAddrDelta <= 0) &&
655 "The Delta should always be zero or negative");
656 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
658 // Create a frame entry for the EBP register that must be saved.
659 int FrameIdx = MFI->CreateFixedObject(SlotSize,
661 TFI.getOffsetOfLocalArea() +
662 TailCallReturnAddrDelta);
663 assert(FrameIdx == MFI->getObjectIndexBegin() &&
664 "Slot for EBP register must be last in order to be found!");
669 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
670 /// stack pointer by a constant value.
672 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
673 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
674 const TargetInstrInfo &TII) {
675 bool isSub = NumBytes < 0;
676 uint64_t Offset = isSub ? -NumBytes : NumBytes;
679 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
680 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
682 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
683 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
684 uint64_t Chunk = (1LL << 31) - 1;
685 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
686 DebugLoc::getUnknownLoc());
689 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
691 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
694 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
699 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
701 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
702 unsigned StackPtr, uint64_t *NumBytes = NULL) {
703 if (MBBI == MBB.begin()) return;
705 MachineBasicBlock::iterator PI = prior(MBBI);
706 unsigned Opc = PI->getOpcode();
707 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
708 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
709 PI->getOperand(0).getReg() == StackPtr) {
711 *NumBytes += PI->getOperand(2).getImm();
713 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
714 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
715 PI->getOperand(0).getReg() == StackPtr) {
717 *NumBytes -= PI->getOperand(2).getImm();
722 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
724 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
725 MachineBasicBlock::iterator &MBBI,
726 unsigned StackPtr, uint64_t *NumBytes = NULL) {
727 // FIXME: THIS ISN'T RUN!!!
730 if (MBBI == MBB.end()) return;
732 MachineBasicBlock::iterator NI = next(MBBI);
733 if (NI == MBB.end()) return;
735 unsigned Opc = NI->getOpcode();
736 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
737 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
738 NI->getOperand(0).getReg() == StackPtr) {
740 *NumBytes -= NI->getOperand(2).getImm();
743 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
744 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
745 NI->getOperand(0).getReg() == StackPtr) {
747 *NumBytes += NI->getOperand(2).getImm();
753 /// mergeSPUpdates - Checks the instruction before/after the passed
754 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
755 /// stack adjustment is returned as a positive value for ADD and a negative for
757 static int mergeSPUpdates(MachineBasicBlock &MBB,
758 MachineBasicBlock::iterator &MBBI,
760 bool doMergeWithPrevious) {
761 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
762 (!doMergeWithPrevious && MBBI == MBB.end()))
765 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
766 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
767 unsigned Opc = PI->getOpcode();
770 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
771 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
772 PI->getOperand(0).getReg() == StackPtr){
773 Offset += PI->getOperand(2).getImm();
775 if (!doMergeWithPrevious) MBBI = NI;
776 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
777 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
778 PI->getOperand(0).getReg() == StackPtr) {
779 Offset -= PI->getOperand(2).getImm();
781 if (!doMergeWithPrevious) MBBI = NI;
787 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
789 unsigned FramePtr) const {
790 MachineFrameInfo *MFI = MF.getFrameInfo();
791 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
794 // Add callee saved registers to move list.
795 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
796 if (CSI.empty()) return;
798 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
799 const TargetData *TD = MF.getTarget().getTargetData();
800 bool HasFP = hasFP(MF);
802 // Calculate amount of bytes used for return address storing.
804 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
805 TargetFrameInfo::StackGrowsUp ?
806 TD->getPointerSize() : -TD->getPointerSize());
808 // FIXME: This is dirty hack. The code itself is pretty mess right now.
809 // It should be rewritten from scratch and generalized sometimes.
811 // Determine maximum offset (minumum due to stack growth).
812 int64_t MaxOffset = 0;
813 for (std::vector<CalleeSavedInfo>::const_iterator
814 I = CSI.begin(), E = CSI.end(); I != E; ++I)
815 MaxOffset = std::min(MaxOffset,
816 MFI->getObjectOffset(I->getFrameIdx()));
818 // Calculate offsets.
819 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
820 for (std::vector<CalleeSavedInfo>::const_iterator
821 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
822 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
823 unsigned Reg = I->getReg();
824 Offset = MaxOffset - Offset + saveAreaOffset;
826 // Don't output a new machine move if we're re-saving the frame
827 // pointer. This happens when the PrologEpilogInserter has inserted an extra
828 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
829 // generates one when frame pointers are used. If we generate a "machine
830 // move" for this extra "PUSH", the linker will lose track of the fact that
831 // the frame pointer should have the value of the first "PUSH" when it's
834 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
835 // another bug. I.e., one where we generate a prolog like this:
843 // The immediate re-push of EBP is unnecessary. At the least, it's an
844 // optimization bug. EBP can be used as a scratch register in certain
845 // cases, but probably not when we have a frame pointer.
846 if (HasFP && FramePtr == Reg)
849 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
850 MachineLocation CSSrc(Reg);
851 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
855 /// emitPrologue - Push callee-saved registers onto the stack, which
856 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
857 /// space for local variables. Also emit labels used by the exception handler to
858 /// generate the exception handling frames.
859 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
860 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
861 MachineBasicBlock::iterator MBBI = MBB.begin();
862 MachineFrameInfo *MFI = MF.getFrameInfo();
863 const Function *Fn = MF.getFunction();
864 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
865 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
866 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
867 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
868 !Fn->doesNotThrow() || UnwindTablesMandatory;
869 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
870 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
871 bool HasFP = hasFP(MF);
874 // Add RETADDR move area to callee saved frame size.
875 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
876 if (TailCallReturnAddrDelta < 0)
877 X86FI->setCalleeSavedFrameSize(
878 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
880 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
881 // function, and use up to 128 bytes of stack space, don't have a frame
882 // pointer, calls, or dynamic alloca then we do not need to adjust the
883 // stack pointer (we fit in the Red Zone).
884 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
885 !needsStackRealignment(MF) &&
886 !MFI->hasVarSizedObjects() && // No dynamic alloca.
887 !MFI->hasCalls() && // No calls.
888 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
889 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
890 if (HasFP) MinSize += SlotSize;
891 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
892 MFI->setStackSize(StackSize);
893 } else if (Subtarget->isTargetWin64()) {
894 // We need to always allocate 32 bytes as register spill area.
895 // FIXME: We might reuse these 32 bytes for leaf functions.
897 MFI->setStackSize(StackSize);
900 // Insert stack pointer adjustment for later moving of return addr. Only
901 // applies to tail call optimized functions where the callee argument stack
902 // size is bigger than the callers.
903 if (TailCallReturnAddrDelta < 0) {
905 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
908 .addImm(-TailCallReturnAddrDelta);
909 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
912 // Mapping for machine moves:
914 // DST: VirtualFP AND
915 // SRC: VirtualFP => DW_CFA_def_cfa_offset
916 // ELSE => DW_CFA_def_cfa
918 // SRC: VirtualFP AND
919 // DST: Register => DW_CFA_def_cfa_register
922 // OFFSET < 0 => DW_CFA_offset_extended_sf
923 // REG < 64 => DW_CFA_offset + Reg
924 // ELSE => DW_CFA_offset_extended
926 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
927 const TargetData *TD = MF.getTarget().getTargetData();
928 uint64_t NumBytes = 0;
930 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
931 TargetFrameInfo::StackGrowsUp ?
932 TD->getPointerSize() : -TD->getPointerSize());
935 // Calculate required stack adjustment.
936 uint64_t FrameSize = StackSize - SlotSize;
937 if (needsStackRealignment(MF))
938 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
940 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
942 // Get the offset of the stack slot for the EBP register, which is
943 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
944 // Update the frame offset adjustment.
945 MFI->setOffsetAdjustment(-NumBytes);
947 // Save EBP/RBP into the appropriate stack slot.
948 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
949 .addReg(FramePtr, RegState::Kill);
951 if (needsFrameMoves) {
952 // Mark the place where EBP/RBP was saved.
953 unsigned FrameLabelId = MMI->NextLabelID();
954 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
956 // Define the current CFA rule to use the provided offset.
958 MachineLocation SPDst(MachineLocation::VirtualFP);
959 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
960 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
962 // FIXME: Verify & implement for FP
963 MachineLocation SPDst(StackPtr);
964 MachineLocation SPSrc(StackPtr, stackGrowth);
965 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
968 // Change the rule for the FramePtr to be an "offset" rule.
969 MachineLocation FPDst(MachineLocation::VirtualFP,
971 MachineLocation FPSrc(FramePtr);
972 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
975 // Update EBP with the new base value...
976 BuildMI(MBB, MBBI, DL,
977 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
980 if (needsFrameMoves) {
981 // Mark effective beginning of when frame pointer becomes valid.
982 unsigned FrameLabelId = MMI->NextLabelID();
983 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
985 // Define the current CFA to use the EBP/RBP register.
986 MachineLocation FPDst(FramePtr);
987 MachineLocation FPSrc(MachineLocation::VirtualFP);
988 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
991 // Mark the FramePtr as live-in in every block except the entry.
992 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
994 I->addLiveIn(FramePtr);
997 if (needsStackRealignment(MF)) {
999 BuildMI(MBB, MBBI, DL,
1000 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1001 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1003 // The EFLAGS implicit def is dead.
1004 MI->getOperand(3).setIsDead();
1007 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1010 // Skip the callee-saved push instructions.
1011 bool PushedRegs = false;
1012 int StackOffset = 2 * stackGrowth;
1014 while (MBBI != MBB.end() &&
1015 (MBBI->getOpcode() == X86::PUSH32r ||
1016 MBBI->getOpcode() == X86::PUSH64r)) {
1020 if (!HasFP && needsFrameMoves) {
1021 // Mark callee-saved push instruction.
1022 unsigned LabelId = MMI->NextLabelID();
1023 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1025 // Define the current CFA rule to use the provided offset.
1026 unsigned Ptr = StackSize ?
1027 MachineLocation::VirtualFP : StackPtr;
1028 MachineLocation SPDst(Ptr);
1029 MachineLocation SPSrc(Ptr, StackOffset);
1030 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1031 StackOffset += stackGrowth;
1035 if (MBBI != MBB.end())
1036 DL = MBBI->getDebugLoc();
1038 // Adjust stack pointer: ESP -= numbytes.
1039 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1040 // Check, whether EAX is livein for this function.
1041 bool isEAXAlive = false;
1042 for (MachineRegisterInfo::livein_iterator
1043 II = MF.getRegInfo().livein_begin(),
1044 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1045 unsigned Reg = II->first;
1046 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1047 Reg == X86::AH || Reg == X86::AL);
1050 // Function prologue calls _alloca to probe the stack when allocating more
1051 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1052 // to ensure that the guard pages used by the OS virtual memory manager are
1053 // allocated in correct sequence.
1055 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1057 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1058 .addExternalSymbol("_alloca");
1061 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1062 .addReg(X86::EAX, RegState::Kill);
1064 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1065 // allocated bytes for EAX.
1066 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1067 .addImm(NumBytes - 4);
1068 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1069 .addExternalSymbol("_alloca");
1072 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1074 StackPtr, false, NumBytes - 4);
1075 MBB.insert(MBBI, MI);
1077 } else if (NumBytes) {
1078 // If there is an SUB32ri of ESP immediately before this instruction, merge
1079 // the two. This can be the case when tail call elimination is enabled and
1080 // the callee has more arguments then the caller.
1081 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1083 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1084 // instruction, merge the two instructions.
1085 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1088 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1091 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1092 // Mark end of stack pointer adjustment.
1093 unsigned LabelId = MMI->NextLabelID();
1094 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1096 if (!HasFP && NumBytes) {
1097 // Define the current CFA rule to use the provided offset.
1099 MachineLocation SPDst(MachineLocation::VirtualFP);
1100 MachineLocation SPSrc(MachineLocation::VirtualFP,
1101 -StackSize + stackGrowth);
1102 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1104 // FIXME: Verify & implement for FP
1105 MachineLocation SPDst(StackPtr);
1106 MachineLocation SPSrc(StackPtr, stackGrowth);
1107 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1111 // Emit DWARF info specifying the offsets of the callee-saved registers.
1113 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1117 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1118 MachineBasicBlock &MBB) const {
1119 const MachineFrameInfo *MFI = MF.getFrameInfo();
1120 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1121 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1122 unsigned RetOpcode = MBBI->getOpcode();
1123 DebugLoc DL = MBBI->getDebugLoc();
1125 switch (RetOpcode) {
1127 llvm_unreachable("Can only insert epilog into returning blocks");
1130 case X86::TCRETURNdi:
1131 case X86::TCRETURNri:
1132 case X86::TCRETURNri64:
1133 case X86::TCRETURNdi64:
1134 case X86::EH_RETURN:
1135 case X86::EH_RETURN64:
1139 break; // These are ok
1142 // Get the number of bytes to allocate from the FrameInfo.
1143 uint64_t StackSize = MFI->getStackSize();
1144 uint64_t MaxAlign = MFI->getMaxAlignment();
1145 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1146 uint64_t NumBytes = 0;
1149 // Calculate required stack adjustment.
1150 uint64_t FrameSize = StackSize - SlotSize;
1151 if (needsStackRealignment(MF))
1152 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1154 NumBytes = FrameSize - CSSize;
1157 BuildMI(MBB, MBBI, DL,
1158 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1160 NumBytes = StackSize - CSSize;
1163 // Skip the callee-saved pop instructions.
1164 MachineBasicBlock::iterator LastCSPop = MBBI;
1165 while (MBBI != MBB.begin()) {
1166 MachineBasicBlock::iterator PI = prior(MBBI);
1167 unsigned Opc = PI->getOpcode();
1169 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1170 !PI->getDesc().isTerminator())
1176 DL = MBBI->getDebugLoc();
1178 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1179 // instruction, merge the two instructions.
1180 if (NumBytes || MFI->hasVarSizedObjects())
1181 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1183 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1184 // slot before popping them off! Same applies for the case, when stack was
1186 if (needsStackRealignment(MF)) {
1187 // We cannot use LEA here, because stack pointer was realigned. We need to
1188 // deallocate local frame back.
1190 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1191 MBBI = prior(LastCSPop);
1194 BuildMI(MBB, MBBI, DL,
1195 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1196 StackPtr).addReg(FramePtr);
1197 } else if (MFI->hasVarSizedObjects()) {
1199 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1201 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1202 FramePtr, false, -CSSize);
1203 MBB.insert(MBBI, MI);
1205 BuildMI(MBB, MBBI, DL,
1206 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1209 } else if (NumBytes) {
1210 // Adjust stack pointer back: ESP += numbytes.
1211 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1214 // We're returning from function via eh_return.
1215 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1216 MBBI = prior(MBB.end());
1217 MachineOperand &DestAddr = MBBI->getOperand(0);
1218 assert(DestAddr.isReg() && "Offset should be in register!");
1219 BuildMI(MBB, MBBI, DL,
1220 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1221 StackPtr).addReg(DestAddr.getReg());
1222 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1223 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1224 // Tail call return: adjust the stack pointer and jump to callee.
1225 MBBI = prior(MBB.end());
1226 MachineOperand &JumpTarget = MBBI->getOperand(0);
1227 MachineOperand &StackAdjust = MBBI->getOperand(1);
1228 assert(StackAdjust.isImm() && "Expecting immediate value.");
1230 // Adjust stack pointer.
1231 int StackAdj = StackAdjust.getImm();
1232 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1234 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1236 // Incoporate the retaddr area.
1237 Offset = StackAdj-MaxTCDelta;
1238 assert(Offset >= 0 && "Offset should never be negative");
1241 // Check for possible merge with preceeding ADD instruction.
1242 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1243 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1246 // Jump to label or value in register.
1247 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1248 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1249 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1250 else if (RetOpcode== X86::TCRETURNri64)
1251 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1253 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1255 // Delete the pseudo instruction TCRETURN.
1257 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1258 (X86FI->getTCReturnAddrDelta() < 0)) {
1259 // Add the return addr area delta back since we are not tail calling.
1260 int delta = -1*X86FI->getTCReturnAddrDelta();
1261 MBBI = prior(MBB.end());
1263 // Check for possible merge with preceeding ADD instruction.
1264 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1265 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1269 unsigned X86RegisterInfo::getRARegister() const {
1270 return Is64Bit ? X86::RIP // Should have dwarf #16.
1271 : X86::EIP; // Should have dwarf #8.
1274 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1275 return hasFP(MF) ? FramePtr : StackPtr;
1279 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1280 // Calculate amount of bytes used for return address storing
1281 int stackGrowth = (Is64Bit ? -8 : -4);
1283 // Initial state of the frame pointer is esp+4.
1284 MachineLocation Dst(MachineLocation::VirtualFP);
1285 MachineLocation Src(StackPtr, stackGrowth);
1286 Moves.push_back(MachineMove(0, Dst, Src));
1288 // Add return address to move list
1289 MachineLocation CSDst(StackPtr, stackGrowth);
1290 MachineLocation CSSrc(getRARegister());
1291 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1294 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1295 llvm_unreachable("What is the exception register");
1299 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1300 llvm_unreachable("What is the exception handler register");
1305 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1306 switch (VT.getSimpleVT().SimpleTy) {
1307 default: return Reg;
1312 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1314 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1316 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1318 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1324 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1326 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1328 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1330 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1332 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1334 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1336 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1338 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1340 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1342 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1344 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1346 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1348 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1350 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1352 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1354 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1360 default: return Reg;
1361 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1363 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1365 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1367 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1369 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1371 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1373 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1375 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1377 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1379 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1381 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1383 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1385 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1387 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1389 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1391 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1396 default: return Reg;
1397 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1399 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1401 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1403 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1405 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1407 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1409 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1411 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1413 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1415 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1417 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1419 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1421 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1423 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1425 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1427 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1432 default: return Reg;
1433 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1435 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1437 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1439 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1441 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1443 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1445 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1447 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1449 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1451 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1453 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1455 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1457 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1459 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1461 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1463 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1472 #include "X86GenRegisterInfo.inc"
1475 struct MSAC : public MachineFunctionPass {
1477 MSAC() : MachineFunctionPass(&ID) {}
1479 virtual bool runOnMachineFunction(MachineFunction &MF) {
1480 MachineFrameInfo *FFI = MF.getFrameInfo();
1481 MachineRegisterInfo &RI = MF.getRegInfo();
1483 // Calculate max stack alignment of all already allocated stack objects.
1484 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1486 // Be over-conservative: scan over all vreg defs and find, whether vector
1487 // registers are used. If yes - there is probability, that vector register
1488 // will be spilled and thus stack needs to be aligned properly.
1489 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1490 RegNum < RI.getLastVirtReg(); ++RegNum)
1491 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1493 if (FFI->getMaxAlignment() == MaxAlign)
1496 FFI->setMaxAlignment(MaxAlign);
1500 virtual const char *getPassName() const {
1501 return "X86 Maximal Stack Alignment Calculator";
1504 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1505 AU.setPreservesCFG();
1506 MachineFunctionPass::getAnalysisUsage(AU);
1514 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }