1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
48 ForceStackAlign("force-align-stack",
49 cl::desc("Force align the stack to the minimum alignment"
50 " needed for the function."),
51 cl::init(false), cl::Hidden);
54 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
57 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
58 const TargetInstrInfo &tii)
59 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
60 ? X86::RIP : X86::EIP,
61 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
62 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
64 X86_MC::InitLLVM2SEHRegisterMapping(this);
66 // Cache some information.
67 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
68 Is64Bit = Subtarget->is64Bit();
69 IsWin64 = Subtarget->isTargetWin64();
80 // Use a callee-saved register as the base pointer. These registers must
81 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
82 // requires GOT in the EBX register before function calls via PLT GOT pointer.
83 BasePtr = Is64Bit ? X86::RBX : X86::ESI;
86 /// getCompactUnwindRegNum - This function maps the register to the number for
87 /// compact unwind encoding. Return -1 if the register isn't valid.
88 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
89 switch (getLLVMRegNum(RegNum, isEH)) {
90 case X86::EBX: case X86::RBX: return 1;
91 case X86::ECX: case X86::R12: return 2;
92 case X86::EDX: case X86::R13: return 3;
93 case X86::EDI: case X86::R14: return 4;
94 case X86::ESI: case X86::R15: return 5;
95 case X86::EBP: case X86::RBP: return 6;
102 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
103 // Only enable when post-RA scheduling is enabled and this is needed.
104 return TM.getSubtargetImpl()->postRAScheduler();
108 X86RegisterInfo::getSEHRegNum(unsigned i) const {
109 return getEncodingValue(i);
112 const TargetRegisterClass *
113 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
114 unsigned Idx) const {
115 // The sub_8bit sub-register index is more constrained in 32-bit mode.
116 // It behaves just like the sub_8bit_hi index.
117 if (!Is64Bit && Idx == X86::sub_8bit)
118 Idx = X86::sub_8bit_hi;
120 // Forward to TableGen's default version.
121 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
124 const TargetRegisterClass *
125 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
126 const TargetRegisterClass *B,
127 unsigned SubIdx) const {
128 // The sub_8bit sub-register index is more constrained in 32-bit mode.
129 if (!Is64Bit && SubIdx == X86::sub_8bit) {
130 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
134 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
137 const TargetRegisterClass*
138 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
139 // Don't allow super-classes of GR8_NOREX. This class is only used after
140 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
141 // to the full GR8 register class in 64-bit mode, so we cannot allow the
142 // reigster class inflation.
144 // The GR8_NOREX class is always used in a way that won't be constrained to a
145 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
147 if (RC == &X86::GR8_NOREXRegClass)
150 const TargetRegisterClass *Super = RC;
151 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
153 switch (Super->getID()) {
154 case X86::GR8RegClassID:
155 case X86::GR16RegClassID:
156 case X86::GR32RegClassID:
157 case X86::GR64RegClassID:
158 case X86::FR32RegClassID:
159 case X86::FR64RegClassID:
160 case X86::RFP32RegClassID:
161 case X86::RFP64RegClassID:
162 case X86::RFP80RegClassID:
163 case X86::VR128RegClassID:
164 case X86::VR256RegClassID:
165 // Don't return a super-class that would shrink the spill size.
166 // That can happen with the vector and float classes.
167 if (Super->getSize() == RC->getSize())
175 const TargetRegisterClass *
176 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
179 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
180 case 0: // Normal GPRs.
181 if (TM.getSubtarget<X86Subtarget>().is64Bit())
182 return &X86::GR64RegClass;
183 return &X86::GR32RegClass;
184 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
185 if (TM.getSubtarget<X86Subtarget>().is64Bit())
186 return &X86::GR64_NOSPRegClass;
187 return &X86::GR32_NOSPRegClass;
188 case 2: // Available for tailcall (not callee-saved GPRs).
189 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
190 return &X86::GR64_TCW64RegClass;
191 if (TM.getSubtarget<X86Subtarget>().is64Bit())
192 return &X86::GR64_TCRegClass;
193 return &X86::GR32_TCRegClass;
197 const TargetRegisterClass *
198 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
199 if (RC == &X86::CCRRegClass) {
201 return &X86::GR64RegClass;
203 return &X86::GR32RegClass;
209 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
210 MachineFunction &MF) const {
211 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
213 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
214 switch (RC->getID()) {
217 case X86::GR32RegClassID:
219 case X86::GR64RegClassID:
221 case X86::VR128RegClassID:
222 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
223 case X86::VR64RegClassID:
229 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
230 bool callsEHReturn = false;
231 bool ghcCall = false;
234 callsEHReturn = MF->getMMI().callsEHReturn();
235 const Function *F = MF->getFunction();
236 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
240 return CSR_NoRegs_SaveList;
243 return CSR_Win64_SaveList;
245 return CSR_64EHRet_SaveList;
246 return CSR_64_SaveList;
249 return CSR_32EHRet_SaveList;
250 return CSR_32_SaveList;
254 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
255 if (CC == CallingConv::GHC)
256 return CSR_NoRegs_RegMask;
258 return CSR_32_RegMask;
260 return CSR_Win64_RegMask;
261 return CSR_64_RegMask;
264 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
265 BitVector Reserved(getNumRegs());
266 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
268 // Set the stack-pointer register and its aliases as reserved.
269 Reserved.set(X86::RSP);
270 for (MCSubRegIterator I(X86::RSP, this); I.isValid(); ++I)
273 // Set the instruction pointer register and its aliases as reserved.
274 Reserved.set(X86::RIP);
275 for (MCSubRegIterator I(X86::RIP, this); I.isValid(); ++I)
278 // Set the frame-pointer register and its aliases as reserved if needed.
279 if (TFI->hasFP(MF)) {
280 Reserved.set(X86::RBP);
281 for (MCSubRegIterator I(X86::RBP, this); I.isValid(); ++I)
285 // Set the base-pointer register and its aliases as reserved if needed.
286 if (hasBasePointer(MF)) {
287 CallingConv::ID CC = MF.getFunction()->getCallingConv();
288 const uint32_t* RegMask = getCallPreservedMask(CC);
289 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
291 "Stack realignment in presence of dynamic allocas is not supported with"
292 "this calling convention.");
294 Reserved.set(getBaseRegister());
295 for (MCSubRegIterator I(getBaseRegister(), this); I.isValid(); ++I)
299 // Mark the segment registers as reserved.
300 Reserved.set(X86::CS);
301 Reserved.set(X86::SS);
302 Reserved.set(X86::DS);
303 Reserved.set(X86::ES);
304 Reserved.set(X86::FS);
305 Reserved.set(X86::GS);
307 // Mark the floating point stack registers as reserved.
308 Reserved.set(X86::ST0);
309 Reserved.set(X86::ST1);
310 Reserved.set(X86::ST2);
311 Reserved.set(X86::ST3);
312 Reserved.set(X86::ST4);
313 Reserved.set(X86::ST5);
314 Reserved.set(X86::ST6);
315 Reserved.set(X86::ST7);
317 // Reserve the registers that only exist in 64-bit mode.
319 // These 8-bit registers are part of the x86-64 extension even though their
320 // super-registers are old 32-bits.
321 Reserved.set(X86::SIL);
322 Reserved.set(X86::DIL);
323 Reserved.set(X86::BPL);
324 Reserved.set(X86::SPL);
326 for (unsigned n = 0; n != 8; ++n) {
328 static const uint16_t GPR64[] = {
329 X86::R8, X86::R9, X86::R10, X86::R11,
330 X86::R12, X86::R13, X86::R14, X86::R15
332 for (MCRegAliasIterator AI(GPR64[n], this, true); AI.isValid(); ++AI)
336 assert(X86::XMM15 == X86::XMM8+7);
337 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
345 //===----------------------------------------------------------------------===//
346 // Stack Frame Processing methods
347 //===----------------------------------------------------------------------===//
349 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
350 const MachineFrameInfo *MFI = MF.getFrameInfo();
352 if (!EnableBasePointer)
355 // When we need stack realignment and there are dynamic allocas, we can't
356 // reference off of the stack pointer, so we reserve a base pointer.
357 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
363 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
364 const MachineFrameInfo *MFI = MF.getFrameInfo();
365 const MachineRegisterInfo *MRI = &MF.getRegInfo();
366 if (!MF.getTarget().Options.RealignStack)
369 // Stack realignment requires a frame pointer. If we already started
370 // register allocation with frame pointer elimination, it is too late now.
371 if (!MRI->canReserveReg(FramePtr))
374 // If a base pointer is necessary. Check that it isn't too late to reserve
376 if (MFI->hasVarSizedObjects())
377 return MRI->canReserveReg(BasePtr);
381 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
382 const MachineFrameInfo *MFI = MF.getFrameInfo();
383 const Function *F = MF.getFunction();
384 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
385 bool requiresRealignment =
386 ((MFI->getMaxAlignment() > StackAlign) ||
387 F->getFnAttributes().hasAttribute(Attributes::StackAlignment));
389 // If we've requested that we force align the stack do so now.
391 return canRealignStack(MF);
393 return requiresRealignment && canRealignStack(MF);
396 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
397 unsigned Reg, int &FrameIdx) const {
398 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
400 if (Reg == FramePtr && TFI->hasFP(MF)) {
401 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
407 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
410 return X86::SUB64ri8;
411 return X86::SUB64ri32;
414 return X86::SUB32ri8;
419 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
422 return X86::ADD64ri8;
423 return X86::ADD64ri32;
426 return X86::ADD32ri8;
431 void X86RegisterInfo::
432 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
433 MachineBasicBlock::iterator I) const {
434 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
435 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
436 int Opcode = I->getOpcode();
437 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
438 DebugLoc DL = I->getDebugLoc();
439 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
440 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
443 if (!reseveCallFrame) {
444 // If the stack pointer can be changed after prologue, turn the
445 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
446 // adjcallstackdown instruction into 'add ESP, <amt>'
447 // TODO: consider using push / pop instead of sub + store / add
451 // We need to keep the stack aligned properly. To do this, we round the
452 // amount of space needed for the outgoing arguments up to the next
453 // alignment boundary.
454 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
455 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
457 MachineInstr *New = 0;
458 if (Opcode == TII.getCallFrameSetupOpcode()) {
459 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
464 assert(Opcode == TII.getCallFrameDestroyOpcode());
466 // Factor out the amount the callee already popped.
470 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
471 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
472 .addReg(StackPtr).addImm(Amount);
477 // The EFLAGS implicit def is dead.
478 New->getOperand(3).setIsDead();
480 // Replace the pseudo instruction with a new instruction.
487 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
488 // If we are performing frame pointer elimination and if the callee pops
489 // something off the stack pointer, add it back. We do this until we have
490 // more advanced stack pointer tracking ability.
491 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
492 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
493 .addReg(StackPtr).addImm(CalleeAmt);
495 // The EFLAGS implicit def is dead.
496 New->getOperand(3).setIsDead();
498 // We are not tracking the stack pointer adjustment by the callee, so make
499 // sure we restore the stack pointer immediately after the call, there may
500 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
501 MachineBasicBlock::iterator B = MBB.begin();
502 while (I != B && !llvm::prior(I)->isCall())
509 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
510 int SPAdj, RegScavenger *RS) const {
511 assert(SPAdj == 0 && "Unexpected");
514 MachineInstr &MI = *II;
515 MachineFunction &MF = *MI.getParent()->getParent();
516 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
518 while (!MI.getOperand(i).isFI()) {
520 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
523 int FrameIndex = MI.getOperand(i).getIndex();
526 unsigned Opc = MI.getOpcode();
527 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
528 if (hasBasePointer(MF))
529 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
530 else if (needsStackRealignment(MF))
531 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
535 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
537 // This must be part of a four operand memory reference. Replace the
538 // FrameIndex with base register with EBP. Add an offset to the offset.
539 MI.getOperand(i).ChangeToRegister(BasePtr, false);
541 // Now add the frame object offset to the offset from EBP.
544 // Tail call jmp happens after FP is popped.
545 const MachineFrameInfo *MFI = MF.getFrameInfo();
546 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
548 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
550 if (MI.getOperand(i+3).isImm()) {
551 // Offset is a 32-bit integer.
552 int Imm = (int)(MI.getOperand(i + 3).getImm());
553 int Offset = FIOffset + Imm;
554 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
555 "Requesting 64-bit offset in 32-bit immediate!");
556 MI.getOperand(i + 3).ChangeToImmediate(Offset);
558 // Offset is symbolic. This is extremely rare.
559 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
560 MI.getOperand(i+3).setOffset(Offset);
564 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
565 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
566 return TFI->hasFP(MF) ? FramePtr : StackPtr;
569 unsigned X86RegisterInfo::getEHExceptionRegister() const {
570 llvm_unreachable("What is the exception register");
573 unsigned X86RegisterInfo::getEHHandlerRegister() const {
574 llvm_unreachable("What is the exception handler register");
578 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
581 default: llvm_unreachable("Unexpected VT");
585 default: return getX86SubSuperRegister(Reg, MVT::i64, High);
586 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
588 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
590 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
592 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
597 default: llvm_unreachable("Unexpected register");
598 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
600 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
602 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
604 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
606 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
608 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
610 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
612 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
614 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
616 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
618 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
620 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
622 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
624 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
626 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
628 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
634 default: llvm_unreachable("Unexpected register");
635 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
637 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
639 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
641 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
643 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
645 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
647 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
649 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
651 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
653 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
655 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
657 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
659 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
661 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
663 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
665 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
670 default: llvm_unreachable("Unexpected register");
671 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
673 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
675 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
677 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
679 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
681 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
683 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
685 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
687 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
689 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
691 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
693 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
695 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
697 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
699 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
701 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
705 // For 64-bit mode if we've requested a "high" register and the
706 // Q or r constraints we want one of these high registers or
707 // just the register name otherwise.
710 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
712 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
714 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
716 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
722 default: llvm_unreachable("Unexpected register");
723 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
725 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
727 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
729 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
731 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
733 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
735 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
737 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
739 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
741 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
743 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
745 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
747 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
749 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
751 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
753 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
761 struct MSAH : public MachineFunctionPass {
763 MSAH() : MachineFunctionPass(ID) {}
765 virtual bool runOnMachineFunction(MachineFunction &MF) {
766 const X86TargetMachine *TM =
767 static_cast<const X86TargetMachine *>(&MF.getTarget());
768 const TargetFrameLowering *TFI = TM->getFrameLowering();
769 MachineRegisterInfo &RI = MF.getRegInfo();
770 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
771 unsigned StackAlignment = TFI->getStackAlignment();
773 // Be over-conservative: scan over all vreg defs and find whether vector
774 // registers are used. If yes, there is a possibility that vector register
775 // will be spilled and thus require dynamic stack realignment.
776 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
777 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
778 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
779 FuncInfo->setForceFramePointer(true);
787 virtual const char *getPassName() const {
788 return "X86 Maximal Stack Alignment Check";
791 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
792 AU.setPreservesCFG();
793 MachineFunctionPass::getAnalysisUsage(AU);
801 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }