1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/MachineValueType.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
47 ForceStackAlign("force-align-stack",
48 cl::desc("Force align the stack to the minimum alignment"
49 " needed for the function."),
50 cl::init(false), cl::Hidden);
53 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
56 X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI)
58 (STI.is64Bit() ? X86::RIP : X86::EIP),
59 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false),
60 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true),
61 (STI.is64Bit() ? X86::RIP : X86::EIP)),
63 X86_MC::InitLLVM2SEHRegisterMapping(this);
65 // Cache some information.
66 Is64Bit = Subtarget.is64Bit();
67 IsWin64 = Subtarget.isTargetWin64();
69 // Use a callee-saved register as the base pointer. These registers must
70 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
71 // requires GOT in the EBX register before function calls via PLT GOT pointer.
75 Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64();
76 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
77 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
78 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
88 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
89 // ExeDepsFixer and PostRAScheduler require liveness.
94 X86RegisterInfo::getSEHRegNum(unsigned i) const {
95 return getEncodingValue(i);
98 const TargetRegisterClass *
99 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
100 unsigned Idx) const {
101 // The sub_8bit sub-register index is more constrained in 32-bit mode.
102 // It behaves just like the sub_8bit_hi index.
103 if (!Is64Bit && Idx == X86::sub_8bit)
104 Idx = X86::sub_8bit_hi;
106 // Forward to TableGen's default version.
107 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
110 const TargetRegisterClass *
111 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
112 const TargetRegisterClass *B,
113 unsigned SubIdx) const {
114 // The sub_8bit sub-register index is more constrained in 32-bit mode.
115 if (!Is64Bit && SubIdx == X86::sub_8bit) {
116 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
120 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
123 const TargetRegisterClass*
124 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
125 // Don't allow super-classes of GR8_NOREX. This class is only used after
126 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
127 // to the full GR8 register class in 64-bit mode, so we cannot allow the
128 // reigster class inflation.
130 // The GR8_NOREX class is always used in a way that won't be constrained to a
131 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
133 if (RC == &X86::GR8_NOREXRegClass)
136 const TargetRegisterClass *Super = RC;
137 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
139 switch (Super->getID()) {
140 case X86::GR8RegClassID:
141 case X86::GR16RegClassID:
142 case X86::GR32RegClassID:
143 case X86::GR64RegClassID:
144 case X86::FR32RegClassID:
145 case X86::FR64RegClassID:
146 case X86::RFP32RegClassID:
147 case X86::RFP64RegClassID:
148 case X86::RFP80RegClassID:
149 case X86::VR128RegClassID:
150 case X86::VR256RegClassID:
151 // Don't return a super-class that would shrink the spill size.
152 // That can happen with the vector and float classes.
153 if (Super->getSize() == RC->getSize())
161 const TargetRegisterClass *
162 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
163 unsigned Kind) const {
165 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
166 case 0: // Normal GPRs.
167 if (Subtarget.isTarget64BitLP64())
168 return &X86::GR64RegClass;
169 return &X86::GR32RegClass;
170 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
171 if (Subtarget.isTarget64BitLP64())
172 return &X86::GR64_NOSPRegClass;
173 return &X86::GR32_NOSPRegClass;
174 case 2: // Available for tailcall (not callee-saved GPRs).
175 if (Subtarget.isTargetWin64())
176 return &X86::GR64_TCW64RegClass;
177 else if (Subtarget.is64Bit())
178 return &X86::GR64_TCRegClass;
180 const Function *F = MF.getFunction();
181 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
183 return &X86::GR32RegClass;
184 return &X86::GR32_TCRegClass;
188 const TargetRegisterClass *
189 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
190 if (RC == &X86::CCRRegClass) {
192 return &X86::GR64RegClass;
194 return &X86::GR32RegClass;
200 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
201 MachineFunction &MF) const {
202 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
204 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
205 switch (RC->getID()) {
208 case X86::GR32RegClassID:
210 case X86::GR64RegClassID:
212 case X86::VR128RegClassID:
213 return Subtarget.is64Bit() ? 10 : 4;
214 case X86::VR64RegClassID:
220 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
221 bool HasAVX = Subtarget.hasAVX();
222 bool HasAVX512 = Subtarget.hasAVX512();
224 assert(MF && "MachineFunction required");
225 switch (MF->getFunction()->getCallingConv()) {
226 case CallingConv::GHC:
227 case CallingConv::HiPE:
228 return CSR_NoRegs_SaveList;
229 case CallingConv::AnyReg:
231 return CSR_64_AllRegs_AVX_SaveList;
232 return CSR_64_AllRegs_SaveList;
233 case CallingConv::PreserveMost:
234 return CSR_64_RT_MostRegs_SaveList;
235 case CallingConv::PreserveAll:
237 return CSR_64_RT_AllRegs_AVX_SaveList;
238 return CSR_64_RT_AllRegs_SaveList;
239 case CallingConv::Intel_OCL_BI: {
240 if (HasAVX512 && IsWin64)
241 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
242 if (HasAVX512 && Is64Bit)
243 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
244 if (HasAVX && IsWin64)
245 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
246 if (HasAVX && Is64Bit)
247 return CSR_64_Intel_OCL_BI_AVX_SaveList;
248 if (!HasAVX && !IsWin64 && Is64Bit)
249 return CSR_64_Intel_OCL_BI_SaveList;
252 case CallingConv::Cold:
254 return CSR_64_MostRegs_SaveList;
260 bool CallsEHReturn = MF->getMMI().callsEHReturn();
263 return CSR_Win64_SaveList;
265 return CSR_64EHRet_SaveList;
266 return CSR_64_SaveList;
269 return CSR_32EHRet_SaveList;
270 return CSR_32_SaveList;
274 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
275 bool HasAVX = Subtarget.hasAVX();
276 bool HasAVX512 = Subtarget.hasAVX512();
279 case CallingConv::GHC:
280 case CallingConv::HiPE:
281 return CSR_NoRegs_RegMask;
282 case CallingConv::AnyReg:
284 return CSR_64_AllRegs_AVX_RegMask;
285 return CSR_64_AllRegs_RegMask;
286 case CallingConv::PreserveMost:
287 return CSR_64_RT_MostRegs_RegMask;
288 case CallingConv::PreserveAll:
290 return CSR_64_RT_AllRegs_AVX_RegMask;
291 return CSR_64_RT_AllRegs_RegMask;
292 case CallingConv::Intel_OCL_BI: {
293 if (HasAVX512 && IsWin64)
294 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
295 if (HasAVX512 && Is64Bit)
296 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
297 if (HasAVX && IsWin64)
298 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
299 if (HasAVX && Is64Bit)
300 return CSR_64_Intel_OCL_BI_AVX_RegMask;
301 if (!HasAVX && !IsWin64 && Is64Bit)
302 return CSR_64_Intel_OCL_BI_RegMask;
305 case CallingConv::Cold:
307 return CSR_64_MostRegs_RegMask;
313 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
317 return CSR_Win64_RegMask;
318 return CSR_64_RegMask;
320 return CSR_32_RegMask;
324 X86RegisterInfo::getNoPreservedMask() const {
325 return CSR_NoRegs_RegMask;
328 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
329 BitVector Reserved(getNumRegs());
330 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
332 // Set the stack-pointer register and its aliases as reserved.
333 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
337 // Set the instruction pointer register and its aliases as reserved.
338 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
342 // Set the frame-pointer register and its aliases as reserved if needed.
343 if (TFI->hasFP(MF)) {
344 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
349 // Set the base-pointer register and its aliases as reserved if needed.
350 if (hasBasePointer(MF)) {
351 CallingConv::ID CC = MF.getFunction()->getCallingConv();
352 const uint32_t* RegMask = getCallPreservedMask(CC);
353 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
355 "Stack realignment in presence of dynamic allocas is not supported with"
356 "this calling convention.");
358 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64,
360 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
365 // Mark the segment registers as reserved.
366 Reserved.set(X86::CS);
367 Reserved.set(X86::SS);
368 Reserved.set(X86::DS);
369 Reserved.set(X86::ES);
370 Reserved.set(X86::FS);
371 Reserved.set(X86::GS);
373 // Mark the floating point stack registers as reserved.
374 for (unsigned n = 0; n != 8; ++n)
375 Reserved.set(X86::ST0 + n);
377 // Reserve the registers that only exist in 64-bit mode.
379 // These 8-bit registers are part of the x86-64 extension even though their
380 // super-registers are old 32-bits.
381 Reserved.set(X86::SIL);
382 Reserved.set(X86::DIL);
383 Reserved.set(X86::BPL);
384 Reserved.set(X86::SPL);
386 for (unsigned n = 0; n != 8; ++n) {
388 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
392 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
396 if (!Is64Bit || !Subtarget.hasAVX512()) {
397 for (unsigned n = 16; n != 32; ++n) {
398 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
406 //===----------------------------------------------------------------------===//
407 // Stack Frame Processing methods
408 //===----------------------------------------------------------------------===//
410 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
411 const MachineFrameInfo *MFI = MF.getFrameInfo();
413 if (!EnableBasePointer)
416 // When we need stack realignment, we can't address the stack from the frame
417 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
418 // can't address variables from the stack pointer. MS inline asm can
419 // reference locals while also adjusting the stack pointer. When we can't
420 // use both the SP and the FP, we need a separate base pointer register.
421 bool CantUseFP = needsStackRealignment(MF);
423 MFI->hasVarSizedObjects() || MFI->hasInlineAsmWithSPAdjust();
424 return CantUseFP && CantUseSP;
427 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
428 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
431 const MachineFrameInfo *MFI = MF.getFrameInfo();
432 const MachineRegisterInfo *MRI = &MF.getRegInfo();
434 // Stack realignment requires a frame pointer. If we already started
435 // register allocation with frame pointer elimination, it is too late now.
436 if (!MRI->canReserveReg(FramePtr))
439 // If a base pointer is necessary. Check that it isn't too late to reserve
441 if (MFI->hasVarSizedObjects())
442 return MRI->canReserveReg(BasePtr);
446 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
447 const MachineFrameInfo *MFI = MF.getFrameInfo();
448 const Function *F = MF.getFunction();
449 unsigned StackAlign =
450 MF.getSubtarget().getFrameLowering()->getStackAlignment();
451 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
452 F->hasFnAttribute(Attribute::StackAlignment));
454 // If we've requested that we force align the stack do so now.
456 return canRealignStack(MF);
458 return requiresRealignment && canRealignStack(MF);
461 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
462 unsigned Reg, int &FrameIdx) const {
463 // Since X86 defines assignCalleeSavedSpillSlots which always return true
464 // this function neither used nor tested.
465 llvm_unreachable("Unused function on X86. Otherwise need a test case.");
469 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
470 int SPAdj, unsigned FIOperandNum,
471 RegScavenger *RS) const {
472 MachineInstr &MI = *II;
473 MachineFunction &MF = *MI.getParent()->getParent();
474 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
475 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
478 unsigned Opc = MI.getOpcode();
479 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
480 if (hasBasePointer(MF))
481 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
482 else if (needsStackRealignment(MF))
483 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
487 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
489 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
490 // register as source operand, semantic is the same and destination is
491 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
492 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
493 BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64, false);
495 // This must be part of a four operand memory reference. Replace the
496 // FrameIndex with base register with EBP. Add an offset to the offset.
497 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
499 // Now add the frame object offset to the offset from EBP.
502 // Tail call jmp happens after FP is popped.
503 const MachineFrameInfo *MFI = MF.getFrameInfo();
504 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
506 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
508 if (BasePtr == StackPtr)
511 // The frame index format for stackmaps and patchpoints is different from the
512 // X86 format. It only has a FI and an offset.
513 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
514 assert(BasePtr == FramePtr && "Expected the FP as base register");
515 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
516 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
520 if (MI.getOperand(FIOperandNum+3).isImm()) {
521 // Offset is a 32-bit integer.
522 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
523 int Offset = FIOffset + Imm;
524 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
525 "Requesting 64-bit offset in 32-bit immediate!");
526 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
528 // Offset is symbolic. This is extremely rare.
529 uint64_t Offset = FIOffset +
530 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
531 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
535 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
536 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
537 return TFI->hasFP(MF) ? FramePtr : StackPtr;
540 unsigned X86RegisterInfo::getPtrSizedFrameRegister(
541 const MachineFunction &MF) const {
542 unsigned FrameReg = getFrameRegister(MF);
543 if (Subtarget.isTarget64BitILP32())
544 FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
549 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
552 default: llvm_unreachable("Unexpected VT");
556 default: return getX86SubSuperRegister(Reg, MVT::i64);
557 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
559 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
561 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
563 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
565 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
567 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
569 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
571 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
576 default: llvm_unreachable("Unexpected register");
577 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
579 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
581 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
583 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
585 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
587 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
589 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
591 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
593 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
595 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
597 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
599 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
601 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
603 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
605 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
607 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
613 default: llvm_unreachable("Unexpected register");
614 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
616 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
618 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
620 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
622 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
624 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
626 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
628 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
630 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
632 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
634 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
636 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
638 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
640 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
642 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
644 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
649 default: llvm_unreachable("Unexpected register");
650 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
652 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
654 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
656 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
658 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
660 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
662 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
664 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
666 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
668 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
670 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
672 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
674 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
676 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
678 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
680 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
685 default: llvm_unreachable("Unexpected register");
686 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
688 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
690 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
692 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
694 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
696 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
698 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
700 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
702 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
704 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
706 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
708 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
710 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
712 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
714 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
716 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
722 unsigned get512BitSuperRegister(unsigned Reg) {
723 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
724 return X86::ZMM0 + (Reg - X86::XMM0);
725 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
726 return X86::ZMM0 + (Reg - X86::YMM0);
727 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
729 llvm_unreachable("Unexpected SIMD register");