1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "Support/CommandLine.h"
27 #include "Support/STLExtras.h"
32 NoFPElim("disable-fp-elim",
33 cl::desc("Disable frame pointer elimination optimization"));
35 NoFusing("disable-spill-fusing",
36 cl::desc("Disable fusing of spill code into instructions"));
38 PrintFailedFusing("print-failed-fuse-candidates",
39 cl::desc("Print instructions that the allocator wants to"
40 " fuse, but the X86 backend currently can't"),
44 X86RegisterInfo::X86RegisterInfo()
45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
47 static unsigned getIdx(const TargetRegisterClass *RC) {
48 switch (RC->getSize()) {
49 default: assert(0 && "Invalid data size!");
57 int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MI,
59 unsigned SrcReg, int FrameIdx,
60 const TargetRegisterClass *RC) const {
61 static const unsigned Opcode[] =
62 { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FSTP80m };
63 MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
64 FrameIdx).addReg(SrcReg);
69 int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator MI,
71 unsigned DestReg, int FrameIdx,
72 const TargetRegisterClass *RC) const{
73 static const unsigned Opcode[] =
74 { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD80m };
75 unsigned OC = Opcode[getIdx(RC)];
76 MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
80 int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MI,
82 unsigned DestReg, unsigned SrcReg,
83 const TargetRegisterClass *RC) const {
84 static const unsigned Opcode[] =
85 { X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV };
86 MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
90 static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
92 return addFrameReference(BuildMI(Opcode, 4), FrameIndex);
95 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
97 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
98 .addReg(MI->getOperand(1).getReg());
101 static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
103 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
104 .addReg(MI->getOperand(1).getReg())
105 .addZImm(MI->getOperand(2).getImmedValue());
108 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
110 if (MI->getOperand(1).isImmediate())
111 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
112 .addZImm(MI->getOperand(1).getImmedValue());
113 else if (MI->getOperand(1).isGlobalAddress())
114 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
115 .addGlobalAddress(MI->getOperand(1).getGlobal());
116 assert(0 && "Unknown operand for MakeMI!");
120 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
122 const MachineOperand& op = MI->getOperand(0);
123 return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
127 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
129 const MachineOperand& op = MI->getOperand(0);
130 return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
131 FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
135 bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI,
136 unsigned i, int FrameIndex) const {
137 if (NoFusing) return false;
139 /// FIXME: This should obviously be autogenerated by tablegen when patterns
141 MachineBasicBlock& MBB = *MI->getParent();
142 MachineInstr* NI = 0;
144 switch(MI->getOpcode()) {
145 case X86::XCHG8rr: NI = MakeMRInst(X86::XCHG8mr ,FrameIndex, MI); break;
146 case X86::XCHG16rr:NI = MakeMRInst(X86::XCHG16mr,FrameIndex, MI); break;
147 case X86::XCHG32rr:NI = MakeMRInst(X86::XCHG32mr,FrameIndex, MI); break;
148 case X86::MOV8rr: NI = MakeMRInst(X86::MOV8mr , FrameIndex, MI); break;
149 case X86::MOV16rr: NI = MakeMRInst(X86::MOV16mr, FrameIndex, MI); break;
150 case X86::MOV32rr: NI = MakeMRInst(X86::MOV32mr, FrameIndex, MI); break;
151 case X86::MOV8ri: NI = MakeMIInst(X86::MOV8mi , FrameIndex, MI); break;
152 case X86::MOV16ri: NI = MakeMIInst(X86::MOV16mi, FrameIndex, MI); break;
153 case X86::MOV32ri: NI = MakeMIInst(X86::MOV32mi, FrameIndex, MI); break;
154 case X86::MUL8r: NI = MakeMInst( X86::MUL8m , FrameIndex, MI); break;
155 case X86::MUL16r: NI = MakeMInst( X86::MUL16m, FrameIndex, MI); break;
156 case X86::MUL32r: NI = MakeMInst( X86::MUL32m, FrameIndex, MI); break;
157 case X86::DIV8r: NI = MakeMInst( X86::DIV8m , FrameIndex, MI); break;
158 case X86::DIV16r: NI = MakeMInst( X86::DIV16m, FrameIndex, MI); break;
159 case X86::DIV32r: NI = MakeMInst( X86::DIV32m, FrameIndex, MI); break;
160 case X86::IDIV8r: NI = MakeMInst( X86::IDIV8m , FrameIndex, MI); break;
161 case X86::IDIV16r: NI = MakeMInst( X86::IDIV16m, FrameIndex, MI); break;
162 case X86::IDIV32r: NI = MakeMInst( X86::IDIV32m, FrameIndex, MI); break;
163 case X86::NEG8r: NI = MakeMInst( X86::NEG8m , FrameIndex, MI); break;
164 case X86::NEG16r: NI = MakeMInst( X86::NEG16m, FrameIndex, MI); break;
165 case X86::NEG32r: NI = MakeMInst( X86::NEG32m, FrameIndex, MI); break;
166 case X86::NOT8r: NI = MakeMInst( X86::NOT8m , FrameIndex, MI); break;
167 case X86::NOT16r: NI = MakeMInst( X86::NOT16m, FrameIndex, MI); break;
168 case X86::NOT32r: NI = MakeMInst( X86::NOT32m, FrameIndex, MI); break;
169 case X86::INC8r: NI = MakeMInst( X86::INC8m , FrameIndex, MI); break;
170 case X86::INC16r: NI = MakeMInst( X86::INC16m, FrameIndex, MI); break;
171 case X86::INC32r: NI = MakeMInst( X86::INC32m, FrameIndex, MI); break;
172 case X86::DEC8r: NI = MakeMInst( X86::DEC8m , FrameIndex, MI); break;
173 case X86::DEC16r: NI = MakeMInst( X86::DEC16m, FrameIndex, MI); break;
174 case X86::DEC32r: NI = MakeMInst( X86::DEC32m, FrameIndex, MI); break;
175 case X86::ADD8rr: NI = MakeMRInst(X86::ADD8mr , FrameIndex, MI); break;
176 case X86::ADD16rr: NI = MakeMRInst(X86::ADD16mr, FrameIndex, MI); break;
177 case X86::ADD32rr: NI = MakeMRInst(X86::ADD32mr, FrameIndex, MI); break;
178 case X86::ADC32rr: NI = MakeMRInst(X86::ADC32mr, FrameIndex, MI); break;
179 case X86::ADD8ri: NI = MakeMIInst(X86::ADD8mi , FrameIndex, MI); break;
180 case X86::ADD16ri: NI = MakeMIInst(X86::ADD16mi, FrameIndex, MI); break;
181 case X86::ADD32ri: NI = MakeMIInst(X86::ADD32mi, FrameIndex, MI); break;
182 case X86::SUB8rr: NI = MakeMRInst(X86::SUB8mr , FrameIndex, MI); break;
183 case X86::SUB16rr: NI = MakeMRInst(X86::SUB16mr, FrameIndex, MI); break;
184 case X86::SUB32rr: NI = MakeMRInst(X86::SUB32mr, FrameIndex, MI); break;
185 case X86::SBB32rr: NI = MakeMRInst(X86::SBB32mr, FrameIndex, MI); break;
186 case X86::SUB8ri: NI = MakeMIInst(X86::SUB8mi , FrameIndex, MI); break;
187 case X86::SUB16ri: NI = MakeMIInst(X86::SUB16mi, FrameIndex, MI); break;
188 case X86::SUB32ri: NI = MakeMIInst(X86::SUB32mi, FrameIndex, MI); break;
189 case X86::AND8rr: NI = MakeMRInst(X86::AND8mr , FrameIndex, MI); break;
190 case X86::AND16rr: NI = MakeMRInst(X86::AND16mr, FrameIndex, MI); break;
191 case X86::AND32rr: NI = MakeMRInst(X86::AND32mr, FrameIndex, MI); break;
192 case X86::AND8ri: NI = MakeMIInst(X86::AND8mi , FrameIndex, MI); break;
193 case X86::AND16ri: NI = MakeMIInst(X86::AND16mi, FrameIndex, MI); break;
194 case X86::AND32ri: NI = MakeMIInst(X86::AND32mi, FrameIndex, MI); break;
195 case X86::OR8rr: NI = MakeMRInst(X86::OR8mr , FrameIndex, MI); break;
196 case X86::OR16rr: NI = MakeMRInst(X86::OR16mr, FrameIndex, MI); break;
197 case X86::OR32rr: NI = MakeMRInst(X86::OR32mr, FrameIndex, MI); break;
198 case X86::OR8ri: NI = MakeMIInst(X86::OR8mi , FrameIndex, MI); break;
199 case X86::OR16ri: NI = MakeMIInst(X86::OR16mi, FrameIndex, MI); break;
200 case X86::OR32ri: NI = MakeMIInst(X86::OR32mi, FrameIndex, MI); break;
201 case X86::XOR8rr: NI = MakeMRInst(X86::XOR8mr , FrameIndex, MI); break;
202 case X86::XOR16rr: NI = MakeMRInst(X86::XOR16mr, FrameIndex, MI); break;
203 case X86::XOR32rr: NI = MakeMRInst(X86::XOR32mr, FrameIndex, MI); break;
204 case X86::XOR8ri: NI = MakeMIInst(X86::XOR8mi , FrameIndex, MI); break;
205 case X86::XOR16ri: NI = MakeMIInst(X86::XOR16mi, FrameIndex, MI); break;
206 case X86::XOR32ri: NI = MakeMIInst(X86::XOR32mi, FrameIndex, MI); break;
207 case X86::SHL8rCL: NI = MakeMInst( X86::SHL8mCL ,FrameIndex, MI); break;
208 case X86::SHL16rCL:NI = MakeMInst( X86::SHL16mCL,FrameIndex, MI); break;
209 case X86::SHL32rCL:NI = MakeMInst( X86::SHL32mCL,FrameIndex, MI); break;
210 case X86::SHL8ri: NI = MakeMIInst(X86::SHL8mi , FrameIndex, MI); break;
211 case X86::SHL16ri: NI = MakeMIInst(X86::SHL16mi, FrameIndex, MI); break;
212 case X86::SHL32ri: NI = MakeMIInst(X86::SHL32mi, FrameIndex, MI); break;
213 case X86::SHR8rCL: NI = MakeMInst( X86::SHR8mCL ,FrameIndex, MI); break;
214 case X86::SHR16rCL:NI = MakeMInst( X86::SHR16mCL,FrameIndex, MI); break;
215 case X86::SHR32rCL:NI = MakeMInst( X86::SHR32mCL,FrameIndex, MI); break;
216 case X86::SHR8ri: NI = MakeMIInst(X86::SHR8mi , FrameIndex, MI); break;
217 case X86::SHR16ri: NI = MakeMIInst(X86::SHR16mi, FrameIndex, MI); break;
218 case X86::SHR32ri: NI = MakeMIInst(X86::SHR32mi, FrameIndex, MI); break;
219 case X86::SAR8rCL: NI = MakeMInst( X86::SAR8mCL ,FrameIndex, MI); break;
220 case X86::SAR16rCL:NI = MakeMInst( X86::SAR16mCL,FrameIndex, MI); break;
221 case X86::SAR32rCL:NI = MakeMInst( X86::SAR32mCL,FrameIndex, MI); break;
222 case X86::SAR8ri: NI = MakeMIInst(X86::SAR8mi , FrameIndex, MI); break;
223 case X86::SAR16ri: NI = MakeMIInst(X86::SAR16mi, FrameIndex, MI); break;
224 case X86::SAR32ri: NI = MakeMIInst(X86::SAR32mi, FrameIndex, MI); break;
225 case X86::SHLD32rrCL:NI = MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);break;
226 case X86::SHLD32rri8:NI = MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);break;
227 case X86::SHRD32rrCL:NI = MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);break;
228 case X86::SHRD32rri8:NI = MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI);break;
229 case X86::SETBr: NI = MakeMInst( X86::SETBm, FrameIndex, MI); break;
230 case X86::SETAEr: NI = MakeMInst( X86::SETAEm, FrameIndex, MI); break;
231 case X86::SETEr: NI = MakeMInst( X86::SETEm, FrameIndex, MI); break;
232 case X86::SETNEr: NI = MakeMInst( X86::SETNEm, FrameIndex, MI); break;
233 case X86::SETBEr: NI = MakeMInst( X86::SETBEm, FrameIndex, MI); break;
234 case X86::SETAr: NI = MakeMInst( X86::SETAm, FrameIndex, MI); break;
235 case X86::SETSr: NI = MakeMInst( X86::SETSm, FrameIndex, MI); break;
236 case X86::SETNSr: NI = MakeMInst( X86::SETNSm, FrameIndex, MI); break;
237 case X86::SETLr: NI = MakeMInst( X86::SETLm, FrameIndex, MI); break;
238 case X86::SETGEr: NI = MakeMInst( X86::SETGEm, FrameIndex, MI); break;
239 case X86::SETLEr: NI = MakeMInst( X86::SETLEm, FrameIndex, MI); break;
240 case X86::SETGr: NI = MakeMInst( X86::SETGm, FrameIndex, MI); break;
241 case X86::TEST8rr: NI = MakeMRInst(X86::TEST8mr ,FrameIndex, MI); break;
242 case X86::TEST16rr:NI = MakeMRInst(X86::TEST16mr,FrameIndex, MI); break;
243 case X86::TEST32rr:NI = MakeMRInst(X86::TEST32mr,FrameIndex, MI); break;
244 case X86::TEST8ri: NI = MakeMIInst(X86::TEST8mi ,FrameIndex, MI); break;
245 case X86::TEST16ri:NI = MakeMIInst(X86::TEST16mi,FrameIndex, MI); break;
246 case X86::TEST32ri:NI = MakeMIInst(X86::TEST32mi,FrameIndex, MI); break;
247 case X86::CMP8rr: NI = MakeMRInst(X86::CMP8mr , FrameIndex, MI); break;
248 case X86::CMP16rr: NI = MakeMRInst(X86::CMP16mr, FrameIndex, MI); break;
249 case X86::CMP32rr: NI = MakeMRInst(X86::CMP32mr, FrameIndex, MI); break;
250 case X86::CMP8ri: NI = MakeMIInst(X86::CMP8mi , FrameIndex, MI); break;
251 case X86::CMP16ri: NI = MakeMIInst(X86::CMP16mi, FrameIndex, MI); break;
252 case X86::CMP32ri: NI = MakeMIInst(X86::CMP32mi, FrameIndex, MI); break;
253 default: break; // Cannot fold
256 switch(MI->getOpcode()) {
257 case X86::XCHG8rr: NI = MakeRMInst(X86::XCHG8rm ,FrameIndex, MI); break;
258 case X86::XCHG16rr:NI = MakeRMInst(X86::XCHG16rm,FrameIndex, MI); break;
259 case X86::XCHG32rr:NI = MakeRMInst(X86::XCHG32rm,FrameIndex, MI); break;
260 case X86::MOV8rr: NI = MakeRMInst(X86::MOV8rm , FrameIndex, MI); break;
261 case X86::MOV16rr: NI = MakeRMInst(X86::MOV16rm, FrameIndex, MI); break;
262 case X86::MOV32rr: NI = MakeRMInst(X86::MOV32rm, FrameIndex, MI); break;
263 case X86::ADD8rr: NI = MakeRMInst(X86::ADD8rm , FrameIndex, MI); break;
264 case X86::ADD16rr: NI = MakeRMInst(X86::ADD16rm, FrameIndex, MI); break;
265 case X86::ADD32rr: NI = MakeRMInst(X86::ADD32rm, FrameIndex, MI); break;
266 case X86::ADC32rr: NI = MakeRMInst(X86::ADC32rm, FrameIndex, MI); break;
267 case X86::SUB8rr: NI = MakeRMInst(X86::SUB8rm , FrameIndex, MI); break;
268 case X86::SUB16rr: NI = MakeRMInst(X86::SUB16rm, FrameIndex, MI); break;
269 case X86::SUB32rr: NI = MakeRMInst(X86::SUB32rm, FrameIndex, MI); break;
270 case X86::SBB32rr: NI = MakeRMInst(X86::SBB32rm, FrameIndex, MI); break;
271 case X86::AND8rr: NI = MakeRMInst(X86::AND8rm , FrameIndex, MI); break;
272 case X86::AND16rr: NI = MakeRMInst(X86::AND16rm, FrameIndex, MI); break;
273 case X86::AND32rr: NI = MakeRMInst(X86::AND32rm, FrameIndex, MI); break;
274 case X86::OR8rr: NI = MakeRMInst(X86::OR8rm , FrameIndex, MI); break;
275 case X86::OR16rr: NI = MakeRMInst(X86::OR16rm, FrameIndex, MI); break;
276 case X86::OR32rr: NI = MakeRMInst(X86::OR32rm, FrameIndex, MI); break;
277 case X86::XOR8rr: NI = MakeRMInst(X86::XOR8rm , FrameIndex, MI); break;
278 case X86::XOR16rr: NI = MakeRMInst(X86::XOR16rm, FrameIndex, MI); break;
279 case X86::XOR32rr: NI = MakeRMInst(X86::XOR32rm, FrameIndex, MI); break;
280 case X86::TEST8rr: NI = MakeRMInst(X86::TEST8rm ,FrameIndex, MI); break;
281 case X86::TEST16rr:NI = MakeRMInst(X86::TEST16rm,FrameIndex, MI); break;
282 case X86::TEST32rr:NI = MakeRMInst(X86::TEST32rm,FrameIndex, MI); break;
283 case X86::IMUL16rr:NI = MakeRMInst(X86::IMUL16rm,FrameIndex, MI); break;
284 case X86::IMUL32rr:NI = MakeRMInst(X86::IMUL32rm,FrameIndex, MI); break;
285 case X86::IMUL16rri: NI = MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);break;
286 case X86::IMUL32rri: NI = MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI);break;
287 case X86::CMP8rr: NI = MakeRMInst(X86::CMP8rm , FrameIndex, MI); break;
288 case X86::CMP16rr: NI = MakeRMInst(X86::CMP16rm, FrameIndex, MI); break;
289 case X86::CMP32rr: NI = MakeRMInst(X86::CMP32rm, FrameIndex, MI); break;
290 case X86::MOVSX16rr8: NI = MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI); break;
291 case X86::MOVSX32rr8: NI = MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI); break;
292 case X86::MOVSX32rr16:NI = MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI); break;
293 case X86::MOVZX16rr8: NI = MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI); break;
294 case X86::MOVZX32rr8: NI = MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI); break;
295 case X86::MOVZX32rr16:NI = MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI); break;
300 MI = MBB.insert(MBB.erase(MI), NI);
303 if (PrintFailedFusing)
304 std::cerr << "We failed to fuse: " << *MI;
309 //===----------------------------------------------------------------------===//
310 // Stack Frame Processing methods
311 //===----------------------------------------------------------------------===//
313 // hasFP - Return true if the specified function should have a dedicated frame
314 // pointer register. This is true if the function has variable sized allocas or
315 // if frame pointer elimination is disabled.
317 static bool hasFP(MachineFunction &MF) {
318 return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
321 void X86RegisterInfo::
322 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
323 MachineBasicBlock::iterator I) const {
325 // If we have a frame pointer, turn the adjcallstackup instruction into a
326 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
328 MachineInstr *Old = I;
329 unsigned Amount = Old->getOperand(0).getImmedValue();
331 // We need to keep the stack aligned properly. To do this, we round the
332 // amount of space needed for the outgoing arguments up to the next
333 // alignment boundary.
334 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
335 Amount = (Amount+Align-1)/Align*Align;
338 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
339 New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
342 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
343 New=BuildMI(X86::ADD32ri, 1, X86::ESP, MachineOperand::UseAndDef)
347 // Replace the pseudo instruction with a new instruction...
355 void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
356 MachineBasicBlock::iterator II) const {
358 MachineInstr &MI = *II;
359 while (!MI.getOperand(i).isFrameIndex()) {
361 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
364 int FrameIndex = MI.getOperand(i).getFrameIndex();
366 // This must be part of a four operand memory reference. Replace the
367 // FrameIndex with base register with EBP. Add add an offset to the offset.
368 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
370 // Now add the frame object offset to the offset from EBP.
371 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
372 MI.getOperand(i+3).getImmedValue()+4;
375 Offset += MF.getFrameInfo()->getStackSize();
377 Offset += 4; // Skip the saved EBP
379 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
383 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
385 // Create a frame entry for the EBP register that must be saved.
386 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
387 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
388 "Slot for EBP register must be last in order to be found!");
392 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
393 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
394 MachineBasicBlock::iterator MBBI = MBB.begin();
395 MachineFrameInfo *MFI = MF.getFrameInfo();
398 // Get the number of bytes to allocate from the FrameInfo
399 unsigned NumBytes = MFI->getStackSize();
401 // Get the offset of the stack slot for the EBP register... which is
402 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
403 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
405 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
406 MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
408 MBB.insert(MBBI, MI);
411 // Save EBP into the appropriate stack slot...
412 MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP
413 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
414 MBB.insert(MBBI, MI);
416 // Update EBP with the new base value...
417 if (NumBytes == 4) // mov EBP, ESP
418 MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
419 else // lea EBP, [ESP+StackSize]
420 MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
422 MBB.insert(MBBI, MI);
425 if (MFI->hasCalls()) {
426 // When we have no frame pointer, we reserve argument space for call sites
427 // in the function immediately on entry to the current function. This
428 // eliminates the need for add/sub ESP brackets around call sites.
430 NumBytes += MFI->getMaxCallFrameSize();
432 // Round the size to a multiple of the alignment (don't forget the 4 byte
434 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
435 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
438 // Update frame info to pretend that this is part of the stack...
439 MFI->setStackSize(NumBytes);
442 // adjust stack pointer: ESP -= numbytes
443 MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
445 MBB.insert(MBBI, MI);
450 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
451 MachineBasicBlock &MBB) const {
452 const MachineFrameInfo *MFI = MF.getFrameInfo();
453 MachineBasicBlock::iterator MBBI = prior(MBB.end());
455 assert(MBBI->getOpcode() == X86::RET &&
456 "Can only insert epilog into returning blocks");
459 // Get the offset of the stack slot for the EBP register... which is
460 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
461 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
464 MI = BuildMI(X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP);
465 MBB.insert(MBBI, MI);
468 MI = BuildMI(X86::POP32r, 0, X86::EBP);
469 MBB.insert(MBBI, MI);
471 // Get the number of bytes allocated from the FrameInfo...
472 unsigned NumBytes = MFI->getStackSize();
474 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
475 MI =BuildMI(X86::ADD32ri, 1, X86::ESP, MachineOperand::UseAndDef)
477 MBB.insert(MBBI, MI);
482 #include "X86GenRegisterInfo.inc"
484 const TargetRegisterClass*
485 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
486 switch (Ty->getPrimitiveID()) {
488 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
489 default: assert(0 && "Invalid type to getClass!");
491 case Type::SByteTyID:
492 case Type::UByteTyID: return &R8Instance;
493 case Type::ShortTyID:
494 case Type::UShortTyID: return &R16Instance;
497 case Type::PointerTyID: return &R32Instance;
499 case Type::FloatTyID:
500 case Type::DoubleTyID: return &RFPInstance;