1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "Support/CommandLine.h"
27 #include "Support/STLExtras.h"
32 NoFPElim("disable-fp-elim",
33 cl::desc("Disable frame pointer elimination optimization"));
35 NoFusing("disable-spill-fusing",
36 cl::desc("Disable fusing of spill code into instructions"));
39 X86RegisterInfo::X86RegisterInfo()
40 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
42 static unsigned getIdx(const TargetRegisterClass *RC) {
43 switch (RC->getSize()) {
44 default: assert(0 && "Invalid data size!");
52 int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MI,
54 unsigned SrcReg, int FrameIdx,
55 const TargetRegisterClass *RC) const {
56 static const unsigned Opcode[] =
57 { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTPr80 };
58 MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
59 FrameIdx).addReg(SrcReg);
64 int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI,
66 unsigned DestReg, int FrameIdx,
67 const TargetRegisterClass *RC) const{
68 static const unsigned Opcode[] =
69 { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDr80 };
70 unsigned OC = Opcode[getIdx(RC)];
71 MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
75 int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator MI,
77 unsigned DestReg, unsigned SrcReg,
78 const TargetRegisterClass *RC) const {
79 static const unsigned Opcode[] =
80 { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
81 MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
85 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
87 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
88 .addReg(MI->getOperand(1).getReg());
91 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
93 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
94 .addZImm(MI->getOperand(1).getImmedValue());
97 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
99 return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
103 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
105 return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
106 FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
110 bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI,
111 unsigned i, int FrameIndex) const {
112 if (NoFusing) return false;
114 /// FIXME: This should obviously be autogenerated by tablegen when patterns
116 MachineBasicBlock& MBB = *MI->getParent();
117 MachineInstr* NI = 0;
119 switch(MI->getOpcode()) {
120 case X86::MOVrr8: NI = MakeMRInst(X86::MOVmr8 , FrameIndex, MI); break;
121 case X86::MOVrr16: NI = MakeMRInst(X86::MOVmr16, FrameIndex, MI); break;
122 case X86::MOVrr32: NI = MakeMRInst(X86::MOVmr32, FrameIndex, MI); break;
123 case X86::ADDrr8: NI = MakeMRInst(X86::ADDmr8 , FrameIndex, MI); break;
124 case X86::ADDrr16: NI = MakeMRInst(X86::ADDmr16, FrameIndex, MI); break;
125 case X86::ADDrr32: NI = MakeMRInst(X86::ADDmr32, FrameIndex, MI); break;
126 case X86::ADDri8: NI = MakeMIInst(X86::ADDmi8 , FrameIndex, MI); break;
127 case X86::ADDri16: NI = MakeMIInst(X86::ADDmi16, FrameIndex, MI); break;
128 case X86::ADDri32: NI = MakeMIInst(X86::ADDmi32, FrameIndex, MI); break;
129 case X86::ANDrr8: NI = MakeMRInst(X86::ANDmr8 , FrameIndex, MI); break;
130 case X86::ANDrr16: NI = MakeMRInst(X86::ANDmr16, FrameIndex, MI); break;
131 case X86::ANDrr32: NI = MakeMRInst(X86::ANDmr32, FrameIndex, MI); break;
132 case X86::ANDri8: NI = MakeMIInst(X86::ANDmi8 , FrameIndex, MI); break;
133 case X86::ANDri16: NI = MakeMIInst(X86::ANDmi16, FrameIndex, MI); break;
134 case X86::ANDri32: NI = MakeMIInst(X86::ANDmi32, FrameIndex, MI); break;
135 default: return false; // Cannot fold
138 switch(MI->getOpcode()) {
139 case X86::MOVrr8: NI = MakeRMInst(X86::MOVrm8 , FrameIndex, MI); break;
140 case X86::MOVrr16: NI = MakeRMInst(X86::MOVrm16, FrameIndex, MI); break;
141 case X86::MOVrr32: NI = MakeRMInst(X86::MOVrm32, FrameIndex, MI); break;
142 case X86::ADDrr8: NI = MakeRMInst(X86::ADDrm8 , FrameIndex, MI); break;
143 case X86::ADDrr16: NI = MakeRMInst(X86::ADDrm16, FrameIndex, MI); break;
144 case X86::ADDrr32: NI = MakeRMInst(X86::ADDrm32, FrameIndex, MI); break;
145 case X86::ANDrr8: NI = MakeRMInst(X86::ANDrm8 , FrameIndex, MI); break;
146 case X86::ANDrr16: NI = MakeRMInst(X86::ANDrm16, FrameIndex, MI); break;
147 case X86::ANDrr32: NI = MakeRMInst(X86::ANDrm32, FrameIndex, MI); break;
148 case X86::IMULrr16:NI = MakeRMInst(X86::IMULrm16, FrameIndex, MI); break;
149 case X86::IMULrr32:NI = MakeRMInst(X86::IMULrm32, FrameIndex, MI); break;
150 case X86::IMULrri16: NI = MakeRMIInst(X86::IMULrmi16, FrameIndex, MI); break;
151 case X86::IMULrri32: NI = MakeRMIInst(X86::IMULrmi32, FrameIndex, MI); break;
152 default: return false; // cannot fold.
155 return false; // cannot fold.
158 MI = MBB.insert(MBB.erase(MI), NI);
162 //===----------------------------------------------------------------------===//
163 // Stack Frame Processing methods
164 //===----------------------------------------------------------------------===//
166 // hasFP - Return true if the specified function should have a dedicated frame
167 // pointer register. This is true if the function has variable sized allocas or
168 // if frame pointer elimination is disabled.
170 static bool hasFP(MachineFunction &MF) {
171 return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
174 void X86RegisterInfo::
175 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
176 MachineBasicBlock::iterator I) const {
178 // If we have a frame pointer, turn the adjcallstackup instruction into a
179 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
181 MachineInstr *Old = I;
182 unsigned Amount = Old->getOperand(0).getImmedValue();
184 // We need to keep the stack aligned properly. To do this, we round the
185 // amount of space needed for the outgoing arguments up to the next
186 // alignment boundary.
187 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
188 Amount = (Amount+Align-1)/Align*Align;
191 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
192 New=BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
194 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
195 New=BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
198 // Replace the pseudo instruction with a new instruction...
206 void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
207 MachineBasicBlock::iterator II) const {
209 MachineInstr &MI = *II;
210 while (!MI.getOperand(i).isFrameIndex()) {
212 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
215 int FrameIndex = MI.getOperand(i).getFrameIndex();
217 // This must be part of a four operand memory reference. Replace the
218 // FrameIndex with base register with EBP. Add add an offset to the offset.
219 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
221 // Now add the frame object offset to the offset from EBP.
222 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
223 MI.getOperand(i+3).getImmedValue()+4;
226 Offset += MF.getFrameInfo()->getStackSize();
228 Offset += 4; // Skip the saved EBP
230 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
234 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
236 // Create a frame entry for the EBP register that must be saved.
237 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
238 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
239 "Slot for EBP register must be last in order to be found!");
243 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
244 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
245 MachineBasicBlock::iterator MBBI = MBB.begin();
246 MachineFrameInfo *MFI = MF.getFrameInfo();
249 // Get the number of bytes to allocate from the FrameInfo
250 unsigned NumBytes = MFI->getStackSize();
252 // Get the offset of the stack slot for the EBP register... which is
253 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
254 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
256 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
257 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
258 MBB.insert(MBBI, MI);
261 // Save EBP into the appropriate stack slot...
262 MI = addRegOffset(BuildMI(X86::MOVmr32, 5), // mov [ESP-<offset>], EBP
263 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
264 MBB.insert(MBBI, MI);
266 // Update EBP with the new base value...
267 if (NumBytes == 4) // mov EBP, ESP
268 MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
269 else // lea EBP, [ESP+StackSize]
270 MI = addRegOffset(BuildMI(X86::LEAr32, 5, X86::EBP), X86::ESP,NumBytes-4);
272 MBB.insert(MBBI, MI);
275 if (MFI->hasCalls()) {
276 // When we have no frame pointer, we reserve argument space for call sites
277 // in the function immediately on entry to the current function. This
278 // eliminates the need for add/sub ESP brackets around call sites.
280 NumBytes += MFI->getMaxCallFrameSize();
282 // Round the size to a multiple of the alignment (don't forget the 4 byte
284 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
285 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
288 // Update frame info to pretend that this is part of the stack...
289 MFI->setStackSize(NumBytes);
292 // adjust stack pointer: ESP -= numbytes
293 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
294 MBB.insert(MBBI, MI);
299 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
300 MachineBasicBlock &MBB) const {
301 const MachineFrameInfo *MFI = MF.getFrameInfo();
302 MachineBasicBlock::iterator MBBI = prior(MBB.end());
304 assert(MBBI->getOpcode() == X86::RET &&
305 "Can only insert epilog into returning blocks");
308 // Get the offset of the stack slot for the EBP register... which is
309 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
310 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
313 MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
314 MBB.insert(MBBI, MI);
317 MI = BuildMI(X86::POPr32, 0, X86::EBP);
318 MBB.insert(MBBI, MI);
320 // Get the number of bytes allocated from the FrameInfo...
321 unsigned NumBytes = MFI->getStackSize();
323 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
324 MI =BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
325 MBB.insert(MBBI, MI);
330 #include "X86GenRegisterInfo.inc"
332 const TargetRegisterClass*
333 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
334 switch (Ty->getPrimitiveID()) {
336 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
337 default: assert(0 && "Invalid type to getClass!");
339 case Type::SByteTyID:
340 case Type::UByteTyID: return &R8Instance;
341 case Type::ShortTyID:
342 case Type::UShortTyID: return &R16Instance;
345 case Type::PointerTyID: return &R32Instance;
347 case Type::FloatTyID:
348 case Type::DoubleTyID: return &RFPInstance;