1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/ErrorHandling.h"
44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45 const TargetInstrInfo &tii)
46 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47 X86::ADJCALLSTACKDOWN64 :
48 X86::ADJCALLSTACKDOWN32,
49 tm.getSubtarget<X86Subtarget>().is64Bit() ?
50 X86::ADJCALLSTACKUP64 :
51 X86::ADJCALLSTACKUP32),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
56 IsWin64 = Subtarget->isTargetWin64();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 // getDwarfRegNum - This function maps LLVM register identifiers to the
70 // Dwarf specific numbering, used in debug info and exception tables.
72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74 unsigned Flavour = DWARFFlavour::X86_64;
75 if (!Subtarget->is64Bit()) {
76 if (Subtarget->isTargetDarwin()) {
78 Flavour = DWARFFlavour::X86_32_DarwinEH;
80 Flavour = DWARFFlavour::X86_32_Generic;
81 } else if (Subtarget->isTargetCygMing()) {
82 // Unsupported by now, just quick fallback
83 Flavour = DWARFFlavour::X86_32_Generic;
85 Flavour = DWARFFlavour::X86_32_Generic;
89 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
92 // getX86RegNum - This function maps LLVM register identifiers to their X86
93 // specific numbering, which is used in various places encoding instructions.
95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
97 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
103 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
105 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
107 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
114 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
116 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
120 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
122 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
124 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129 return RegNo-X86::ST0;
131 case X86::XMM0: case X86::XMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9: case X86::MM1:
135 case X86::XMM2: case X86::XMM10: case X86::MM2:
137 case X86::XMM3: case X86::XMM11: case X86::MM3:
139 case X86::XMM4: case X86::XMM12: case X86::MM4:
141 case X86::XMM5: case X86::XMM13: case X86::MM5:
143 case X86::XMM6: case X86::XMM14: case X86::MM6:
145 case X86::XMM7: case X86::XMM15: case X86::MM7:
149 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
155 const TargetRegisterClass *
156 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157 const TargetRegisterClass *B,
158 unsigned SubIdx) const {
163 if (B == &X86::GR8RegClass) {
164 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
166 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168 A == &X86::GR64_NOREXRegClass)
169 return &X86::GR64_ABCDRegClass;
170 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
171 A == &X86::GR32_NOREXRegClass)
172 return &X86::GR32_ABCDRegClass;
173 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
174 A == &X86::GR16_NOREXRegClass)
175 return &X86::GR16_ABCDRegClass;
176 } else if (B == &X86::GR8_NOREXRegClass) {
177 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
178 return &X86::GR64_NOREXRegClass;
179 else if (A == &X86::GR64_ABCDRegClass)
180 return &X86::GR64_ABCDRegClass;
181 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass)
182 return &X86::GR32_NOREXRegClass;
183 else if (A == &X86::GR32_ABCDRegClass)
184 return &X86::GR32_ABCDRegClass;
185 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
186 return &X86::GR16_NOREXRegClass;
187 else if (A == &X86::GR16_ABCDRegClass)
188 return &X86::GR16_ABCDRegClass;
193 if (B == &X86::GR8_ABCD_HRegClass) {
194 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
195 A == &X86::GR64_NOREXRegClass)
196 return &X86::GR64_ABCDRegClass;
197 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
198 A == &X86::GR32_NOREXRegClass)
199 return &X86::GR32_ABCDRegClass;
200 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
201 A == &X86::GR16_NOREXRegClass)
202 return &X86::GR16_ABCDRegClass;
207 if (B == &X86::GR16RegClass) {
208 if (A->getSize() == 4 || A->getSize() == 8)
210 } else if (B == &X86::GR16_ABCDRegClass) {
211 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
212 A == &X86::GR64_NOREXRegClass)
213 return &X86::GR64_ABCDRegClass;
214 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
215 A == &X86::GR32_NOREXRegClass)
216 return &X86::GR32_ABCDRegClass;
217 } else if (B == &X86::GR16_NOREXRegClass) {
218 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
219 return &X86::GR64_NOREXRegClass;
220 else if (A == &X86::GR64_ABCDRegClass)
221 return &X86::GR64_ABCDRegClass;
222 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass)
223 return &X86::GR32_NOREXRegClass;
224 else if (A == &X86::GR32_ABCDRegClass)
225 return &X86::GR64_ABCDRegClass;
230 if (B == &X86::GR32RegClass) {
231 if (A->getSize() == 8)
233 } else if (B == &X86::GR32_ABCDRegClass) {
234 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
235 A == &X86::GR64_NOREXRegClass)
236 return &X86::GR64_ABCDRegClass;
237 } else if (B == &X86::GR32_NOREXRegClass) {
238 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
239 return &X86::GR64_NOREXRegClass;
240 else if (A == &X86::GR64_ABCDRegClass)
241 return &X86::GR64_ABCDRegClass;
248 const TargetRegisterClass *X86RegisterInfo::
249 getPointerRegClass(unsigned Kind) const {
250 if (TM.getSubtarget<X86Subtarget>().is64Bit())
251 return &X86::GR64RegClass;
252 return &X86::GR32RegClass;
255 const TargetRegisterClass *
256 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
257 if (RC == &X86::CCRRegClass) {
259 return &X86::GR64RegClass;
261 return &X86::GR32RegClass;
267 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
268 bool callsEHReturn = false;
271 const MachineFrameInfo *MFI = MF->getFrameInfo();
272 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
273 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
276 static const unsigned CalleeSavedRegs32Bit[] = {
277 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
280 static const unsigned CalleeSavedRegs32EHRet[] = {
281 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
284 static const unsigned CalleeSavedRegs64Bit[] = {
285 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
288 static const unsigned CalleeSavedRegs64EHRet[] = {
289 X86::RAX, X86::RDX, X86::RBX, X86::R12,
290 X86::R13, X86::R14, X86::R15, X86::RBP, 0
293 static const unsigned CalleeSavedRegsWin64[] = {
294 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
295 X86::R12, X86::R13, X86::R14, X86::R15,
296 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
297 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
298 X86::XMM14, X86::XMM15, 0
303 return CalleeSavedRegsWin64;
305 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
307 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
311 const TargetRegisterClass* const*
312 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
313 bool callsEHReturn = false;
316 const MachineFrameInfo *MFI = MF->getFrameInfo();
317 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
318 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
321 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
322 &X86::GR32RegClass, &X86::GR32RegClass,
323 &X86::GR32RegClass, &X86::GR32RegClass, 0
325 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
326 &X86::GR32RegClass, &X86::GR32RegClass,
327 &X86::GR32RegClass, &X86::GR32RegClass,
328 &X86::GR32RegClass, &X86::GR32RegClass, 0
330 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
331 &X86::GR64RegClass, &X86::GR64RegClass,
332 &X86::GR64RegClass, &X86::GR64RegClass,
333 &X86::GR64RegClass, &X86::GR64RegClass, 0
335 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
336 &X86::GR64RegClass, &X86::GR64RegClass,
337 &X86::GR64RegClass, &X86::GR64RegClass,
338 &X86::GR64RegClass, &X86::GR64RegClass,
339 &X86::GR64RegClass, &X86::GR64RegClass, 0
341 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
342 &X86::GR64RegClass, &X86::GR64RegClass,
343 &X86::GR64RegClass, &X86::GR64RegClass,
344 &X86::GR64RegClass, &X86::GR64RegClass,
345 &X86::GR64RegClass, &X86::GR64RegClass,
346 &X86::VR128RegClass, &X86::VR128RegClass,
347 &X86::VR128RegClass, &X86::VR128RegClass,
348 &X86::VR128RegClass, &X86::VR128RegClass,
349 &X86::VR128RegClass, &X86::VR128RegClass,
350 &X86::VR128RegClass, &X86::VR128RegClass, 0
355 return CalleeSavedRegClassesWin64;
357 return (callsEHReturn ?
358 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
360 return (callsEHReturn ?
361 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
365 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
366 BitVector Reserved(getNumRegs());
367 // Set the stack-pointer register and its aliases as reserved.
368 Reserved.set(X86::RSP);
369 Reserved.set(X86::ESP);
370 Reserved.set(X86::SP);
371 Reserved.set(X86::SPL);
372 // Set the frame-pointer register and its aliases as reserved if needed.
374 Reserved.set(X86::RBP);
375 Reserved.set(X86::EBP);
376 Reserved.set(X86::BP);
377 Reserved.set(X86::BPL);
379 // Mark the x87 stack registers as reserved, since they don't
380 // behave normally with respect to liveness. We don't fully
381 // model the effects of x87 stack pushes and pops after
383 Reserved.set(X86::ST0);
384 Reserved.set(X86::ST1);
385 Reserved.set(X86::ST2);
386 Reserved.set(X86::ST3);
387 Reserved.set(X86::ST4);
388 Reserved.set(X86::ST5);
389 Reserved.set(X86::ST6);
390 Reserved.set(X86::ST7);
394 //===----------------------------------------------------------------------===//
395 // Stack Frame Processing methods
396 //===----------------------------------------------------------------------===//
398 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
399 unsigned MaxAlign = 0;
400 for (int i = FFI->getObjectIndexBegin(),
401 e = FFI->getObjectIndexEnd(); i != e; ++i) {
402 if (FFI->isDeadObjectIndex(i))
404 unsigned Align = FFI->getObjectAlignment(i);
405 MaxAlign = std::max(MaxAlign, Align);
411 // hasFP - Return true if the specified function should have a dedicated frame
412 // pointer register. This is true if the function has variable sized allocas or
413 // if frame pointer elimination is disabled.
415 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
416 const MachineFrameInfo *MFI = MF.getFrameInfo();
417 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
419 return (NoFramePointerElim ||
420 needsStackRealignment(MF) ||
421 MFI->hasVarSizedObjects() ||
422 MFI->isFrameAddressTaken() ||
423 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
424 (MMI && MMI->callsUnwindInit()));
427 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
428 const MachineFrameInfo *MFI = MF.getFrameInfo();
430 // FIXME: Currently we don't support stack realignment for functions with
431 // variable-sized allocas
432 return (RealignStack &&
433 (MFI->getMaxAlignment() > StackAlign &&
434 !MFI->hasVarSizedObjects()));
437 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
438 return !MF.getFrameInfo()->hasVarSizedObjects();
441 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
442 int &FrameIdx) const {
443 if (Reg == FramePtr && hasFP(MF)) {
444 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
452 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
453 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
454 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
456 if (needsStackRealignment(MF)) {
458 // Skip the saved EBP
461 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
462 assert( (-(Offset + StackSize)) % Align == 0);
464 return Offset + StackSize;
467 // FIXME: Support tail calls
470 return Offset + StackSize;
472 // Skip the saved EBP
475 // Skip the RETADDR move area
476 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
477 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
478 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
484 void X86RegisterInfo::
485 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
486 MachineBasicBlock::iterator I) const {
487 if (!hasReservedCallFrame(MF)) {
488 // If the stack pointer can be changed after prologue, turn the
489 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
490 // adjcallstackdown instruction into 'add ESP, <amt>'
491 // TODO: consider using push / pop instead of sub + store / add
492 MachineInstr *Old = I;
493 uint64_t Amount = Old->getOperand(0).getImm();
495 // We need to keep the stack aligned properly. To do this, we round the
496 // amount of space needed for the outgoing arguments up to the next
497 // alignment boundary.
498 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
500 MachineInstr *New = 0;
501 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
502 New = BuildMI(MF, Old->getDebugLoc(),
503 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
504 StackPtr).addReg(StackPtr).addImm(Amount);
506 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
507 // factor out the amount the callee already popped.
508 uint64_t CalleeAmt = Old->getOperand(1).getImm();
511 unsigned Opc = (Amount < 128) ?
512 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
513 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
514 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
515 .addReg(StackPtr).addImm(Amount);
520 // The EFLAGS implicit def is dead.
521 New->getOperand(3).setIsDead();
523 // Replace the pseudo instruction with a new instruction...
527 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
528 // If we are performing frame pointer elimination and if the callee pops
529 // something off the stack pointer, add it back. We do this until we have
530 // more advanced stack pointer tracking ability.
531 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
532 unsigned Opc = (CalleeAmt < 128) ?
533 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
534 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
535 MachineInstr *Old = I;
537 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
538 StackPtr).addReg(StackPtr).addImm(CalleeAmt);
539 // The EFLAGS implicit def is dead.
540 New->getOperand(3).setIsDead();
549 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
550 int SPAdj, RegScavenger *RS) const{
551 assert(SPAdj == 0 && "Unexpected");
554 MachineInstr &MI = *II;
555 MachineFunction &MF = *MI.getParent()->getParent();
556 while (!MI.getOperand(i).isFI()) {
558 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
561 int FrameIndex = MI.getOperand(i).getIndex();
564 if (needsStackRealignment(MF))
565 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
567 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
569 // This must be part of a four operand memory reference. Replace the
570 // FrameIndex with base register with EBP. Add an offset to the offset.
571 MI.getOperand(i).ChangeToRegister(BasePtr, false);
573 // Now add the frame object offset to the offset from EBP.
574 if (MI.getOperand(i+3).isImm()) {
575 // Offset is a 32-bit integer.
576 int Offset = getFrameIndexOffset(MF, FrameIndex) +
577 (int)(MI.getOperand(i+3).getImm());
579 MI.getOperand(i+3).ChangeToImmediate(Offset);
581 // Offset is symbolic. This is extremely rare.
582 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
583 (uint64_t)MI.getOperand(i+3).getOffset();
584 MI.getOperand(i+3).setOffset(Offset);
589 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
590 RegScavenger *RS) const {
591 MachineFrameInfo *FFI = MF.getFrameInfo();
593 // Calculate and set max stack object alignment early, so we can decide
594 // whether we will need stack realignment (and thus FP).
595 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
596 calculateMaxStackAlignment(FFI));
598 FFI->setMaxAlignment(MaxAlign);
600 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
601 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
602 if (TailCallReturnAddrDelta < 0) {
603 // create RETURNADDR area
613 CreateFixedObject(-TailCallReturnAddrDelta,
614 (-1*SlotSize)+TailCallReturnAddrDelta);
617 assert((TailCallReturnAddrDelta <= 0) &&
618 "The Delta should always be zero or negative");
619 // Create a frame entry for the EBP register that must be saved.
620 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
622 TailCallReturnAddrDelta);
623 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
624 "Slot for EBP register must be last in order to be found!");
629 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
630 /// stack pointer by a constant value.
632 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
633 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
634 const TargetInstrInfo &TII) {
635 bool isSub = NumBytes < 0;
636 uint64_t Offset = isSub ? -NumBytes : NumBytes;
639 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
640 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
642 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
643 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
644 uint64_t Chunk = (1LL << 31) - 1;
645 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
646 DebugLoc::getUnknownLoc());
649 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
651 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
652 .addReg(StackPtr).addImm(ThisVal);
653 // The EFLAGS implicit def is dead.
654 MI->getOperand(3).setIsDead();
659 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
661 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
662 unsigned StackPtr, uint64_t *NumBytes = NULL) {
663 if (MBBI == MBB.begin()) return;
665 MachineBasicBlock::iterator PI = prior(MBBI);
666 unsigned Opc = PI->getOpcode();
667 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
668 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
669 PI->getOperand(0).getReg() == StackPtr) {
671 *NumBytes += PI->getOperand(2).getImm();
673 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
674 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
675 PI->getOperand(0).getReg() == StackPtr) {
677 *NumBytes -= PI->getOperand(2).getImm();
682 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
684 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
685 MachineBasicBlock::iterator &MBBI,
686 unsigned StackPtr, uint64_t *NumBytes = NULL) {
689 if (MBBI == MBB.end()) return;
691 MachineBasicBlock::iterator NI = next(MBBI);
692 if (NI == MBB.end()) return;
694 unsigned Opc = NI->getOpcode();
695 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
696 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
697 NI->getOperand(0).getReg() == StackPtr) {
699 *NumBytes -= NI->getOperand(2).getImm();
702 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
703 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
704 NI->getOperand(0).getReg() == StackPtr) {
706 *NumBytes += NI->getOperand(2).getImm();
712 /// mergeSPUpdates - Checks the instruction before/after the passed
713 /// instruction. If it is an ADD/SUB instruction it is deleted
714 /// argument and the stack adjustment is returned as a positive value for ADD
715 /// and a negative for SUB.
716 static int mergeSPUpdates(MachineBasicBlock &MBB,
717 MachineBasicBlock::iterator &MBBI,
719 bool doMergeWithPrevious) {
721 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
722 (!doMergeWithPrevious && MBBI == MBB.end()))
727 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
728 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
729 unsigned Opc = PI->getOpcode();
730 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
731 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
732 PI->getOperand(0).getReg() == StackPtr){
733 Offset += PI->getOperand(2).getImm();
735 if (!doMergeWithPrevious) MBBI = NI;
736 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
737 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
738 PI->getOperand(0).getReg() == StackPtr) {
739 Offset -= PI->getOperand(2).getImm();
741 if (!doMergeWithPrevious) MBBI = NI;
747 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
749 unsigned FramePtr) const {
750 MachineFrameInfo *MFI = MF.getFrameInfo();
751 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
754 // Add callee saved registers to move list.
755 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
756 if (CSI.empty()) return;
758 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
759 const TargetData *TD = MF.getTarget().getTargetData();
760 bool HasFP = hasFP(MF);
762 // Calculate amount of bytes used for return address storing
764 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
765 TargetFrameInfo::StackGrowsUp ?
766 TD->getPointerSize() : -TD->getPointerSize());
768 // FIXME: This is dirty hack. The code itself is pretty mess right now.
769 // It should be rewritten from scratch and generalized sometimes.
771 // Determine maximum offset (minumum due to stack growth)
772 int64_t MaxOffset = 0;
773 for (std::vector<CalleeSavedInfo>::const_iterator
774 I = CSI.begin(), E = CSI.end(); I != E; ++I)
775 MaxOffset = std::min(MaxOffset,
776 MFI->getObjectOffset(I->getFrameIdx()));
778 // Calculate offsets.
779 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
780 for (std::vector<CalleeSavedInfo>::const_iterator
781 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
782 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
783 unsigned Reg = I->getReg();
784 Offset = MaxOffset - Offset + saveAreaOffset;
786 // Don't output a new machine move if we're re-saving the frame
787 // pointer. This happens when the PrologEpilogInserter has inserted an extra
788 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
789 // generates one when frame pointers are used. If we generate a "machine
790 // move" for this extra "PUSH", the linker will lose track of the fact that
791 // the frame pointer should have the value of the first "PUSH" when it's
794 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
795 // another bug. I.e., one where we generate a prolog like this:
803 // The immediate re-push of EBP is unnecessary. At the least, it's an
804 // optimization bug. EBP can be used as a scratch register in certain
805 // cases, but probably not when we have a frame pointer.
806 if (HasFP && FramePtr == Reg)
809 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
810 MachineLocation CSSrc(Reg);
811 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
815 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
816 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
817 MachineFrameInfo *MFI = MF.getFrameInfo();
818 const Function* Fn = MF.getFunction();
819 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
820 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
821 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
822 MachineBasicBlock::iterator MBBI = MBB.begin();
823 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
824 !Fn->doesNotThrow() ||
825 UnwindTablesMandatory;
826 bool HasFP = hasFP(MF);
829 // Get the number of bytes to allocate from the FrameInfo.
830 uint64_t StackSize = MFI->getStackSize();
832 // Get desired stack alignment
833 uint64_t MaxAlign = MFI->getMaxAlignment();
835 // Add RETADDR move area to callee saved frame size.
836 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
837 if (TailCallReturnAddrDelta < 0)
838 X86FI->setCalleeSavedFrameSize(
839 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
841 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
842 // function, and use up to 128 bytes of stack space, don't have a frame
843 // pointer, calls, or dynamic alloca then we do not need to adjust the
844 // stack pointer (we fit in the Red Zone).
845 bool DisableRedZone = Fn->hasFnAttr(Attribute::NoRedZone);
846 if (Is64Bit && !DisableRedZone &&
847 !needsStackRealignment(MF) &&
848 !MFI->hasVarSizedObjects() && // No dynamic alloca.
849 !MFI->hasCalls() && // No calls.
850 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
851 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
852 if (HasFP) MinSize += SlotSize;
853 StackSize = std::max(MinSize,
854 StackSize > 128 ? StackSize - 128 : 0);
855 MFI->setStackSize(StackSize);
858 // Insert stack pointer adjustment for later moving of return addr. Only
859 // applies to tail call optimized functions where the callee argument stack
860 // size is bigger than the callers.
861 if (TailCallReturnAddrDelta < 0) {
863 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
864 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
865 // The EFLAGS implicit def is dead.
866 MI->getOperand(3).setIsDead();
869 // uint64_t StackSize = MFI->getStackSize();
870 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
871 const TargetData *TD = MF.getTarget().getTargetData();
873 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
874 TargetFrameInfo::StackGrowsUp ?
875 TD->getPointerSize() : -TD->getPointerSize());
877 uint64_t NumBytes = 0;
879 // Calculate required stack adjustment
880 uint64_t FrameSize = StackSize - SlotSize;
881 if (needsStackRealignment(MF))
882 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
884 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
886 // Get the offset of the stack slot for the EBP register, which is
887 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
888 // Update the frame offset adjustment.
889 MFI->setOffsetAdjustment(-NumBytes);
891 // Save EBP/RBP into the appropriate stack slot...
892 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
893 .addReg(FramePtr, RegState::Kill);
895 if (needsFrameMoves) {
896 // Mark effective beginning of when frame pointer becomes valid.
897 unsigned FrameLabelId = MMI->NextLabelID();
898 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
900 // Define the current CFA rule to use the provided offset.
902 MachineLocation SPDst(MachineLocation::VirtualFP);
903 MachineLocation SPSrc(MachineLocation::VirtualFP,
904 HasFP ? 2 * stackGrowth :
905 -StackSize + stackGrowth);
906 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
908 // FIXME: Verify & implement for FP
909 MachineLocation SPDst(StackPtr);
910 MachineLocation SPSrc(StackPtr, stackGrowth);
911 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
914 // Change the rule for the FramePtr to be an "offset" rule.
915 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
916 MachineLocation FPSrc(FramePtr);
917 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
920 // Update EBP with the new base value...
921 BuildMI(MBB, MBBI, DL,
922 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
925 if (needsFrameMoves) {
926 unsigned FrameLabelId = MMI->NextLabelID();
927 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
929 // Define the current CFA to use the EBP/RBP register.
930 MachineLocation FPDst(FramePtr);
931 MachineLocation FPSrc(MachineLocation::VirtualFP);
932 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
935 // Mark the FramePtr as live-in in every block except the entry.
936 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
938 I->addLiveIn(FramePtr);
941 if (needsStackRealignment(MF)) {
943 BuildMI(MBB, MBBI, DL,
944 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
945 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
947 // The EFLAGS implicit def is dead.
948 MI->getOperand(3).setIsDead();
951 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
954 // Skip the callee-saved push instructions.
955 bool RegsSaved = false;
956 while (MBBI != MBB.end() &&
957 (MBBI->getOpcode() == X86::PUSH32r ||
958 MBBI->getOpcode() == X86::PUSH64r)) {
963 if (RegsSaved && needsFrameMoves) {
964 // Mark end of callee-saved push instructions.
965 unsigned LabelId = MMI->NextLabelID();
966 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
968 // Emit DWARF info specifying the offsets of the callee-saved registers.
969 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
972 if (MBBI != MBB.end())
973 DL = MBBI->getDebugLoc();
975 // Adjust stack pointer: ESP -= numbytes.
976 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
977 // Check, whether EAX is livein for this function.
978 bool isEAXAlive = false;
979 for (MachineRegisterInfo::livein_iterator
980 II = MF.getRegInfo().livein_begin(),
981 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
982 unsigned Reg = II->first;
983 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
984 Reg == X86::AH || Reg == X86::AL);
987 // Function prologue calls _alloca to probe the stack when allocating more
988 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
989 // to ensure that the guard pages used by the OS virtual memory manager are
990 // allocated in correct sequence.
992 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
994 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
995 .addExternalSymbol("_alloca");
998 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
999 .addReg(X86::EAX, RegState::Kill);
1001 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1002 // allocated bytes for EAX.
1003 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1004 .addImm(NumBytes - 4);
1005 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1006 .addExternalSymbol("_alloca");
1009 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1011 StackPtr, false, NumBytes - 4);
1012 MBB.insert(MBBI, MI);
1014 } else if (NumBytes) {
1015 // If there is an SUB32ri of ESP immediately before this instruction, merge
1016 // the two. This can be the case when tail call elimination is enabled and
1017 // the callee has more arguments then the caller.
1018 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1020 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1021 // instruction, merge the two instructions.
1022 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1025 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1028 if (!HasFP && needsFrameMoves && NumBytes) {
1029 // Mark end of stack pointer adjustment.
1030 unsigned LabelId = MMI->NextLabelID();
1031 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1033 // Define the current CFA rule to use the provided offset.
1035 MachineLocation SPDst(MachineLocation::VirtualFP);
1036 MachineLocation SPSrc(MachineLocation::VirtualFP,
1037 -StackSize + stackGrowth);
1038 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1040 // FIXME: Verify & implement for FP
1041 MachineLocation SPDst(StackPtr);
1042 MachineLocation SPSrc(StackPtr, stackGrowth);
1043 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1048 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1049 MachineBasicBlock &MBB) const {
1050 const MachineFrameInfo *MFI = MF.getFrameInfo();
1051 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1052 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1053 unsigned RetOpcode = MBBI->getOpcode();
1054 DebugLoc DL = MBBI->getDebugLoc();
1056 switch (RetOpcode) {
1059 case X86::TCRETURNdi:
1060 case X86::TCRETURNri:
1061 case X86::TCRETURNri64:
1062 case X86::TCRETURNdi64:
1063 case X86::EH_RETURN:
1064 case X86::EH_RETURN64:
1067 case X86::TAILJMPm: break; // These are ok
1069 llvm_unreachable("Can only insert epilog into returning blocks");
1072 // Get the number of bytes to allocate from the FrameInfo
1073 uint64_t StackSize = MFI->getStackSize();
1074 uint64_t MaxAlign = MFI->getMaxAlignment();
1075 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1076 uint64_t NumBytes = 0;
1079 // Calculate required stack adjustment
1080 uint64_t FrameSize = StackSize - SlotSize;
1081 if (needsStackRealignment(MF))
1082 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1084 NumBytes = FrameSize - CSSize;
1087 BuildMI(MBB, MBBI, DL,
1088 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1090 NumBytes = StackSize - CSSize;
1093 // Skip the callee-saved pop instructions.
1094 MachineBasicBlock::iterator LastCSPop = MBBI;
1095 while (MBBI != MBB.begin()) {
1096 MachineBasicBlock::iterator PI = prior(MBBI);
1097 unsigned Opc = PI->getOpcode();
1098 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1099 !PI->getDesc().isTerminator())
1104 DL = MBBI->getDebugLoc();
1106 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1107 // instruction, merge the two instructions.
1108 if (NumBytes || MFI->hasVarSizedObjects())
1109 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1111 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1112 // slot before popping them off! Same applies for the case, when stack was
1114 if (needsStackRealignment(MF)) {
1115 // We cannot use LEA here, because stack pointer was realigned. We need to
1116 // deallocate local frame back
1118 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1119 MBBI = prior(LastCSPop);
1122 BuildMI(MBB, MBBI, DL,
1123 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1124 StackPtr).addReg(FramePtr);
1125 } else if (MFI->hasVarSizedObjects()) {
1127 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1128 MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1129 FramePtr, false, -CSSize);
1130 MBB.insert(MBBI, MI);
1132 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1133 StackPtr).addReg(FramePtr);
1136 // adjust stack pointer back: ESP += numbytes
1138 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1141 // We're returning from function via eh_return.
1142 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1143 MBBI = prior(MBB.end());
1144 MachineOperand &DestAddr = MBBI->getOperand(0);
1145 assert(DestAddr.isReg() && "Offset should be in register!");
1146 BuildMI(MBB, MBBI, DL,
1147 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1148 StackPtr).addReg(DestAddr.getReg());
1149 // Tail call return: adjust the stack pointer and jump to callee
1150 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1151 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1152 MBBI = prior(MBB.end());
1153 MachineOperand &JumpTarget = MBBI->getOperand(0);
1154 MachineOperand &StackAdjust = MBBI->getOperand(1);
1155 assert(StackAdjust.isImm() && "Expecting immediate value.");
1157 // Adjust stack pointer.
1158 int StackAdj = StackAdjust.getImm();
1159 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1161 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1162 // Incoporate the retaddr area.
1163 Offset = StackAdj-MaxTCDelta;
1164 assert(Offset >= 0 && "Offset should never be negative");
1167 // Check for possible merge with preceeding ADD instruction.
1168 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1169 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1172 // Jump to label or value in register.
1173 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1174 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1175 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1176 else if (RetOpcode== X86::TCRETURNri64)
1177 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1179 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1181 // Delete the pseudo instruction TCRETURN.
1183 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1184 (X86FI->getTCReturnAddrDelta() < 0)) {
1185 // Add the return addr area delta back since we are not tail calling.
1186 int delta = -1*X86FI->getTCReturnAddrDelta();
1187 MBBI = prior(MBB.end());
1188 // Check for possible merge with preceeding ADD instruction.
1189 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1190 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1194 unsigned X86RegisterInfo::getRARegister() const {
1196 return X86::RIP; // Should have dwarf #16
1198 return X86::EIP; // Should have dwarf #8
1201 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1202 return hasFP(MF) ? FramePtr : StackPtr;
1205 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1207 // Calculate amount of bytes used for return address storing
1208 int stackGrowth = (Is64Bit ? -8 : -4);
1210 // Initial state of the frame pointer is esp+4.
1211 MachineLocation Dst(MachineLocation::VirtualFP);
1212 MachineLocation Src(StackPtr, stackGrowth);
1213 Moves.push_back(MachineMove(0, Dst, Src));
1215 // Add return address to move list
1216 MachineLocation CSDst(StackPtr, stackGrowth);
1217 MachineLocation CSSrc(getRARegister());
1218 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1221 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1222 llvm_unreachable("What is the exception register");
1226 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1227 llvm_unreachable("What is the exception handler register");
1232 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1233 switch (VT.getSimpleVT()) {
1234 default: return Reg;
1239 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1241 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1243 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1245 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1251 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1253 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1255 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1257 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1259 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1261 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1263 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1265 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1267 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1269 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1271 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1273 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1275 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1277 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1279 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1281 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1287 default: return Reg;
1288 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1290 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1292 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1294 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1296 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1298 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1300 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1302 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1304 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1306 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1308 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1310 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1312 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1314 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1316 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1318 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1323 default: return Reg;
1324 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1326 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1328 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1330 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1332 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1334 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1336 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1338 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1340 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1342 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1344 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1346 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1348 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1350 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1352 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1354 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1359 default: return Reg;
1360 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1362 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1364 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1366 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1368 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1370 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1372 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1374 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1376 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1378 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1380 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1382 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1384 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1386 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1388 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1390 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1399 #include "X86GenRegisterInfo.inc"
1402 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1404 MSAC() : MachineFunctionPass(&ID) {}
1406 virtual bool runOnMachineFunction(MachineFunction &MF) {
1407 MachineFrameInfo *FFI = MF.getFrameInfo();
1408 MachineRegisterInfo &RI = MF.getRegInfo();
1410 // Calculate max stack alignment of all already allocated stack objects.
1411 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1413 // Be over-conservative: scan over all vreg defs and find, whether vector
1414 // registers are used. If yes - there is probability, that vector register
1415 // will be spilled and thus stack needs to be aligned properly.
1416 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1417 RegNum < RI.getLastVirtReg(); ++RegNum)
1418 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1420 FFI->setMaxAlignment(MaxAlign);
1425 virtual const char *getPassName() const {
1426 return "X86 Maximal Stack Alignment Calculator";
1434 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }