1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
41 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
42 const TargetInstrInfo &tii)
43 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
45 // Cache some information.
46 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
47 Is64Bit = Subtarget->is64Bit();
48 StackAlign = TM.getFrameInfo()->getStackAlignment();
60 // getDwarfRegNum - This function maps LLVM register identifiers to the
61 // Dwarf specific numbering, used in debug info and exception tables.
63 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
64 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
65 unsigned Flavour = DWARFFlavour::X86_64;
66 if (!Subtarget->is64Bit()) {
67 if (Subtarget->isTargetDarwin()) {
69 Flavour = DWARFFlavour::X86_32_DarwinEH;
71 Flavour = DWARFFlavour::X86_32_Generic;
72 } else if (Subtarget->isTargetCygMing()) {
73 // Unsupported by now, just quick fallback
74 Flavour = DWARFFlavour::X86_32_Generic;
76 Flavour = DWARFFlavour::X86_32_Generic;
80 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
83 // getX86RegNum - This function maps LLVM register identifiers to their X86
84 // specific numbering, which is used in various places encoding instructions.
86 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const {
88 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
89 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
90 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
91 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
92 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
94 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
96 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
98 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
101 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
103 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
105 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
107 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
109 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
111 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
113 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
115 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
118 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
119 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
120 return RegNo-X86::ST0;
122 case X86::XMM0: case X86::XMM8: case X86::MM0:
124 case X86::XMM1: case X86::XMM9: case X86::MM1:
126 case X86::XMM2: case X86::XMM10: case X86::MM2:
128 case X86::XMM3: case X86::XMM11: case X86::MM3:
130 case X86::XMM4: case X86::XMM12: case X86::MM4:
132 case X86::XMM5: case X86::XMM13: case X86::MM5:
134 case X86::XMM6: case X86::XMM14: case X86::MM6:
136 case X86::XMM7: case X86::XMM15: case X86::MM7:
140 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
141 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
146 const TargetRegisterClass *
147 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
148 if (RC == &X86::CCRRegClass) {
150 return &X86::GR64RegClass;
152 return &X86::GR32RegClass;
157 void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
158 MachineBasicBlock::iterator I,
160 const MachineInstr *Orig) const {
161 // MOV32r0 etc. are implemented with xor which clobbers condition code.
162 // Re-materialize them as movri instructions to avoid side effects.
163 switch (Orig->getOpcode()) {
165 BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
168 BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
171 BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
174 BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
177 MachineInstr *MI = Orig->clone();
178 MI->getOperand(0).setReg(DestReg);
186 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
187 static const unsigned CalleeSavedRegs32Bit[] = {
188 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
191 static const unsigned CalleeSavedRegs32EHRet[] = {
192 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
195 static const unsigned CalleeSavedRegs64Bit[] = {
196 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
200 return CalleeSavedRegs64Bit;
203 MachineFrameInfo *MFI = MF->getFrameInfo();
204 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
205 if (MMI && MMI->callsEHReturn())
206 return CalleeSavedRegs32EHRet;
208 return CalleeSavedRegs32Bit;
212 const TargetRegisterClass* const*
213 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
214 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
215 &X86::GR32RegClass, &X86::GR32RegClass,
216 &X86::GR32RegClass, &X86::GR32RegClass, 0
218 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
219 &X86::GR32RegClass, &X86::GR32RegClass,
220 &X86::GR32RegClass, &X86::GR32RegClass,
221 &X86::GR32RegClass, &X86::GR32RegClass, 0
223 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
224 &X86::GR64RegClass, &X86::GR64RegClass,
225 &X86::GR64RegClass, &X86::GR64RegClass,
226 &X86::GR64RegClass, &X86::GR64RegClass, 0
230 return CalleeSavedRegClasses64Bit;
233 MachineFrameInfo *MFI = MF->getFrameInfo();
234 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
235 if (MMI && MMI->callsEHReturn())
236 return CalleeSavedRegClasses32EHRet;
238 return CalleeSavedRegClasses32Bit;
243 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
244 BitVector Reserved(getNumRegs());
245 Reserved.set(X86::RSP);
246 Reserved.set(X86::ESP);
247 Reserved.set(X86::SP);
248 Reserved.set(X86::SPL);
250 Reserved.set(X86::RBP);
251 Reserved.set(X86::EBP);
252 Reserved.set(X86::BP);
253 Reserved.set(X86::BPL);
258 //===----------------------------------------------------------------------===//
259 // Stack Frame Processing methods
260 //===----------------------------------------------------------------------===//
262 // hasFP - Return true if the specified function should have a dedicated frame
263 // pointer register. This is true if the function has variable sized allocas or
264 // if frame pointer elimination is disabled.
266 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
267 MachineFrameInfo *MFI = MF.getFrameInfo();
268 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
270 return (NoFramePointerElim ||
271 MFI->hasVarSizedObjects() ||
272 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
273 (MMI && MMI->callsUnwindInit()));
276 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
277 return !MF.getFrameInfo()->hasVarSizedObjects();
280 void X86RegisterInfo::
281 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
282 MachineBasicBlock::iterator I) const {
283 if (!hasReservedCallFrame(MF)) {
284 // If the stack pointer can be changed after prologue, turn the
285 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
286 // adjcallstackdown instruction into 'add ESP, <amt>'
287 // TODO: consider using push / pop instead of sub + store / add
288 MachineInstr *Old = I;
289 uint64_t Amount = Old->getOperand(0).getImm();
291 // We need to keep the stack aligned properly. To do this, we round the
292 // amount of space needed for the outgoing arguments up to the next
293 // alignment boundary.
294 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
296 MachineInstr *New = 0;
297 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
298 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
299 .addReg(StackPtr).addImm(Amount);
301 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
302 // factor out the amount the callee already popped.
303 uint64_t CalleeAmt = Old->getOperand(1).getImm();
306 unsigned Opc = (Amount < 128) ?
307 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
308 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
309 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
313 // Replace the pseudo instruction with a new instruction...
314 if (New) MBB.insert(I, New);
316 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
317 // If we are performing frame pointer elimination and if the callee pops
318 // something off the stack pointer, add it back. We do this until we have
319 // more advanced stack pointer tracking ability.
320 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
321 unsigned Opc = (CalleeAmt < 128) ?
322 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
323 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
325 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
333 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
334 int SPAdj, RegScavenger *RS) const{
335 assert(SPAdj == 0 && "Unexpected");
338 MachineInstr &MI = *II;
339 MachineFunction &MF = *MI.getParent()->getParent();
340 while (!MI.getOperand(i).isFrameIndex()) {
342 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
345 int FrameIndex = MI.getOperand(i).getIndex();
346 // This must be part of a four operand memory reference. Replace the
347 // FrameIndex with base register with EBP. Add an offset to the offset.
348 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
350 // Now add the frame object offset to the offset from EBP.
351 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
352 MI.getOperand(i+3).getImm()+SlotSize;
355 Offset += MF.getFrameInfo()->getStackSize();
357 Offset += SlotSize; // Skip the saved EBP
358 // Skip the RETADDR move area
359 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
360 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
361 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
364 MI.getOperand(i+3).ChangeToImmediate(Offset);
368 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
369 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
370 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
371 if (TailCallReturnAddrDelta < 0) {
372 // create RETURNADDR area
382 CreateFixedObject(-TailCallReturnAddrDelta,
383 (-1*SlotSize)+TailCallReturnAddrDelta);
386 assert((TailCallReturnAddrDelta <= 0) &&
387 "The Delta should always be zero or negative");
388 // Create a frame entry for the EBP register that must be saved.
389 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
391 TailCallReturnAddrDelta);
392 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
393 "Slot for EBP register must be last in order to be found!");
397 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
398 /// stack pointer by a constant value.
400 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
401 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
402 const TargetInstrInfo &TII) {
403 bool isSub = NumBytes < 0;
404 uint64_t Offset = isSub ? -NumBytes : NumBytes;
407 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
408 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
410 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
411 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
412 uint64_t Chunk = (1LL << 31) - 1;
415 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
416 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
421 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
423 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
424 unsigned StackPtr, uint64_t *NumBytes = NULL) {
425 if (MBBI == MBB.begin()) return;
427 MachineBasicBlock::iterator PI = prior(MBBI);
428 unsigned Opc = PI->getOpcode();
429 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
430 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
431 PI->getOperand(0).getReg() == StackPtr) {
433 *NumBytes += PI->getOperand(2).getImm();
435 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
436 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
437 PI->getOperand(0).getReg() == StackPtr) {
439 *NumBytes -= PI->getOperand(2).getImm();
444 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
446 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
447 MachineBasicBlock::iterator &MBBI,
448 unsigned StackPtr, uint64_t *NumBytes = NULL) {
451 if (MBBI == MBB.end()) return;
453 MachineBasicBlock::iterator NI = next(MBBI);
454 if (NI == MBB.end()) return;
456 unsigned Opc = NI->getOpcode();
457 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
458 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
459 NI->getOperand(0).getReg() == StackPtr) {
461 *NumBytes -= NI->getOperand(2).getImm();
464 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
465 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
466 NI->getOperand(0).getReg() == StackPtr) {
468 *NumBytes += NI->getOperand(2).getImm();
474 /// mergeSPUpdates - Checks the instruction before/after the passed
475 /// instruction. If it is an ADD/SUB instruction it is deleted
476 /// argument and the stack adjustment is returned as a positive value for ADD
477 /// and a negative for SUB.
478 static int mergeSPUpdates(MachineBasicBlock &MBB,
479 MachineBasicBlock::iterator &MBBI,
481 bool doMergeWithPrevious) {
483 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
484 (!doMergeWithPrevious && MBBI == MBB.end()))
489 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
490 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
491 unsigned Opc = PI->getOpcode();
492 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
493 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
494 PI->getOperand(0).getReg() == StackPtr){
495 Offset += PI->getOperand(2).getImm();
497 if (!doMergeWithPrevious) MBBI = NI;
498 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
499 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
500 PI->getOperand(0).getReg() == StackPtr) {
501 Offset -= PI->getOperand(2).getImm();
503 if (!doMergeWithPrevious) MBBI = NI;
509 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
510 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
511 MachineFrameInfo *MFI = MF.getFrameInfo();
512 const Function* Fn = MF.getFunction();
513 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
514 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
515 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
516 MachineBasicBlock::iterator MBBI = MBB.begin();
518 // Prepare for frame info.
519 unsigned FrameLabelId = 0;
521 // Get the number of bytes to allocate from the FrameInfo.
522 uint64_t StackSize = MFI->getStackSize();
523 // Add RETADDR move area to callee saved frame size.
524 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
525 if (TailCallReturnAddrDelta < 0)
526 X86FI->setCalleeSavedFrameSize(
527 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
528 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
530 // Insert stack pointer adjustment for later moving of return addr. Only
531 // applies to tail call optimized functions where the callee argument stack
532 // size is bigger than the callers.
533 if (TailCallReturnAddrDelta < 0) {
534 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
535 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
539 // Get the offset of the stack slot for the EBP register... which is
540 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
541 // Update the frame offset adjustment.
542 MFI->setOffsetAdjustment(SlotSize-NumBytes);
544 // Save EBP into the appropriate stack slot...
545 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
547 NumBytes -= SlotSize;
549 if (MMI && MMI->needsFrameInfo()) {
550 // Mark effective beginning of when frame pointer becomes valid.
551 FrameLabelId = MMI->NextLabelID();
552 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
555 // Update EBP with the new base value...
556 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
560 unsigned ReadyLabelId = 0;
561 if (MMI && MMI->needsFrameInfo()) {
562 // Mark effective beginning of when frame pointer is ready.
563 ReadyLabelId = MMI->NextLabelID();
564 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
567 // Skip the callee-saved push instructions.
568 while (MBBI != MBB.end() &&
569 (MBBI->getOpcode() == X86::PUSH32r ||
570 MBBI->getOpcode() == X86::PUSH64r))
573 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
574 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
575 // Check, whether EAX is livein for this function
576 bool isEAXAlive = false;
577 for (MachineRegisterInfo::livein_iterator
578 II = MF.getRegInfo().livein_begin(),
579 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
580 unsigned Reg = II->first;
581 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
582 Reg == X86::AH || Reg == X86::AL);
585 // Function prologue calls _alloca to probe the stack when allocating
586 // more than 4k bytes in one go. Touching the stack at 4K increments is
587 // necessary to ensure that the guard pages used by the OS virtual memory
588 // manager are allocated in correct sequence.
590 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
591 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
592 .addExternalSymbol("_alloca");
595 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
596 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
597 // allocated bytes for EAX.
598 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
599 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
600 .addExternalSymbol("_alloca");
602 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
603 StackPtr, NumBytes-4);
604 MBB.insert(MBBI, MI);
607 // If there is an SUB32ri of ESP immediately before this instruction,
608 // merge the two. This can be the case when tail call elimination is
609 // enabled and the callee has more arguments then the caller.
610 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
611 // If there is an ADD32ri or SUB32ri of ESP immediately after this
612 // instruction, merge the two instructions.
613 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
616 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
620 if (MMI && MMI->needsFrameInfo()) {
621 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
622 const TargetData *TD = MF.getTarget().getTargetData();
624 // Calculate amount of bytes used for return address storing
626 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
627 TargetFrameInfo::StackGrowsUp ?
628 TD->getPointerSize() : -TD->getPointerSize());
631 // Show update of SP.
634 MachineLocation SPDst(MachineLocation::VirtualFP);
635 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
636 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
638 MachineLocation SPDst(MachineLocation::VirtualFP);
639 MachineLocation SPSrc(MachineLocation::VirtualFP,
640 -StackSize+stackGrowth);
641 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
644 //FIXME: Verify & implement for FP
645 MachineLocation SPDst(StackPtr);
646 MachineLocation SPSrc(StackPtr, stackGrowth);
647 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
650 // Add callee saved registers to move list.
651 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
653 // FIXME: This is dirty hack. The code itself is pretty mess right now.
654 // It should be rewritten from scratch and generalized sometimes.
656 // Determine maximum offset (minumum due to stack growth)
657 int64_t MaxOffset = 0;
658 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
659 MaxOffset = std::min(MaxOffset,
660 MFI->getObjectOffset(CSI[I].getFrameIdx()));
663 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
664 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
665 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
666 unsigned Reg = CSI[I].getReg();
667 Offset = (MaxOffset-Offset+saveAreaOffset);
668 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
669 MachineLocation CSSrc(Reg);
670 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
675 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
676 MachineLocation FPSrc(FramePtr);
677 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
680 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
681 MachineLocation FPSrc(MachineLocation::VirtualFP);
682 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
685 // If it's main() on Cygwin\Mingw32 we should align stack as well
686 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
687 Subtarget->isTargetCygMing()) {
688 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
689 .addReg(X86::ESP).addImm(-StackAlign);
692 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
693 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
697 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
698 MachineBasicBlock &MBB) const {
699 const MachineFrameInfo *MFI = MF.getFrameInfo();
700 const Function* Fn = MF.getFunction();
701 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
702 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
703 MachineBasicBlock::iterator MBBI = prior(MBB.end());
704 unsigned RetOpcode = MBBI->getOpcode();
709 case X86::TCRETURNdi:
710 case X86::TCRETURNri:
711 case X86::TCRETURNri64:
712 case X86::TCRETURNdi64:
716 case X86::TAILJMPm: break; // These are ok
718 assert(0 && "Can only insert epilog into returning blocks");
721 // Get the number of bytes to allocate from the FrameInfo
722 uint64_t StackSize = MFI->getStackSize();
723 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
724 uint64_t NumBytes = StackSize - CSSize;
728 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
729 NumBytes -= SlotSize;
732 // Skip the callee-saved pop instructions.
733 while (MBBI != MBB.begin()) {
734 MachineBasicBlock::iterator PI = prior(MBBI);
735 unsigned Opc = PI->getOpcode();
736 if (Opc != X86::POP32r && Opc != X86::POP64r &&
737 !PI->getDesc().isTerminator())
742 // If there is an ADD32ri or SUB32ri of ESP immediately before this
743 // instruction, merge the two instructions.
744 if (NumBytes || MFI->hasVarSizedObjects())
745 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
747 // If dynamic alloca is used, then reset esp to point to the last callee-saved
748 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
749 // aligned stack in the prologue, - revert stack changes back. Note: we're
750 // assuming, that frame pointer was forced for main()
751 if (MFI->hasVarSizedObjects() ||
752 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
753 Subtarget->isTargetCygMing())) {
754 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
756 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
758 MBB.insert(MBBI, MI);
760 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
766 // adjust stack pointer back: ESP += numbytes
768 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
770 // We're returning from function via eh_return.
771 if (RetOpcode == X86::EH_RETURN) {
772 MBBI = prior(MBB.end());
773 MachineOperand &DestAddr = MBBI->getOperand(0);
774 assert(DestAddr.isRegister() && "Offset should be in register!");
775 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
776 addReg(DestAddr.getReg());
777 // Tail call return: adjust the stack pointer and jump to callee
778 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
779 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
780 MBBI = prior(MBB.end());
781 MachineOperand &JumpTarget = MBBI->getOperand(0);
782 MachineOperand &StackAdjust = MBBI->getOperand(1);
783 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
785 // Adjust stack pointer.
786 int StackAdj = StackAdjust.getImm();
787 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
789 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
790 // Incoporate the retaddr area.
791 Offset = StackAdj-MaxTCDelta;
792 assert(Offset >= 0 && "Offset should never be negative");
794 // Check for possible merge with preceeding ADD instruction.
795 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
796 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
798 // Jump to label or value in register.
799 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
800 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
801 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
802 else if (RetOpcode== X86::TCRETURNri64) {
803 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
805 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
806 // Delete the pseudo instruction TCRETURN.
808 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
809 (X86FI->getTCReturnAddrDelta() < 0)) {
810 // Add the return addr area delta back since we are not tail calling.
811 int delta = -1*X86FI->getTCReturnAddrDelta();
812 MBBI = prior(MBB.end());
813 // Check for possible merge with preceeding ADD instruction.
814 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
815 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
819 unsigned X86RegisterInfo::getRARegister() const {
821 return X86::RIP; // Should have dwarf #16
823 return X86::EIP; // Should have dwarf #8
826 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
827 return hasFP(MF) ? FramePtr : StackPtr;
831 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
832 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
834 return Offset + MF.getFrameInfo()->getStackSize();
836 Offset += SlotSize; // Skip the saved EBP
837 // Skip the RETADDR move area
838 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
839 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
840 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
844 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
846 // Calculate amount of bytes used for return address storing
847 int stackGrowth = (Is64Bit ? -8 : -4);
849 // Initial state of the frame pointer is esp+4.
850 MachineLocation Dst(MachineLocation::VirtualFP);
851 MachineLocation Src(StackPtr, stackGrowth);
852 Moves.push_back(MachineMove(0, Dst, Src));
854 // Add return address to move list
855 MachineLocation CSDst(StackPtr, stackGrowth);
856 MachineLocation CSSrc(getRARegister());
857 Moves.push_back(MachineMove(0, CSDst, CSSrc));
860 unsigned X86RegisterInfo::getEHExceptionRegister() const {
861 assert(0 && "What is the exception register");
865 unsigned X86RegisterInfo::getEHHandlerRegister() const {
866 assert(0 && "What is the exception handler register");
871 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
878 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
880 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
882 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
884 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
890 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
892 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
894 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
896 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
898 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
900 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
902 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
904 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
906 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
908 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
910 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
912 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
914 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
916 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
918 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
920 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
927 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
929 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
931 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
933 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
935 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
937 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
939 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
941 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
943 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
945 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
947 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
949 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
951 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
953 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
955 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
957 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
963 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
965 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
967 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
969 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
971 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
973 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
975 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
977 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
979 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
981 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
983 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
985 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
987 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
989 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
991 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
993 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
999 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1001 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1003 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1005 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1007 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1009 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1011 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1013 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1015 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1017 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1019 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1021 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1023 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1025 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1027 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1029 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1038 #include "X86GenRegisterInfo.inc"