1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
70 /// specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
75 if (!Subtarget->is64Bit()) {
76 if (Subtarget->isTargetDarwin()) {
78 Flavour = DWARFFlavour::X86_32_DarwinEH;
80 Flavour = DWARFFlavour::X86_32_Generic;
81 } else if (Subtarget->isTargetCygMing()) {
82 // Unsupported by now, just quick fallback
83 Flavour = DWARFFlavour::X86_32_Generic;
85 Flavour = DWARFFlavour::X86_32_Generic;
89 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
92 /// getX86RegNum - This function maps LLVM register identifiers to their X86
93 /// specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8: case X86::MM0:
132 case X86::XMM1: case X86::XMM9: case X86::MM1:
134 case X86::XMM2: case X86::XMM10: case X86::MM2:
136 case X86::XMM3: case X86::XMM11: case X86::MM3:
138 case X86::XMM4: case X86::XMM12: case X86::MM4:
140 case X86::XMM5: case X86::XMM13: case X86::MM5:
142 case X86::XMM6: case X86::XMM14: case X86::MM6:
144 case X86::XMM7: case X86::XMM15: case X86::MM7:
148 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
149 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
154 const TargetRegisterClass *
155 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
156 const TargetRegisterClass *B,
157 unsigned SubIdx) const {
162 if (B == &X86::GR8RegClass) {
163 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
165 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
166 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
167 A == &X86::GR64_NOREXRegClass ||
168 A == &X86::GR64_NOSPRegClass ||
169 A == &X86::GR64_NOREX_NOSPRegClass)
170 return &X86::GR64_ABCDRegClass;
171 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
172 A == &X86::GR32_NOREXRegClass ||
173 A == &X86::GR32_NOSPRegClass)
174 return &X86::GR32_ABCDRegClass;
175 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
176 A == &X86::GR16_NOREXRegClass)
177 return &X86::GR16_ABCDRegClass;
178 } else if (B == &X86::GR8_NOREXRegClass) {
179 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
180 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
181 return &X86::GR64_NOREXRegClass;
182 else if (A == &X86::GR64_ABCDRegClass)
183 return &X86::GR64_ABCDRegClass;
184 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
185 A == &X86::GR32_NOSPRegClass)
186 return &X86::GR32_NOREXRegClass;
187 else if (A == &X86::GR32_ABCDRegClass)
188 return &X86::GR32_ABCDRegClass;
189 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
190 return &X86::GR16_NOREXRegClass;
191 else if (A == &X86::GR16_ABCDRegClass)
192 return &X86::GR16_ABCDRegClass;
193 } else if (B == &X86::FR32RegClass) {
199 if (B == &X86::GR8_ABCD_HRegClass) {
200 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
201 A == &X86::GR64_NOREXRegClass ||
202 A == &X86::GR64_NOSPRegClass ||
203 A == &X86::GR64_NOREX_NOSPRegClass)
204 return &X86::GR64_ABCDRegClass;
205 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
206 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
207 return &X86::GR32_ABCDRegClass;
208 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
209 A == &X86::GR16_NOREXRegClass)
210 return &X86::GR16_ABCDRegClass;
211 } else if (B == &X86::FR64RegClass) {
217 if (B == &X86::GR16RegClass) {
218 if (A->getSize() == 4 || A->getSize() == 8)
220 } else if (B == &X86::GR16_ABCDRegClass) {
221 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
222 A == &X86::GR64_NOREXRegClass ||
223 A == &X86::GR64_NOSPRegClass ||
224 A == &X86::GR64_NOREX_NOSPRegClass)
225 return &X86::GR64_ABCDRegClass;
226 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
227 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
228 return &X86::GR32_ABCDRegClass;
229 } else if (B == &X86::GR16_NOREXRegClass) {
230 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
231 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
232 return &X86::GR64_NOREXRegClass;
233 else if (A == &X86::GR64_ABCDRegClass)
234 return &X86::GR64_ABCDRegClass;
235 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
236 A == &X86::GR32_NOSPRegClass)
237 return &X86::GR32_NOREXRegClass;
238 else if (A == &X86::GR32_ABCDRegClass)
239 return &X86::GR64_ABCDRegClass;
240 } else if (B == &X86::VR128RegClass) {
246 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
247 if (A->getSize() == 8)
249 } else if (B == &X86::GR32_ABCDRegClass) {
250 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
251 A == &X86::GR64_NOREXRegClass ||
252 A == &X86::GR64_NOSPRegClass ||
253 A == &X86::GR64_NOREX_NOSPRegClass)
254 return &X86::GR64_ABCDRegClass;
255 } else if (B == &X86::GR32_NOREXRegClass) {
256 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
257 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
258 return &X86::GR64_NOREXRegClass;
259 else if (A == &X86::GR64_ABCDRegClass)
260 return &X86::GR64_ABCDRegClass;
267 const TargetRegisterClass *
268 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
270 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
271 case 0: // Normal GPRs.
272 if (TM.getSubtarget<X86Subtarget>().is64Bit())
273 return &X86::GR64RegClass;
274 return &X86::GR32RegClass;
275 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
276 if (TM.getSubtarget<X86Subtarget>().is64Bit())
277 return &X86::GR64_NOSPRegClass;
278 return &X86::GR32_NOSPRegClass;
282 const TargetRegisterClass *
283 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
284 if (RC == &X86::CCRRegClass) {
286 return &X86::GR64RegClass;
288 return &X86::GR32RegClass;
294 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
295 bool callsEHReturn = false;
296 bool ghcCall = false;
299 callsEHReturn = MF->getMMI().callsEHReturn();
300 const Function *F = MF->getFunction();
301 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
304 static const unsigned GhcCalleeSavedRegs[] = {
308 static const unsigned CalleeSavedRegs32Bit[] = {
309 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
312 static const unsigned CalleeSavedRegs32EHRet[] = {
313 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
316 static const unsigned CalleeSavedRegs64Bit[] = {
317 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
320 static const unsigned CalleeSavedRegs64EHRet[] = {
321 X86::RAX, X86::RDX, X86::RBX, X86::R12,
322 X86::R13, X86::R14, X86::R15, X86::RBP, 0
325 static const unsigned CalleeSavedRegsWin64[] = {
326 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
327 X86::R12, X86::R13, X86::R14, X86::R15,
328 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
329 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
330 X86::XMM14, X86::XMM15, 0
334 return GhcCalleeSavedRegs;
335 } else if (Is64Bit) {
337 return CalleeSavedRegsWin64;
339 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
341 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
345 const TargetRegisterClass* const*
346 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
347 bool callsEHReturn = false;
349 callsEHReturn = MF->getMMI().callsEHReturn();
351 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
352 &X86::GR32RegClass, &X86::GR32RegClass,
353 &X86::GR32RegClass, &X86::GR32RegClass, 0
355 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
356 &X86::GR32RegClass, &X86::GR32RegClass,
357 &X86::GR32RegClass, &X86::GR32RegClass,
358 &X86::GR32RegClass, &X86::GR32RegClass, 0
360 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
361 &X86::GR64RegClass, &X86::GR64RegClass,
362 &X86::GR64RegClass, &X86::GR64RegClass,
363 &X86::GR64RegClass, &X86::GR64RegClass, 0
365 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
366 &X86::GR64RegClass, &X86::GR64RegClass,
367 &X86::GR64RegClass, &X86::GR64RegClass,
368 &X86::GR64RegClass, &X86::GR64RegClass,
369 &X86::GR64RegClass, &X86::GR64RegClass, 0
371 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
372 &X86::GR64RegClass, &X86::GR64RegClass,
373 &X86::GR64RegClass, &X86::GR64RegClass,
374 &X86::GR64RegClass, &X86::GR64RegClass,
375 &X86::GR64RegClass, &X86::GR64RegClass,
376 &X86::VR128RegClass, &X86::VR128RegClass,
377 &X86::VR128RegClass, &X86::VR128RegClass,
378 &X86::VR128RegClass, &X86::VR128RegClass,
379 &X86::VR128RegClass, &X86::VR128RegClass,
380 &X86::VR128RegClass, &X86::VR128RegClass, 0
385 return CalleeSavedRegClassesWin64;
387 return (callsEHReturn ?
388 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
390 return (callsEHReturn ?
391 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
395 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
396 BitVector Reserved(getNumRegs());
397 // Set the stack-pointer register and its aliases as reserved.
398 Reserved.set(X86::RSP);
399 Reserved.set(X86::ESP);
400 Reserved.set(X86::SP);
401 Reserved.set(X86::SPL);
403 // Set the instruction pointer register and its aliases as reserved.
404 Reserved.set(X86::RIP);
405 Reserved.set(X86::EIP);
406 Reserved.set(X86::IP);
408 // Set the frame-pointer register and its aliases as reserved if needed.
410 Reserved.set(X86::RBP);
411 Reserved.set(X86::EBP);
412 Reserved.set(X86::BP);
413 Reserved.set(X86::BPL);
416 // Mark the x87 stack registers as reserved, since they don't behave normally
417 // with respect to liveness. We don't fully model the effects of x87 stack
418 // pushes and pops after stackification.
419 Reserved.set(X86::ST0);
420 Reserved.set(X86::ST1);
421 Reserved.set(X86::ST2);
422 Reserved.set(X86::ST3);
423 Reserved.set(X86::ST4);
424 Reserved.set(X86::ST5);
425 Reserved.set(X86::ST6);
426 Reserved.set(X86::ST7);
430 //===----------------------------------------------------------------------===//
431 // Stack Frame Processing methods
432 //===----------------------------------------------------------------------===//
434 /// hasFP - Return true if the specified function should have a dedicated frame
435 /// pointer register. This is true if the function has variable sized allocas
436 /// or if frame pointer elimination is disabled.
437 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
438 const MachineFrameInfo *MFI = MF.getFrameInfo();
439 const MachineModuleInfo &MMI = MF.getMMI();
441 return (DisableFramePointerElim(MF) ||
442 needsStackRealignment(MF) ||
443 MFI->hasVarSizedObjects() ||
444 MFI->isFrameAddressTaken() ||
445 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
446 MMI.callsUnwindInit());
449 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
450 const MachineFrameInfo *MFI = MF.getFrameInfo();
451 return (RealignStack &&
452 !MFI->hasVarSizedObjects());
455 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
456 const MachineFrameInfo *MFI = MF.getFrameInfo();
457 const Function *F = MF.getFunction();
458 bool requiresRealignment =
459 RealignStack && ((MFI->getMaxAlignment() > StackAlign) ||
460 F->hasFnAttr(Attribute::StackAlignment));
462 // FIXME: Currently we don't support stack realignment for functions with
463 // variable-sized allocas.
464 // FIXME: Temporary disable the error - it seems to be too conservative.
465 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
467 "Stack realignment in presense of dynamic allocas is not supported");
469 return (requiresRealignment && !MFI->hasVarSizedObjects());
472 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
473 return !MF.getFrameInfo()->hasVarSizedObjects();
476 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
477 int &FrameIdx) const {
478 if (Reg == FramePtr && hasFP(MF)) {
479 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
486 X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
487 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
488 const MachineFrameInfo *MFI = MF.getFrameInfo();
489 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
490 uint64_t StackSize = MFI->getStackSize();
492 if (needsStackRealignment(MF)) {
494 // Skip the saved EBP.
497 unsigned Align = MFI->getObjectAlignment(FI);
498 assert((-(Offset + StackSize)) % Align == 0);
500 return Offset + StackSize;
502 // FIXME: Support tail calls
505 return Offset + StackSize;
507 // Skip the saved EBP.
510 // Skip the RETADDR move area
511 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
512 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
513 if (TailCallReturnAddrDelta < 0)
514 Offset -= TailCallReturnAddrDelta;
520 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
523 return X86::SUB64ri8;
524 return X86::SUB64ri32;
527 return X86::SUB32ri8;
532 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
535 return X86::ADD64ri8;
536 return X86::ADD64ri32;
539 return X86::ADD32ri8;
544 void X86RegisterInfo::
545 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
546 MachineBasicBlock::iterator I) const {
547 if (!hasReservedCallFrame(MF)) {
548 // If the stack pointer can be changed after prologue, turn the
549 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
550 // adjcallstackdown instruction into 'add ESP, <amt>'
551 // TODO: consider using push / pop instead of sub + store / add
552 MachineInstr *Old = I;
553 uint64_t Amount = Old->getOperand(0).getImm();
555 // We need to keep the stack aligned properly. To do this, we round the
556 // amount of space needed for the outgoing arguments up to the next
557 // alignment boundary.
558 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
560 MachineInstr *New = 0;
561 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
562 New = BuildMI(MF, Old->getDebugLoc(),
563 TII.get(getSUBriOpcode(Is64Bit, Amount)),
568 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
570 // Factor out the amount the callee already popped.
571 uint64_t CalleeAmt = Old->getOperand(1).getImm();
575 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
576 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
583 // The EFLAGS implicit def is dead.
584 New->getOperand(3).setIsDead();
586 // Replace the pseudo instruction with a new instruction.
590 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
591 // If we are performing frame pointer elimination and if the callee pops
592 // something off the stack pointer, add it back. We do this until we have
593 // more advanced stack pointer tracking ability.
594 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
595 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
596 MachineInstr *Old = I;
598 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
603 // The EFLAGS implicit def is dead.
604 New->getOperand(3).setIsDead();
613 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
614 int SPAdj, FrameIndexValue *Value,
615 RegScavenger *RS) const{
616 assert(SPAdj == 0 && "Unexpected");
619 MachineInstr &MI = *II;
620 MachineFunction &MF = *MI.getParent()->getParent();
622 while (!MI.getOperand(i).isFI()) {
624 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
627 int FrameIndex = MI.getOperand(i).getIndex();
630 unsigned Opc = MI.getOpcode();
631 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
632 if (needsStackRealignment(MF))
633 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
637 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
639 // This must be part of a four operand memory reference. Replace the
640 // FrameIndex with base register with EBP. Add an offset to the offset.
641 MI.getOperand(i).ChangeToRegister(BasePtr, false);
643 // Now add the frame object offset to the offset from EBP.
646 // Tail call jmp happens after FP is popped.
647 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
648 const MachineFrameInfo *MFI = MF.getFrameInfo();
649 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI.getOffsetOfLocalArea();
651 FIOffset = getFrameIndexOffset(MF, FrameIndex);
653 if (MI.getOperand(i+3).isImm()) {
654 // Offset is a 32-bit integer.
655 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
656 MI.getOperand(i + 3).ChangeToImmediate(Offset);
658 // Offset is symbolic. This is extremely rare.
659 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
660 MI.getOperand(i+3).setOffset(Offset);
666 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
667 RegScavenger *RS) const {
668 MachineFrameInfo *MFI = MF.getFrameInfo();
670 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
671 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
673 if (TailCallReturnAddrDelta < 0) {
674 // create RETURNADDR area
683 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
684 (-1U*SlotSize)+TailCallReturnAddrDelta,
689 assert((TailCallReturnAddrDelta <= 0) &&
690 "The Delta should always be zero or negative");
691 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
693 // Create a frame entry for the EBP register that must be saved.
694 int FrameIdx = MFI->CreateFixedObject(SlotSize,
696 TFI.getOffsetOfLocalArea() +
697 TailCallReturnAddrDelta,
699 assert(FrameIdx == MFI->getObjectIndexBegin() &&
700 "Slot for EBP register must be last in order to be found!");
705 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
706 /// stack pointer by a constant value.
708 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
709 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
710 const TargetInstrInfo &TII) {
711 bool isSub = NumBytes < 0;
712 uint64_t Offset = isSub ? -NumBytes : NumBytes;
713 unsigned Opc = isSub ?
714 getSUBriOpcode(Is64Bit, Offset) :
715 getADDriOpcode(Is64Bit, Offset);
716 uint64_t Chunk = (1LL << 31) - 1;
717 DebugLoc DL = MBB.findDebugLoc(MBBI);
720 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
722 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
725 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
730 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
732 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
733 unsigned StackPtr, uint64_t *NumBytes = NULL) {
734 if (MBBI == MBB.begin()) return;
736 MachineBasicBlock::iterator PI = prior(MBBI);
737 unsigned Opc = PI->getOpcode();
738 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
739 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
740 PI->getOperand(0).getReg() == StackPtr) {
742 *NumBytes += PI->getOperand(2).getImm();
744 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
745 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
746 PI->getOperand(0).getReg() == StackPtr) {
748 *NumBytes -= PI->getOperand(2).getImm();
753 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
755 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
756 MachineBasicBlock::iterator &MBBI,
757 unsigned StackPtr, uint64_t *NumBytes = NULL) {
758 // FIXME: THIS ISN'T RUN!!!
761 if (MBBI == MBB.end()) return;
763 MachineBasicBlock::iterator NI = llvm::next(MBBI);
764 if (NI == MBB.end()) return;
766 unsigned Opc = NI->getOpcode();
767 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
768 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
769 NI->getOperand(0).getReg() == StackPtr) {
771 *NumBytes -= NI->getOperand(2).getImm();
774 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
775 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
776 NI->getOperand(0).getReg() == StackPtr) {
778 *NumBytes += NI->getOperand(2).getImm();
784 /// mergeSPUpdates - Checks the instruction before/after the passed
785 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
786 /// stack adjustment is returned as a positive value for ADD and a negative for
788 static int mergeSPUpdates(MachineBasicBlock &MBB,
789 MachineBasicBlock::iterator &MBBI,
791 bool doMergeWithPrevious) {
792 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
793 (!doMergeWithPrevious && MBBI == MBB.end()))
796 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
797 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
798 unsigned Opc = PI->getOpcode();
801 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
802 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
803 PI->getOperand(0).getReg() == StackPtr){
804 Offset += PI->getOperand(2).getImm();
806 if (!doMergeWithPrevious) MBBI = NI;
807 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
808 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
809 PI->getOperand(0).getReg() == StackPtr) {
810 Offset -= PI->getOperand(2).getImm();
812 if (!doMergeWithPrevious) MBBI = NI;
818 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
820 unsigned FramePtr) const {
821 MachineFrameInfo *MFI = MF.getFrameInfo();
822 MachineModuleInfo &MMI = MF.getMMI();
824 // Add callee saved registers to move list.
825 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
826 if (CSI.empty()) return;
828 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
829 const TargetData *TD = MF.getTarget().getTargetData();
830 bool HasFP = hasFP(MF);
832 // Calculate amount of bytes used for return address storing.
834 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
835 TargetFrameInfo::StackGrowsUp ?
836 TD->getPointerSize() : -TD->getPointerSize());
838 // FIXME: This is dirty hack. The code itself is pretty mess right now.
839 // It should be rewritten from scratch and generalized sometimes.
841 // Determine maximum offset (minumum due to stack growth).
842 int64_t MaxOffset = 0;
843 for (std::vector<CalleeSavedInfo>::const_iterator
844 I = CSI.begin(), E = CSI.end(); I != E; ++I)
845 MaxOffset = std::min(MaxOffset,
846 MFI->getObjectOffset(I->getFrameIdx()));
848 // Calculate offsets.
849 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
850 for (std::vector<CalleeSavedInfo>::const_iterator
851 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
852 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
853 unsigned Reg = I->getReg();
854 Offset = MaxOffset - Offset + saveAreaOffset;
856 // Don't output a new machine move if we're re-saving the frame
857 // pointer. This happens when the PrologEpilogInserter has inserted an extra
858 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
859 // generates one when frame pointers are used. If we generate a "machine
860 // move" for this extra "PUSH", the linker will lose track of the fact that
861 // the frame pointer should have the value of the first "PUSH" when it's
864 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
865 // another bug. I.e., one where we generate a prolog like this:
873 // The immediate re-push of EBP is unnecessary. At the least, it's an
874 // optimization bug. EBP can be used as a scratch register in certain
875 // cases, but probably not when we have a frame pointer.
876 if (HasFP && FramePtr == Reg)
879 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
880 MachineLocation CSSrc(Reg);
881 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
885 /// emitPrologue - Push callee-saved registers onto the stack, which
886 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
887 /// space for local variables. Also emit labels used by the exception handler to
888 /// generate the exception handling frames.
889 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
890 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
891 MachineBasicBlock::iterator MBBI = MBB.begin();
892 MachineFrameInfo *MFI = MF.getFrameInfo();
893 const Function *Fn = MF.getFunction();
894 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
895 MachineModuleInfo &MMI = MF.getMMI();
896 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
897 bool needsFrameMoves = MMI.hasDebugInfo() ||
898 !Fn->doesNotThrow() || UnwindTablesMandatory;
899 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
900 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
901 bool HasFP = hasFP(MF);
904 // Add RETADDR move area to callee saved frame size.
905 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
906 if (TailCallReturnAddrDelta < 0)
907 X86FI->setCalleeSavedFrameSize(
908 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
910 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
911 // function, and use up to 128 bytes of stack space, don't have a frame
912 // pointer, calls, or dynamic alloca then we do not need to adjust the
913 // stack pointer (we fit in the Red Zone).
914 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
915 !needsStackRealignment(MF) &&
916 !MFI->hasVarSizedObjects() && // No dynamic alloca.
917 !MFI->adjustsStack() && // No calls.
918 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
919 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
920 if (HasFP) MinSize += SlotSize;
921 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
922 MFI->setStackSize(StackSize);
923 } else if (Subtarget->isTargetWin64()) {
924 // We need to always allocate 32 bytes as register spill area.
925 // FIXME: We might reuse these 32 bytes for leaf functions.
927 MFI->setStackSize(StackSize);
930 // Insert stack pointer adjustment for later moving of return addr. Only
931 // applies to tail call optimized functions where the callee argument stack
932 // size is bigger than the callers.
933 if (TailCallReturnAddrDelta < 0) {
935 BuildMI(MBB, MBBI, DL,
936 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
939 .addImm(-TailCallReturnAddrDelta);
940 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
943 // Mapping for machine moves:
945 // DST: VirtualFP AND
946 // SRC: VirtualFP => DW_CFA_def_cfa_offset
947 // ELSE => DW_CFA_def_cfa
949 // SRC: VirtualFP AND
950 // DST: Register => DW_CFA_def_cfa_register
953 // OFFSET < 0 => DW_CFA_offset_extended_sf
954 // REG < 64 => DW_CFA_offset + Reg
955 // ELSE => DW_CFA_offset_extended
957 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
958 const TargetData *TD = MF.getTarget().getTargetData();
959 uint64_t NumBytes = 0;
960 int stackGrowth = -TD->getPointerSize();
963 // Calculate required stack adjustment.
964 uint64_t FrameSize = StackSize - SlotSize;
965 if (needsStackRealignment(MF))
966 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
968 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
970 // Get the offset of the stack slot for the EBP register, which is
971 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
972 // Update the frame offset adjustment.
973 MFI->setOffsetAdjustment(-NumBytes);
975 // Save EBP/RBP into the appropriate stack slot.
976 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
977 .addReg(FramePtr, RegState::Kill);
979 if (needsFrameMoves) {
980 // Mark the place where EBP/RBP was saved.
981 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
982 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
984 // Define the current CFA rule to use the provided offset.
986 MachineLocation SPDst(MachineLocation::VirtualFP);
987 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
988 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
990 // FIXME: Verify & implement for FP
991 MachineLocation SPDst(StackPtr);
992 MachineLocation SPSrc(StackPtr, stackGrowth);
993 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
996 // Change the rule for the FramePtr to be an "offset" rule.
997 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
998 MachineLocation FPSrc(FramePtr);
999 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1002 // Update EBP with the new base value...
1003 BuildMI(MBB, MBBI, DL,
1004 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1007 if (needsFrameMoves) {
1008 // Mark effective beginning of when frame pointer becomes valid.
1009 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1010 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
1012 // Define the current CFA to use the EBP/RBP register.
1013 MachineLocation FPDst(FramePtr);
1014 MachineLocation FPSrc(MachineLocation::VirtualFP);
1015 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1018 // Mark the FramePtr as live-in in every block except the entry.
1019 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
1021 I->addLiveIn(FramePtr);
1024 if (needsStackRealignment(MF)) {
1026 BuildMI(MBB, MBBI, DL,
1027 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1028 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1030 // The EFLAGS implicit def is dead.
1031 MI->getOperand(3).setIsDead();
1034 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1037 // Skip the callee-saved push instructions.
1038 bool PushedRegs = false;
1039 int StackOffset = 2 * stackGrowth;
1041 while (MBBI != MBB.end() &&
1042 (MBBI->getOpcode() == X86::PUSH32r ||
1043 MBBI->getOpcode() == X86::PUSH64r)) {
1047 if (!HasFP && needsFrameMoves) {
1048 // Mark callee-saved push instruction.
1049 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1050 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
1052 // Define the current CFA rule to use the provided offset.
1053 unsigned Ptr = StackSize ?
1054 MachineLocation::VirtualFP : StackPtr;
1055 MachineLocation SPDst(Ptr);
1056 MachineLocation SPSrc(Ptr, StackOffset);
1057 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1058 StackOffset += stackGrowth;
1062 DL = MBB.findDebugLoc(MBBI);
1064 // Adjust stack pointer: ESP -= numbytes.
1065 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1066 // Check, whether EAX is livein for this function.
1067 bool isEAXAlive = false;
1068 for (MachineRegisterInfo::livein_iterator
1069 II = MF.getRegInfo().livein_begin(),
1070 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1071 unsigned Reg = II->first;
1072 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1073 Reg == X86::AH || Reg == X86::AL);
1076 // Function prologue calls _alloca to probe the stack when allocating more
1077 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1078 // to ensure that the guard pages used by the OS virtual memory manager are
1079 // allocated in correct sequence.
1081 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1083 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1084 .addExternalSymbol("_alloca")
1085 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1088 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1089 .addReg(X86::EAX, RegState::Kill);
1091 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1092 // allocated bytes for EAX.
1093 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1094 .addImm(NumBytes - 4);
1095 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1096 .addExternalSymbol("_alloca")
1097 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1100 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1102 StackPtr, false, NumBytes - 4);
1103 MBB.insert(MBBI, MI);
1105 } else if (NumBytes) {
1106 // If there is an SUB32ri of ESP immediately before this instruction, merge
1107 // the two. This can be the case when tail call elimination is enabled and
1108 // the callee has more arguments then the caller.
1109 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1111 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1112 // instruction, merge the two instructions.
1113 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1116 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1119 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1120 // Mark end of stack pointer adjustment.
1121 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1122 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
1124 if (!HasFP && NumBytes) {
1125 // Define the current CFA rule to use the provided offset.
1127 MachineLocation SPDst(MachineLocation::VirtualFP);
1128 MachineLocation SPSrc(MachineLocation::VirtualFP,
1129 -StackSize + stackGrowth);
1130 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1132 // FIXME: Verify & implement for FP
1133 MachineLocation SPDst(StackPtr);
1134 MachineLocation SPSrc(StackPtr, stackGrowth);
1135 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1139 // Emit DWARF info specifying the offsets of the callee-saved registers.
1141 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
1145 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1146 MachineBasicBlock &MBB) const {
1147 const MachineFrameInfo *MFI = MF.getFrameInfo();
1148 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1149 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1150 unsigned RetOpcode = MBBI->getOpcode();
1151 DebugLoc DL = MBBI->getDebugLoc();
1153 switch (RetOpcode) {
1155 llvm_unreachable("Can only insert epilog into returning blocks");
1158 case X86::TCRETURNdi:
1159 case X86::TCRETURNri:
1160 case X86::TCRETURNmi:
1161 case X86::TCRETURNdi64:
1162 case X86::TCRETURNri64:
1163 case X86::TCRETURNmi64:
1164 case X86::EH_RETURN:
1165 case X86::EH_RETURN64:
1166 break; // These are ok
1169 // Get the number of bytes to allocate from the FrameInfo.
1170 uint64_t StackSize = MFI->getStackSize();
1171 uint64_t MaxAlign = MFI->getMaxAlignment();
1172 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1173 uint64_t NumBytes = 0;
1176 // Calculate required stack adjustment.
1177 uint64_t FrameSize = StackSize - SlotSize;
1178 if (needsStackRealignment(MF))
1179 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1181 NumBytes = FrameSize - CSSize;
1184 BuildMI(MBB, MBBI, DL,
1185 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1187 NumBytes = StackSize - CSSize;
1190 // Skip the callee-saved pop instructions.
1191 MachineBasicBlock::iterator LastCSPop = MBBI;
1192 while (MBBI != MBB.begin()) {
1193 MachineBasicBlock::iterator PI = prior(MBBI);
1194 unsigned Opc = PI->getOpcode();
1196 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1197 !PI->getDesc().isTerminator())
1203 DL = MBBI->getDebugLoc();
1205 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1206 // instruction, merge the two instructions.
1207 if (NumBytes || MFI->hasVarSizedObjects())
1208 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1210 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1211 // slot before popping them off! Same applies for the case, when stack was
1213 if (needsStackRealignment(MF)) {
1214 // We cannot use LEA here, because stack pointer was realigned. We need to
1215 // deallocate local frame back.
1217 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1218 MBBI = prior(LastCSPop);
1221 BuildMI(MBB, MBBI, DL,
1222 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1223 StackPtr).addReg(FramePtr);
1224 } else if (MFI->hasVarSizedObjects()) {
1226 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1228 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1229 FramePtr, false, -CSSize);
1230 MBB.insert(MBBI, MI);
1232 BuildMI(MBB, MBBI, DL,
1233 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1236 } else if (NumBytes) {
1237 // Adjust stack pointer back: ESP += numbytes.
1238 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1241 // We're returning from function via eh_return.
1242 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1243 MBBI = prior(MBB.end());
1244 MachineOperand &DestAddr = MBBI->getOperand(0);
1245 assert(DestAddr.isReg() && "Offset should be in register!");
1246 BuildMI(MBB, MBBI, DL,
1247 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1248 StackPtr).addReg(DestAddr.getReg());
1249 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1250 RetOpcode == X86::TCRETURNmi ||
1251 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1252 RetOpcode == X86::TCRETURNmi64) {
1253 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1254 // Tail call return: adjust the stack pointer and jump to callee.
1255 MBBI = prior(MBB.end());
1256 MachineOperand &JumpTarget = MBBI->getOperand(0);
1257 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1258 assert(StackAdjust.isImm() && "Expecting immediate value.");
1260 // Adjust stack pointer.
1261 int StackAdj = StackAdjust.getImm();
1262 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1264 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1266 // Incoporate the retaddr area.
1267 Offset = StackAdj-MaxTCDelta;
1268 assert(Offset >= 0 && "Offset should never be negative");
1271 // Check for possible merge with preceeding ADD instruction.
1272 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1273 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1276 // Jump to label or value in register.
1277 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1278 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1279 ? X86::TAILJMPd : X86::TAILJMPd64)).
1280 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1281 JumpTarget.getTargetFlags());
1282 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1283 MachineInstrBuilder MIB =
1284 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1285 ? X86::TAILJMPm : X86::TAILJMPm64));
1286 for (unsigned i = 0; i != 5; ++i)
1287 MIB.addOperand(MBBI->getOperand(i));
1288 } else if (RetOpcode == X86::TCRETURNri64) {
1289 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1291 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1294 MachineInstr *NewMI = prior(MBBI);
1295 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1296 NewMI->addOperand(MBBI->getOperand(i));
1298 // Delete the pseudo instruction TCRETURN.
1300 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1301 (X86FI->getTCReturnAddrDelta() < 0)) {
1302 // Add the return addr area delta back since we are not tail calling.
1303 int delta = -1*X86FI->getTCReturnAddrDelta();
1304 MBBI = prior(MBB.end());
1306 // Check for possible merge with preceeding ADD instruction.
1307 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1308 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1312 unsigned X86RegisterInfo::getRARegister() const {
1313 return Is64Bit ? X86::RIP // Should have dwarf #16.
1314 : X86::EIP; // Should have dwarf #8.
1317 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1318 return hasFP(MF) ? FramePtr : StackPtr;
1322 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1323 // Calculate amount of bytes used for return address storing
1324 int stackGrowth = (Is64Bit ? -8 : -4);
1326 // Initial state of the frame pointer is esp+stackGrowth.
1327 MachineLocation Dst(MachineLocation::VirtualFP);
1328 MachineLocation Src(StackPtr, stackGrowth);
1329 Moves.push_back(MachineMove(0, Dst, Src));
1331 // Add return address to move list
1332 MachineLocation CSDst(StackPtr, stackGrowth);
1333 MachineLocation CSSrc(getRARegister());
1334 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1337 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1338 llvm_unreachable("What is the exception register");
1342 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1343 llvm_unreachable("What is the exception handler register");
1348 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1349 switch (VT.getSimpleVT().SimpleTy) {
1350 default: return Reg;
1355 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1357 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1359 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1361 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1367 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1369 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1371 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1373 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1375 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1377 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1379 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1381 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1383 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1385 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1387 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1389 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1391 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1393 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1395 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1397 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1403 default: return Reg;
1404 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1406 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1408 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1410 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1412 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1414 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1416 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1418 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1420 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1422 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1424 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1426 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1428 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1430 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1432 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1434 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1439 default: return Reg;
1440 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1442 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1444 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1446 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1448 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1450 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1452 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1454 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1456 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1458 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1460 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1462 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1464 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1466 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1468 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1470 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1475 default: return Reg;
1476 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1478 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1480 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1482 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1484 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1486 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1488 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1490 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1492 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1494 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1496 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1498 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1500 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1502 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1504 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1506 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1515 #include "X86GenRegisterInfo.inc"
1518 struct MSAH : public MachineFunctionPass {
1520 MSAH() : MachineFunctionPass(&ID) {}
1522 virtual bool runOnMachineFunction(MachineFunction &MF) {
1523 const X86TargetMachine *TM =
1524 static_cast<const X86TargetMachine *>(&MF.getTarget());
1525 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
1526 MachineRegisterInfo &RI = MF.getRegInfo();
1527 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1528 unsigned StackAlignment = X86RI->getStackAlignment();
1530 // Be over-conservative: scan over all vreg defs and find whether vector
1531 // registers are used. If yes, there is a possibility that vector register
1532 // will be spilled and thus require dynamic stack realignment.
1533 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1534 RegNum < RI.getLastVirtReg(); ++RegNum)
1535 if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) {
1536 FuncInfo->setReserveFP(true);
1544 virtual const char *getPassName() const {
1545 return "X86 Maximal Stack Alignment Check";
1548 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1549 AU.setPreservesCFG();
1550 MachineFunctionPass::getAnalysisUsage(AU);
1558 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }