1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/MachineValueType.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
44 #define GET_REGINFO_TARGET_DESC
45 #include "X86GenRegisterInfo.inc"
48 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
49 cl::desc("Enable use of a base pointer for complex stack frames"));
51 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
52 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
53 X86_MC::getDwarfRegFlavour(TT, false),
54 X86_MC::getDwarfRegFlavour(TT, true),
55 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
56 X86_MC::InitLLVM2SEHRegisterMapping(this);
58 // Cache some information.
59 Is64Bit = TT.isArch64Bit();
60 IsWin64 = Is64Bit && TT.isOSWindows();
62 // Use a callee-saved register as the base pointer. These registers must
63 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
64 // requires GOT in the EBX register before function calls via PLT GOT pointer.
67 // This matches the simplified 32-bit pointer code in the data layout
69 // FIXME: Should use the data layout?
70 bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
71 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
72 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
73 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
83 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
84 // ExeDepsFixer and PostRAScheduler require liveness.
89 X86RegisterInfo::getSEHRegNum(unsigned i) const {
90 return getEncodingValue(i);
93 const TargetRegisterClass *
94 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
96 // The sub_8bit sub-register index is more constrained in 32-bit mode.
97 // It behaves just like the sub_8bit_hi index.
98 if (!Is64Bit && Idx == X86::sub_8bit)
99 Idx = X86::sub_8bit_hi;
101 // Forward to TableGen's default version.
102 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
105 const TargetRegisterClass *
106 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
107 const TargetRegisterClass *B,
108 unsigned SubIdx) const {
109 // The sub_8bit sub-register index is more constrained in 32-bit mode.
110 if (!Is64Bit && SubIdx == X86::sub_8bit) {
111 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
115 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
118 const TargetRegisterClass *
119 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
120 const MachineFunction &MF) const {
121 // Don't allow super-classes of GR8_NOREX. This class is only used after
122 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
123 // to the full GR8 register class in 64-bit mode, so we cannot allow the
124 // reigster class inflation.
126 // The GR8_NOREX class is always used in a way that won't be constrained to a
127 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
129 if (RC == &X86::GR8_NOREXRegClass)
132 const TargetRegisterClass *Super = RC;
133 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
135 switch (Super->getID()) {
136 case X86::GR8RegClassID:
137 case X86::GR16RegClassID:
138 case X86::GR32RegClassID:
139 case X86::GR64RegClassID:
140 case X86::FR32RegClassID:
141 case X86::FR64RegClassID:
142 case X86::RFP32RegClassID:
143 case X86::RFP64RegClassID:
144 case X86::RFP80RegClassID:
145 case X86::VR128RegClassID:
146 case X86::VR256RegClassID:
147 // Don't return a super-class that would shrink the spill size.
148 // That can happen with the vector and float classes.
149 if (Super->getSize() == RC->getSize())
157 const TargetRegisterClass *
158 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
159 unsigned Kind) const {
160 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
162 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
163 case 0: // Normal GPRs.
164 if (Subtarget.isTarget64BitLP64())
165 return &X86::GR64RegClass;
166 return &X86::GR32RegClass;
167 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
168 if (Subtarget.isTarget64BitLP64())
169 return &X86::GR64_NOSPRegClass;
170 return &X86::GR32_NOSPRegClass;
171 case 2: // Available for tailcall (not callee-saved GPRs).
172 const Function *F = MF.getFunction();
173 if (IsWin64 || (F && F->getCallingConv() == CallingConv::X86_64_Win64))
174 return &X86::GR64_TCW64RegClass;
176 return &X86::GR64_TCRegClass;
178 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
180 return &X86::GR32RegClass;
181 return &X86::GR32_TCRegClass;
185 const TargetRegisterClass *
186 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
187 if (RC == &X86::CCRRegClass) {
189 return &X86::GR64RegClass;
191 return &X86::GR32RegClass;
197 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
198 MachineFunction &MF) const {
199 const X86FrameLowering *TFI = getFrameLowering(MF);
201 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
202 switch (RC->getID()) {
205 case X86::GR32RegClassID:
207 case X86::GR64RegClassID:
209 case X86::VR128RegClassID:
210 return Is64Bit ? 10 : 4;
211 case X86::VR64RegClassID:
217 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
218 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
219 bool HasAVX = Subtarget.hasAVX();
220 bool HasAVX512 = Subtarget.hasAVX512();
221 bool CallsEHReturn = MF->getMMI().callsEHReturn();
223 assert(MF && "MachineFunction required");
224 switch (MF->getFunction()->getCallingConv()) {
225 case CallingConv::GHC:
226 case CallingConv::HiPE:
227 return CSR_NoRegs_SaveList;
228 case CallingConv::AnyReg:
230 return CSR_64_AllRegs_AVX_SaveList;
231 return CSR_64_AllRegs_SaveList;
232 case CallingConv::PreserveMost:
233 return CSR_64_RT_MostRegs_SaveList;
234 case CallingConv::PreserveAll:
236 return CSR_64_RT_AllRegs_AVX_SaveList;
237 return CSR_64_RT_AllRegs_SaveList;
238 case CallingConv::Intel_OCL_BI: {
239 if (HasAVX512 && IsWin64)
240 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
241 if (HasAVX512 && Is64Bit)
242 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
243 if (HasAVX && IsWin64)
244 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
245 if (HasAVX && Is64Bit)
246 return CSR_64_Intel_OCL_BI_AVX_SaveList;
247 if (!HasAVX && !IsWin64 && Is64Bit)
248 return CSR_64_Intel_OCL_BI_SaveList;
251 case CallingConv::Cold:
253 return CSR_64_MostRegs_SaveList;
255 case CallingConv::X86_64_Win64:
256 return CSR_Win64_SaveList;
257 case CallingConv::X86_64_SysV:
259 return CSR_64EHRet_SaveList;
260 return CSR_64_SaveList;
267 return CSR_Win64_SaveList;
269 return CSR_64EHRet_SaveList;
270 return CSR_64_SaveList;
273 return CSR_32EHRet_SaveList;
274 return CSR_32_SaveList;
278 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
279 CallingConv::ID CC) const {
280 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
281 bool HasAVX = Subtarget.hasAVX();
282 bool HasAVX512 = Subtarget.hasAVX512();
285 case CallingConv::GHC:
286 case CallingConv::HiPE:
287 return CSR_NoRegs_RegMask;
288 case CallingConv::AnyReg:
290 return CSR_64_AllRegs_AVX_RegMask;
291 return CSR_64_AllRegs_RegMask;
292 case CallingConv::PreserveMost:
293 return CSR_64_RT_MostRegs_RegMask;
294 case CallingConv::PreserveAll:
296 return CSR_64_RT_AllRegs_AVX_RegMask;
297 return CSR_64_RT_AllRegs_RegMask;
298 case CallingConv::Intel_OCL_BI: {
299 if (HasAVX512 && IsWin64)
300 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
301 if (HasAVX512 && Is64Bit)
302 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
303 if (HasAVX && IsWin64)
304 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
305 if (HasAVX && Is64Bit)
306 return CSR_64_Intel_OCL_BI_AVX_RegMask;
307 if (!HasAVX && !IsWin64 && Is64Bit)
308 return CSR_64_Intel_OCL_BI_RegMask;
311 case CallingConv::Cold:
313 return CSR_64_MostRegs_RegMask;
317 case CallingConv::X86_64_Win64:
318 return CSR_Win64_RegMask;
319 case CallingConv::X86_64_SysV:
320 return CSR_64_RegMask;
323 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
327 return CSR_Win64_RegMask;
328 return CSR_64_RegMask;
330 return CSR_32_RegMask;
334 X86RegisterInfo::getNoPreservedMask() const {
335 return CSR_NoRegs_RegMask;
338 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
339 BitVector Reserved(getNumRegs());
340 const X86FrameLowering *TFI = getFrameLowering(MF);
342 // Set the stack-pointer register and its aliases as reserved.
343 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
347 // Set the instruction pointer register and its aliases as reserved.
348 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
352 // Set the frame-pointer register and its aliases as reserved if needed.
353 if (TFI->hasFP(MF)) {
354 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
359 // Set the base-pointer register and its aliases as reserved if needed.
360 if (hasBasePointer(MF)) {
361 CallingConv::ID CC = MF.getFunction()->getCallingConv();
362 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
363 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
365 "Stack realignment in presence of dynamic allocas is not supported with"
366 "this calling convention.");
368 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64,
370 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
375 // Mark the segment registers as reserved.
376 Reserved.set(X86::CS);
377 Reserved.set(X86::SS);
378 Reserved.set(X86::DS);
379 Reserved.set(X86::ES);
380 Reserved.set(X86::FS);
381 Reserved.set(X86::GS);
383 // Mark the floating point stack registers as reserved.
384 for (unsigned n = 0; n != 8; ++n)
385 Reserved.set(X86::ST0 + n);
387 // Reserve the registers that only exist in 64-bit mode.
389 // These 8-bit registers are part of the x86-64 extension even though their
390 // super-registers are old 32-bits.
391 Reserved.set(X86::SIL);
392 Reserved.set(X86::DIL);
393 Reserved.set(X86::BPL);
394 Reserved.set(X86::SPL);
396 for (unsigned n = 0; n != 8; ++n) {
398 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
402 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
406 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
407 for (unsigned n = 16; n != 32; ++n) {
408 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
416 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
417 // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
418 // because the calling convention defines the EFLAGS register as NOT
421 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
422 // an assert to track this and clear the register afterwards to avoid
423 // unnecessary crashes during release builds.
424 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
425 "EFLAGS are not live-out from a patchpoint.");
427 // Also clean other registers that don't need preserving (IP).
428 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
429 Mask[Reg / 32] &= ~(1U << (Reg % 32));
432 //===----------------------------------------------------------------------===//
433 // Stack Frame Processing methods
434 //===----------------------------------------------------------------------===//
436 static bool CantUseSP(const MachineFrameInfo *MFI) {
437 return MFI->hasVarSizedObjects() || MFI->hasOpaqueSPAdjustment();
440 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
441 const MachineFrameInfo *MFI = MF.getFrameInfo();
443 if (!EnableBasePointer)
446 // When we need stack realignment, we can't address the stack from the frame
447 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
448 // can't address variables from the stack pointer. MS inline asm can
449 // reference locals while also adjusting the stack pointer. When we can't
450 // use both the SP and the FP, we need a separate base pointer register.
451 bool CantUseFP = needsStackRealignment(MF);
452 return CantUseFP && CantUseSP(MFI);
455 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
456 if (!TargetRegisterInfo::canRealignStack(MF))
459 const MachineFrameInfo *MFI = MF.getFrameInfo();
460 const MachineRegisterInfo *MRI = &MF.getRegInfo();
462 // Stack realignment requires a frame pointer. If we already started
463 // register allocation with frame pointer elimination, it is too late now.
464 if (!MRI->canReserveReg(FramePtr))
467 // If a base pointer is necessary. Check that it isn't too late to reserve
470 return MRI->canReserveReg(BasePtr);
474 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
475 unsigned Reg, int &FrameIdx) const {
476 // Since X86 defines assignCalleeSavedSpillSlots which always return true
477 // this function neither used nor tested.
478 llvm_unreachable("Unused function on X86. Otherwise need a test case.");
482 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
483 int SPAdj, unsigned FIOperandNum,
484 RegScavenger *RS) const {
485 MachineInstr &MI = *II;
486 MachineFunction &MF = *MI.getParent()->getParent();
487 const X86FrameLowering *TFI = getFrameLowering(MF);
488 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
491 unsigned Opc = MI.getOpcode();
492 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
493 Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
495 if (hasBasePointer(MF))
496 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
497 else if (needsStackRealignment(MF))
498 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
502 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
504 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
505 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
506 // offset is from the traditional base pointer location. On 64-bit, the
507 // offset is from the SP at the end of the prologue, not the FP location. This
508 // matches the behavior of llvm.frameaddress.
509 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
510 MachineOperand &FI = MI.getOperand(FIOperandNum);
511 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
513 unsigned IgnoredFrameReg;
516 TFI->getFrameIndexReferenceFromSP(MF, FrameIndex, IgnoredFrameReg);
518 Offset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
519 FI.ChangeToImmediate(Offset);
523 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
524 // register as source operand, semantic is the same and destination is
525 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
526 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
527 BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64, false);
529 // This must be part of a four operand memory reference. Replace the
530 // FrameIndex with base register with EBP. Add an offset to the offset.
531 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
533 // Now add the frame object offset to the offset from EBP.
535 unsigned IgnoredFrameReg;
537 // Tail call jmp happens after FP is popped.
538 const MachineFrameInfo *MFI = MF.getFrameInfo();
539 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
541 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
543 if (BasePtr == StackPtr)
546 // The frame index format for stackmaps and patchpoints is different from the
547 // X86 format. It only has a FI and an offset.
548 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
549 assert(BasePtr == FramePtr && "Expected the FP as base register");
550 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
551 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
555 if (MI.getOperand(FIOperandNum+3).isImm()) {
556 // Offset is a 32-bit integer.
557 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
558 int Offset = FIOffset + Imm;
559 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
560 "Requesting 64-bit offset in 32-bit immediate!");
561 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
563 // Offset is symbolic. This is extremely rare.
564 uint64_t Offset = FIOffset +
565 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
566 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
570 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
571 const X86FrameLowering *TFI = getFrameLowering(MF);
572 return TFI->hasFP(MF) ? FramePtr : StackPtr;
576 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
577 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
578 unsigned FrameReg = getFrameRegister(MF);
579 if (Subtarget.isTarget64BitILP32())
580 FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
585 unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
592 default: return getX86SubSuperRegister(Reg, MVT::i64);
593 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
595 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
597 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
599 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
601 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
603 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
605 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
607 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
613 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
615 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
617 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
619 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
621 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
623 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
625 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
627 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
629 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
631 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
633 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
635 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
637 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
639 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
641 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
643 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
650 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
652 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
654 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
656 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
658 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
660 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
662 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
664 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
666 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
668 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
670 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
672 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
674 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
676 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
678 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
680 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
686 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
688 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
690 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
692 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
694 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
696 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
698 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
700 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
702 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
704 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
706 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
708 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
710 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
712 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
714 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
716 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
722 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
724 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
726 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
728 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
730 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
732 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
734 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
736 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
738 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
740 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
742 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
744 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
746 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
748 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
750 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
752 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
758 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
760 unsigned Res = getX86SubSuperRegisterOrZero(Reg, VT, High);
762 llvm_unreachable("Unexpected register or VT");
766 unsigned get512BitSuperRegister(unsigned Reg) {
767 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
768 return X86::ZMM0 + (Reg - X86::XMM0);
769 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
770 return X86::ZMM0 + (Reg - X86::YMM0);
771 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
773 llvm_unreachable("Unexpected SIMD register");