1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/ADT/BitVector.h"
35 #include "llvm/ADT/STLExtras.h"
40 NoFusing("disable-spill-fusing",
41 cl::desc("Disable fusing of spill code into instructions"));
43 PrintFailedFusing("print-failed-fuse-candidates",
44 cl::desc("Print instructions that the allocator wants to"
45 " fuse, but the X86 backend currently can't"),
49 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
50 const TargetInstrInfo &tii)
51 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
67 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator MI,
69 unsigned SrcReg, int FrameIdx,
70 const TargetRegisterClass *RC) const {
72 if (RC == &X86::GR64RegClass) {
74 } else if (RC == &X86::GR32RegClass) {
76 } else if (RC == &X86::GR16RegClass) {
78 } else if (RC == &X86::GR8RegClass) {
80 } else if (RC == &X86::GR32_RegClass) {
82 } else if (RC == &X86::GR16_RegClass) {
84 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
86 } else if (RC == &X86::FR32RegClass) {
88 } else if (RC == &X86::FR64RegClass) {
90 } else if (RC == &X86::VR128RegClass) {
93 assert(0 && "Unknown regclass");
96 addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
97 .addReg(SrcReg, false, false, true);
100 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MI,
102 unsigned DestReg, int FrameIdx,
103 const TargetRegisterClass *RC) const{
105 if (RC == &X86::GR64RegClass) {
107 } else if (RC == &X86::GR32RegClass) {
109 } else if (RC == &X86::GR16RegClass) {
111 } else if (RC == &X86::GR8RegClass) {
113 } else if (RC == &X86::GR32_RegClass) {
115 } else if (RC == &X86::GR16_RegClass) {
117 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
119 } else if (RC == &X86::FR32RegClass) {
121 } else if (RC == &X86::FR64RegClass) {
123 } else if (RC == &X86::VR128RegClass) {
126 assert(0 && "Unknown regclass");
129 addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
132 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
133 MachineBasicBlock::iterator MI,
134 unsigned DestReg, unsigned SrcReg,
135 const TargetRegisterClass *RC) const {
137 if (RC == &X86::GR64RegClass) {
139 } else if (RC == &X86::GR32RegClass) {
141 } else if (RC == &X86::GR16RegClass) {
143 } else if (RC == &X86::GR8RegClass) {
145 } else if (RC == &X86::GR32_RegClass) {
147 } else if (RC == &X86::GR16_RegClass) {
149 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
151 } else if (RC == &X86::FR32RegClass) {
152 Opc = X86::FsMOVAPSrr;
153 } else if (RC == &X86::FR64RegClass) {
154 Opc = X86::FsMOVAPDrr;
155 } else if (RC == &X86::VR128RegClass) {
158 assert(0 && "Unknown regclass");
161 BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
164 static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
166 const TargetInstrInfo &TII) {
167 unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
168 // Create the base instruction with the memory operand as the first part.
169 MachineInstrBuilder MIB = addFrameReference(BuildMI(TII.get(Opcode)),
172 // Loop over the rest of the ri operands, converting them over.
173 for (unsigned i = 0; i != NumOps; ++i) {
174 MachineOperand &MO = MI->getOperand(i+2);
176 MIB = MIB.addReg(MO.getReg(), false, MO.isImplicit());
178 MIB = MIB.addImm(MO.getImm());
179 else if (MO.isGlobalAddress())
180 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
181 else if (MO.isJumpTableIndex())
182 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
183 else if (MO.isExternalSymbol())
184 MIB = MIB.addExternalSymbol(MO.getSymbolName());
186 assert(0 && "Unknown operand type!");
191 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
192 unsigned FrameIndex, MachineInstr *MI,
193 const TargetInstrInfo &TII) {
194 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
196 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
197 MachineOperand &MO = MI->getOperand(i);
199 assert(MO.isReg() && "Expected to fold into reg operand!");
200 MIB = addFrameReference(MIB, FrameIndex);
201 } else if (MO.isReg())
202 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
204 MIB = MIB.addImm(MO.getImm());
205 else if (MO.isGlobalAddress())
206 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
207 else if (MO.isJumpTableIndex())
208 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
209 else if (MO.isExternalSymbol())
210 MIB = MIB.addExternalSymbol(MO.getSymbolName());
212 assert(0 && "Unknown operand for FuseInst!");
217 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII,
218 unsigned Opcode, unsigned FrameIndex,
220 return addFrameReference(BuildMI(TII.get(Opcode)), FrameIndex).addImm(0);
224 //===----------------------------------------------------------------------===//
225 // Efficient Lookup Table Support
226 //===----------------------------------------------------------------------===//
229 /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode.
232 unsigned from; // Original opcode.
233 unsigned to; // New opcode.
235 // less operators used by STL search.
236 bool operator<(const TableEntry &TE) const { return from < TE.from; }
237 friend bool operator<(const TableEntry &TE, unsigned V) {
240 friend bool operator<(unsigned V, const TableEntry &TE) {
246 /// TableIsSorted - Return true if the table is in 'from' opcode order.
248 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
249 for (unsigned i = 1; i != NumEntries; ++i)
250 if (!(Table[i-1] < Table[i])) {
251 cerr << "Entries out of order " << Table[i-1].from
252 << " " << Table[i].from << "\n";
258 /// TableLookup - Return the table entry matching the specified opcode.
259 /// Otherwise return NULL.
260 static const TableEntry *TableLookup(const TableEntry *Table, unsigned N,
262 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
263 if (I != Table+N && I->from == Opcode)
268 #define ARRAY_SIZE(TABLE) \
269 (sizeof(TABLE)/sizeof(TABLE[0]))
272 #define ASSERT_SORTED(TABLE)
274 #define ASSERT_SORTED(TABLE) \
275 { static bool TABLE##Checked = false; \
276 if (!TABLE##Checked) { \
277 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
278 "All lookup tables must be sorted for efficient access!"); \
279 TABLE##Checked = true; \
285 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
287 int FrameIndex) const {
289 if (NoFusing) return NULL;
291 // Table (and size) to search
292 const TableEntry *OpcodeTablePtr = NULL;
293 unsigned OpcodeTableSize = 0;
294 bool isTwoAddrFold = false;
295 unsigned NumOps = TII.getNumOperands(MI->getOpcode());
296 bool isTwoAddr = NumOps > 1 &&
297 MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
299 MachineInstr *NewMI = NULL;
300 // Folding a memory location into the two-address part of a two-address
301 // instruction is different than folding it other places. It requires
302 // replacing the *two* registers with the memory location.
303 if (isTwoAddr && NumOps >= 2 && i < 2 &&
304 MI->getOperand(0).isReg() &&
305 MI->getOperand(1).isReg() &&
306 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
307 static const TableEntry OpcodeTable[] = {
308 { X86::ADC32ri, X86::ADC32mi },
309 { X86::ADC32ri8, X86::ADC32mi8 },
310 { X86::ADC32rr, X86::ADC32mr },
311 { X86::ADC64ri32, X86::ADC64mi32 },
312 { X86::ADC64ri8, X86::ADC64mi8 },
313 { X86::ADC64rr, X86::ADC64mr },
314 { X86::ADD16ri, X86::ADD16mi },
315 { X86::ADD16ri8, X86::ADD16mi8 },
316 { X86::ADD16rr, X86::ADD16mr },
317 { X86::ADD32ri, X86::ADD32mi },
318 { X86::ADD32ri8, X86::ADD32mi8 },
319 { X86::ADD32rr, X86::ADD32mr },
320 { X86::ADD64ri32, X86::ADD64mi32 },
321 { X86::ADD64ri8, X86::ADD64mi8 },
322 { X86::ADD64rr, X86::ADD64mr },
323 { X86::ADD8ri, X86::ADD8mi },
324 { X86::ADD8rr, X86::ADD8mr },
325 { X86::AND16ri, X86::AND16mi },
326 { X86::AND16ri8, X86::AND16mi8 },
327 { X86::AND16rr, X86::AND16mr },
328 { X86::AND32ri, X86::AND32mi },
329 { X86::AND32ri8, X86::AND32mi8 },
330 { X86::AND32rr, X86::AND32mr },
331 { X86::AND64ri32, X86::AND64mi32 },
332 { X86::AND64ri8, X86::AND64mi8 },
333 { X86::AND64rr, X86::AND64mr },
334 { X86::AND8ri, X86::AND8mi },
335 { X86::AND8rr, X86::AND8mr },
336 { X86::DEC16r, X86::DEC16m },
337 { X86::DEC32r, X86::DEC32m },
338 { X86::DEC64_16r, X86::DEC16m },
339 { X86::DEC64_32r, X86::DEC32m },
340 { X86::DEC64r, X86::DEC64m },
341 { X86::DEC8r, X86::DEC8m },
342 { X86::INC16r, X86::INC16m },
343 { X86::INC32r, X86::INC32m },
344 { X86::INC64_16r, X86::INC16m },
345 { X86::INC64_32r, X86::INC32m },
346 { X86::INC64r, X86::INC64m },
347 { X86::INC8r, X86::INC8m },
348 { X86::NEG16r, X86::NEG16m },
349 { X86::NEG32r, X86::NEG32m },
350 { X86::NEG64r, X86::NEG64m },
351 { X86::NEG8r, X86::NEG8m },
352 { X86::NOT16r, X86::NOT16m },
353 { X86::NOT32r, X86::NOT32m },
354 { X86::NOT64r, X86::NOT64m },
355 { X86::NOT8r, X86::NOT8m },
356 { X86::OR16ri, X86::OR16mi },
357 { X86::OR16ri8, X86::OR16mi8 },
358 { X86::OR16rr, X86::OR16mr },
359 { X86::OR32ri, X86::OR32mi },
360 { X86::OR32ri8, X86::OR32mi8 },
361 { X86::OR32rr, X86::OR32mr },
362 { X86::OR64ri32, X86::OR64mi32 },
363 { X86::OR64ri8, X86::OR64mi8 },
364 { X86::OR64rr, X86::OR64mr },
365 { X86::OR8ri, X86::OR8mi },
366 { X86::OR8rr, X86::OR8mr },
367 { X86::ROL16r1, X86::ROL16m1 },
368 { X86::ROL16rCL, X86::ROL16mCL },
369 { X86::ROL16ri, X86::ROL16mi },
370 { X86::ROL32r1, X86::ROL32m1 },
371 { X86::ROL32rCL, X86::ROL32mCL },
372 { X86::ROL32ri, X86::ROL32mi },
373 { X86::ROL64r1, X86::ROL64m1 },
374 { X86::ROL64rCL, X86::ROL64mCL },
375 { X86::ROL64ri, X86::ROL64mi },
376 { X86::ROL8r1, X86::ROL8m1 },
377 { X86::ROL8rCL, X86::ROL8mCL },
378 { X86::ROL8ri, X86::ROL8mi },
379 { X86::ROR16r1, X86::ROR16m1 },
380 { X86::ROR16rCL, X86::ROR16mCL },
381 { X86::ROR16ri, X86::ROR16mi },
382 { X86::ROR32r1, X86::ROR32m1 },
383 { X86::ROR32rCL, X86::ROR32mCL },
384 { X86::ROR32ri, X86::ROR32mi },
385 { X86::ROR64r1, X86::ROR64m1 },
386 { X86::ROR64rCL, X86::ROR64mCL },
387 { X86::ROR64ri, X86::ROR64mi },
388 { X86::ROR8r1, X86::ROR8m1 },
389 { X86::ROR8rCL, X86::ROR8mCL },
390 { X86::ROR8ri, X86::ROR8mi },
391 { X86::SAR16r1, X86::SAR16m1 },
392 { X86::SAR16rCL, X86::SAR16mCL },
393 { X86::SAR16ri, X86::SAR16mi },
394 { X86::SAR32r1, X86::SAR32m1 },
395 { X86::SAR32rCL, X86::SAR32mCL },
396 { X86::SAR32ri, X86::SAR32mi },
397 { X86::SAR64r1, X86::SAR64m1 },
398 { X86::SAR64rCL, X86::SAR64mCL },
399 { X86::SAR64ri, X86::SAR64mi },
400 { X86::SAR8r1, X86::SAR8m1 },
401 { X86::SAR8rCL, X86::SAR8mCL },
402 { X86::SAR8ri, X86::SAR8mi },
403 { X86::SBB32ri, X86::SBB32mi },
404 { X86::SBB32ri8, X86::SBB32mi8 },
405 { X86::SBB32rr, X86::SBB32mr },
406 { X86::SBB64ri32, X86::SBB64mi32 },
407 { X86::SBB64ri8, X86::SBB64mi8 },
408 { X86::SBB64rr, X86::SBB64mr },
409 { X86::SHL16r1, X86::SHL16m1 },
410 { X86::SHL16rCL, X86::SHL16mCL },
411 { X86::SHL16ri, X86::SHL16mi },
412 { X86::SHL32r1, X86::SHL32m1 },
413 { X86::SHL32rCL, X86::SHL32mCL },
414 { X86::SHL32ri, X86::SHL32mi },
415 { X86::SHL64r1, X86::SHL64m1 },
416 { X86::SHL64rCL, X86::SHL64mCL },
417 { X86::SHL64ri, X86::SHL64mi },
418 { X86::SHL8r1, X86::SHL8m1 },
419 { X86::SHL8rCL, X86::SHL8mCL },
420 { X86::SHL8ri, X86::SHL8mi },
421 { X86::SHLD16rrCL, X86::SHLD16mrCL },
422 { X86::SHLD16rri8, X86::SHLD16mri8 },
423 { X86::SHLD32rrCL, X86::SHLD32mrCL },
424 { X86::SHLD32rri8, X86::SHLD32mri8 },
425 { X86::SHLD64rrCL, X86::SHLD64mrCL },
426 { X86::SHLD64rri8, X86::SHLD64mri8 },
427 { X86::SHR16r1, X86::SHR16m1 },
428 { X86::SHR16rCL, X86::SHR16mCL },
429 { X86::SHR16ri, X86::SHR16mi },
430 { X86::SHR32r1, X86::SHR32m1 },
431 { X86::SHR32rCL, X86::SHR32mCL },
432 { X86::SHR32ri, X86::SHR32mi },
433 { X86::SHR64r1, X86::SHR64m1 },
434 { X86::SHR64rCL, X86::SHR64mCL },
435 { X86::SHR64ri, X86::SHR64mi },
436 { X86::SHR8r1, X86::SHR8m1 },
437 { X86::SHR8rCL, X86::SHR8mCL },
438 { X86::SHR8ri, X86::SHR8mi },
439 { X86::SHRD16rrCL, X86::SHRD16mrCL },
440 { X86::SHRD16rri8, X86::SHRD16mri8 },
441 { X86::SHRD32rrCL, X86::SHRD32mrCL },
442 { X86::SHRD32rri8, X86::SHRD32mri8 },
443 { X86::SHRD64rrCL, X86::SHRD64mrCL },
444 { X86::SHRD64rri8, X86::SHRD64mri8 },
445 { X86::SUB16ri, X86::SUB16mi },
446 { X86::SUB16ri8, X86::SUB16mi8 },
447 { X86::SUB16rr, X86::SUB16mr },
448 { X86::SUB32ri, X86::SUB32mi },
449 { X86::SUB32ri8, X86::SUB32mi8 },
450 { X86::SUB32rr, X86::SUB32mr },
451 { X86::SUB64ri32, X86::SUB64mi32 },
452 { X86::SUB64ri8, X86::SUB64mi8 },
453 { X86::SUB64rr, X86::SUB64mr },
454 { X86::SUB8ri, X86::SUB8mi },
455 { X86::SUB8rr, X86::SUB8mr },
456 { X86::XOR16ri, X86::XOR16mi },
457 { X86::XOR16ri8, X86::XOR16mi8 },
458 { X86::XOR16rr, X86::XOR16mr },
459 { X86::XOR32ri, X86::XOR32mi },
460 { X86::XOR32ri8, X86::XOR32mi8 },
461 { X86::XOR32rr, X86::XOR32mr },
462 { X86::XOR64ri32, X86::XOR64mi32 },
463 { X86::XOR64ri8, X86::XOR64mi8 },
464 { X86::XOR64rr, X86::XOR64mr },
465 { X86::XOR8ri, X86::XOR8mi },
466 { X86::XOR8rr, X86::XOR8mr }
468 ASSERT_SORTED(OpcodeTable);
469 OpcodeTablePtr = OpcodeTable;
470 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
471 isTwoAddrFold = true;
472 } else if (i == 0) { // If operand 0
473 if (MI->getOpcode() == X86::MOV16r0)
474 NewMI = MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI);
475 else if (MI->getOpcode() == X86::MOV32r0)
476 NewMI = MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI);
477 else if (MI->getOpcode() == X86::MOV64r0)
478 NewMI = MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI);
479 else if (MI->getOpcode() == X86::MOV8r0)
480 NewMI = MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI);
482 NewMI->copyKillDeadInfo(MI);
486 static const TableEntry OpcodeTable[] = {
487 { X86::CMP16ri, X86::CMP16mi },
488 { X86::CMP16ri8, X86::CMP16mi8 },
489 { X86::CMP32ri, X86::CMP32mi },
490 { X86::CMP32ri8, X86::CMP32mi8 },
491 { X86::CMP8ri, X86::CMP8mi },
492 { X86::DIV16r, X86::DIV16m },
493 { X86::DIV32r, X86::DIV32m },
494 { X86::DIV64r, X86::DIV64m },
495 { X86::DIV8r, X86::DIV8m },
496 { X86::FsMOVAPDrr, X86::MOVSDmr },
497 { X86::FsMOVAPSrr, X86::MOVSSmr },
498 { X86::IDIV16r, X86::IDIV16m },
499 { X86::IDIV32r, X86::IDIV32m },
500 { X86::IDIV64r, X86::IDIV64m },
501 { X86::IDIV8r, X86::IDIV8m },
502 { X86::IMUL16r, X86::IMUL16m },
503 { X86::IMUL32r, X86::IMUL32m },
504 { X86::IMUL64r, X86::IMUL64m },
505 { X86::IMUL8r, X86::IMUL8m },
506 { X86::MOV16ri, X86::MOV16mi },
507 { X86::MOV16rr, X86::MOV16mr },
508 { X86::MOV32ri, X86::MOV32mi },
509 { X86::MOV32rr, X86::MOV32mr },
510 { X86::MOV64ri32, X86::MOV64mi32 },
511 { X86::MOV64rr, X86::MOV64mr },
512 { X86::MOV8ri, X86::MOV8mi },
513 { X86::MOV8rr, X86::MOV8mr },
514 { X86::MOVAPDrr, X86::MOVAPDmr },
515 { X86::MOVAPSrr, X86::MOVAPSmr },
516 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
517 { X86::MOVPQIto64rr,X86::MOVPQIto64mr },
518 { X86::MOVPS2SSrr, X86::MOVPS2SSmr },
519 { X86::MOVSDrr, X86::MOVSDmr },
520 { X86::MOVSDto64rr, X86::MOVSDto64mr },
521 { X86::MOVSS2DIrr, X86::MOVSS2DImr },
522 { X86::MOVSSrr, X86::MOVSSmr },
523 { X86::MOVUPDrr, X86::MOVUPDmr },
524 { X86::MOVUPSrr, X86::MOVUPSmr },
525 { X86::MUL16r, X86::MUL16m },
526 { X86::MUL32r, X86::MUL32m },
527 { X86::MUL64r, X86::MUL64m },
528 { X86::MUL8r, X86::MUL8m },
529 { X86::SETAEr, X86::SETAEm },
530 { X86::SETAr, X86::SETAm },
531 { X86::SETBEr, X86::SETBEm },
532 { X86::SETBr, X86::SETBm },
533 { X86::SETEr, X86::SETEm },
534 { X86::SETGEr, X86::SETGEm },
535 { X86::SETGr, X86::SETGm },
536 { X86::SETLEr, X86::SETLEm },
537 { X86::SETLr, X86::SETLm },
538 { X86::SETNEr, X86::SETNEm },
539 { X86::SETNPr, X86::SETNPm },
540 { X86::SETNSr, X86::SETNSm },
541 { X86::SETPr, X86::SETPm },
542 { X86::SETSr, X86::SETSm },
543 { X86::TEST16ri, X86::TEST16mi },
544 { X86::TEST32ri, X86::TEST32mi },
545 { X86::TEST64ri32, X86::TEST64mi32 },
546 { X86::TEST8ri, X86::TEST8mi },
547 { X86::XCHG16rr, X86::XCHG16mr },
548 { X86::XCHG32rr, X86::XCHG32mr },
549 { X86::XCHG64rr, X86::XCHG64mr },
550 { X86::XCHG8rr, X86::XCHG8mr }
552 ASSERT_SORTED(OpcodeTable);
553 OpcodeTablePtr = OpcodeTable;
554 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
556 static const TableEntry OpcodeTable[] = {
557 { X86::CMP16rr, X86::CMP16rm },
558 { X86::CMP32rr, X86::CMP32rm },
559 { X86::CMP64ri32, X86::CMP64mi32 },
560 { X86::CMP64ri8, X86::CMP64mi8 },
561 { X86::CMP64rr, X86::CMP64rm },
562 { X86::CMP8rr, X86::CMP8rm },
563 { X86::CMPPDrri, X86::CMPPDrmi },
564 { X86::CMPPSrri, X86::CMPPSrmi },
565 { X86::CMPSDrr, X86::CMPSDrm },
566 { X86::CMPSSrr, X86::CMPSSrm },
567 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
568 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
569 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
570 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
571 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
572 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
573 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
574 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
575 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
576 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
577 { X86::FsMOVAPDrr, X86::MOVSDrm },
578 { X86::FsMOVAPSrr, X86::MOVSSrm },
579 { X86::IMUL16rri, X86::IMUL16rmi },
580 { X86::IMUL16rri8, X86::IMUL16rmi8 },
581 { X86::IMUL32rri, X86::IMUL32rmi },
582 { X86::IMUL32rri8, X86::IMUL32rmi8 },
583 { X86::IMUL64rr, X86::IMUL64rm },
584 { X86::IMUL64rri32, X86::IMUL64rmi32 },
585 { X86::IMUL64rri8, X86::IMUL64rmi8 },
586 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
587 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
588 { X86::Int_COMISDrr, X86::Int_COMISDrm },
589 { X86::Int_COMISSrr, X86::Int_COMISSrm },
590 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
591 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
592 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
593 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
594 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
595 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
596 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
597 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
598 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
599 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
600 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
601 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
602 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
603 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
604 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
605 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
606 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
607 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
608 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
609 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
610 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
611 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
612 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
613 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
614 { X86::MOV16rr, X86::MOV16rm },
615 { X86::MOV32rr, X86::MOV32rm },
616 { X86::MOV64rr, X86::MOV64rm },
617 { X86::MOV64toPQIrr, X86::MOV64toPQIrm },
618 { X86::MOV64toSDrr, X86::MOV64toSDrm },
619 { X86::MOV8rr, X86::MOV8rm },
620 { X86::MOVAPDrr, X86::MOVAPDrm },
621 { X86::MOVAPSrr, X86::MOVAPSrm },
622 { X86::MOVDDUPrr, X86::MOVDDUPrm },
623 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
624 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
625 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
626 { X86::MOVSDrr, X86::MOVSDrm },
627 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
628 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
629 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
630 { X86::MOVSSrr, X86::MOVSSrm },
631 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
632 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
633 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
634 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
635 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
636 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
637 { X86::MOVUPDrr, X86::MOVUPDrm },
638 { X86::MOVUPSrr, X86::MOVUPSrm },
639 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
640 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
641 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
642 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
643 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
644 { X86::PSHUFDri, X86::PSHUFDmi },
645 { X86::PSHUFHWri, X86::PSHUFHWmi },
646 { X86::PSHUFLWri, X86::PSHUFLWmi },
647 { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
648 { X86::TEST16rr, X86::TEST16rm },
649 { X86::TEST32rr, X86::TEST32rm },
650 { X86::TEST64rr, X86::TEST64rm },
651 { X86::TEST8rr, X86::TEST8rm },
652 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
653 { X86::UCOMISDrr, X86::UCOMISDrm },
654 { X86::UCOMISSrr, X86::UCOMISSrm },
655 { X86::XCHG16rr, X86::XCHG16rm },
656 { X86::XCHG32rr, X86::XCHG32rm },
657 { X86::XCHG64rr, X86::XCHG64rm },
658 { X86::XCHG8rr, X86::XCHG8rm }
660 ASSERT_SORTED(OpcodeTable);
661 OpcodeTablePtr = OpcodeTable;
662 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
664 static const TableEntry OpcodeTable[] = {
665 { X86::ADC32rr, X86::ADC32rm },
666 { X86::ADC64rr, X86::ADC64rm },
667 { X86::ADD16rr, X86::ADD16rm },
668 { X86::ADD32rr, X86::ADD32rm },
669 { X86::ADD64rr, X86::ADD64rm },
670 { X86::ADD8rr, X86::ADD8rm },
671 { X86::ADDPDrr, X86::ADDPDrm },
672 { X86::ADDPSrr, X86::ADDPSrm },
673 { X86::ADDSDrr, X86::ADDSDrm },
674 { X86::ADDSSrr, X86::ADDSSrm },
675 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
676 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
677 { X86::AND16rr, X86::AND16rm },
678 { X86::AND32rr, X86::AND32rm },
679 { X86::AND64rr, X86::AND64rm },
680 { X86::AND8rr, X86::AND8rm },
681 { X86::ANDNPDrr, X86::ANDNPDrm },
682 { X86::ANDNPSrr, X86::ANDNPSrm },
683 { X86::ANDPDrr, X86::ANDPDrm },
684 { X86::ANDPSrr, X86::ANDPSrm },
685 { X86::CMOVA16rr, X86::CMOVA16rm },
686 { X86::CMOVA32rr, X86::CMOVA32rm },
687 { X86::CMOVA64rr, X86::CMOVA64rm },
688 { X86::CMOVAE16rr, X86::CMOVAE16rm },
689 { X86::CMOVAE32rr, X86::CMOVAE32rm },
690 { X86::CMOVAE64rr, X86::CMOVAE64rm },
691 { X86::CMOVB16rr, X86::CMOVB16rm },
692 { X86::CMOVB32rr, X86::CMOVB32rm },
693 { X86::CMOVB64rr, X86::CMOVB64rm },
694 { X86::CMOVBE16rr, X86::CMOVBE16rm },
695 { X86::CMOVBE32rr, X86::CMOVBE32rm },
696 { X86::CMOVBE64rr, X86::CMOVBE64rm },
697 { X86::CMOVE16rr, X86::CMOVE16rm },
698 { X86::CMOVE32rr, X86::CMOVE32rm },
699 { X86::CMOVE64rr, X86::CMOVE64rm },
700 { X86::CMOVG16rr, X86::CMOVG16rm },
701 { X86::CMOVG32rr, X86::CMOVG32rm },
702 { X86::CMOVG64rr, X86::CMOVG64rm },
703 { X86::CMOVGE16rr, X86::CMOVGE16rm },
704 { X86::CMOVGE32rr, X86::CMOVGE32rm },
705 { X86::CMOVGE64rr, X86::CMOVGE64rm },
706 { X86::CMOVL16rr, X86::CMOVL16rm },
707 { X86::CMOVL32rr, X86::CMOVL32rm },
708 { X86::CMOVL64rr, X86::CMOVL64rm },
709 { X86::CMOVLE16rr, X86::CMOVLE16rm },
710 { X86::CMOVLE32rr, X86::CMOVLE32rm },
711 { X86::CMOVLE64rr, X86::CMOVLE64rm },
712 { X86::CMOVNE16rr, X86::CMOVNE16rm },
713 { X86::CMOVNE32rr, X86::CMOVNE32rm },
714 { X86::CMOVNE64rr, X86::CMOVNE64rm },
715 { X86::CMOVNP16rr, X86::CMOVNP16rm },
716 { X86::CMOVNP32rr, X86::CMOVNP32rm },
717 { X86::CMOVNP64rr, X86::CMOVNP64rm },
718 { X86::CMOVNS16rr, X86::CMOVNS16rm },
719 { X86::CMOVNS32rr, X86::CMOVNS32rm },
720 { X86::CMOVNS64rr, X86::CMOVNS64rm },
721 { X86::CMOVP16rr, X86::CMOVP16rm },
722 { X86::CMOVP32rr, X86::CMOVP32rm },
723 { X86::CMOVP64rr, X86::CMOVP64rm },
724 { X86::CMOVS16rr, X86::CMOVS16rm },
725 { X86::CMOVS32rr, X86::CMOVS32rm },
726 { X86::CMOVS64rr, X86::CMOVS64rm },
727 { X86::DIVPDrr, X86::DIVPDrm },
728 { X86::DIVPSrr, X86::DIVPSrm },
729 { X86::DIVSDrr, X86::DIVSDrm },
730 { X86::DIVSSrr, X86::DIVSSrm },
731 { X86::HADDPDrr, X86::HADDPDrm },
732 { X86::HADDPSrr, X86::HADDPSrm },
733 { X86::HSUBPDrr, X86::HSUBPDrm },
734 { X86::HSUBPSrr, X86::HSUBPSrm },
735 { X86::IMUL16rr, X86::IMUL16rm },
736 { X86::IMUL32rr, X86::IMUL32rm },
737 { X86::MAXPDrr, X86::MAXPDrm },
738 { X86::MAXPSrr, X86::MAXPSrm },
739 { X86::MINPDrr, X86::MINPDrm },
740 { X86::MINPSrr, X86::MINPSrm },
741 { X86::MULPDrr, X86::MULPDrm },
742 { X86::MULPSrr, X86::MULPSrm },
743 { X86::MULSDrr, X86::MULSDrm },
744 { X86::MULSSrr, X86::MULSSrm },
745 { X86::OR16rr, X86::OR16rm },
746 { X86::OR32rr, X86::OR32rm },
747 { X86::OR64rr, X86::OR64rm },
748 { X86::OR8rr, X86::OR8rm },
749 { X86::ORPDrr, X86::ORPDrm },
750 { X86::ORPSrr, X86::ORPSrm },
751 { X86::PACKSSDWrr, X86::PACKSSDWrm },
752 { X86::PACKSSWBrr, X86::PACKSSWBrm },
753 { X86::PACKUSWBrr, X86::PACKUSWBrm },
754 { X86::PADDBrr, X86::PADDBrm },
755 { X86::PADDDrr, X86::PADDDrm },
756 { X86::PADDSBrr, X86::PADDSBrm },
757 { X86::PADDSWrr, X86::PADDSWrm },
758 { X86::PADDWrr, X86::PADDWrm },
759 { X86::PANDNrr, X86::PANDNrm },
760 { X86::PANDrr, X86::PANDrm },
761 { X86::PAVGBrr, X86::PAVGBrm },
762 { X86::PAVGWrr, X86::PAVGWrm },
763 { X86::PCMPEQBrr, X86::PCMPEQBrm },
764 { X86::PCMPEQDrr, X86::PCMPEQDrm },
765 { X86::PCMPEQWrr, X86::PCMPEQWrm },
766 { X86::PCMPGTBrr, X86::PCMPGTBrm },
767 { X86::PCMPGTDrr, X86::PCMPGTDrm },
768 { X86::PCMPGTWrr, X86::PCMPGTWrm },
769 { X86::PINSRWrri, X86::PINSRWrmi },
770 { X86::PMADDWDrr, X86::PMADDWDrm },
771 { X86::PMAXSWrr, X86::PMAXSWrm },
772 { X86::PMAXUBrr, X86::PMAXUBrm },
773 { X86::PMINSWrr, X86::PMINSWrm },
774 { X86::PMINUBrr, X86::PMINUBrm },
775 { X86::PMULHUWrr, X86::PMULHUWrm },
776 { X86::PMULHWrr, X86::PMULHWrm },
777 { X86::PMULLWrr, X86::PMULLWrm },
778 { X86::PMULUDQrr, X86::PMULUDQrm },
779 { X86::PORrr, X86::PORrm },
780 { X86::PSADBWrr, X86::PSADBWrm },
781 { X86::PSLLDrr, X86::PSLLDrm },
782 { X86::PSLLQrr, X86::PSLLQrm },
783 { X86::PSLLWrr, X86::PSLLWrm },
784 { X86::PSRADrr, X86::PSRADrm },
785 { X86::PSRAWrr, X86::PSRAWrm },
786 { X86::PSRLDrr, X86::PSRLDrm },
787 { X86::PSRLQrr, X86::PSRLQrm },
788 { X86::PSRLWrr, X86::PSRLWrm },
789 { X86::PSUBBrr, X86::PSUBBrm },
790 { X86::PSUBDrr, X86::PSUBDrm },
791 { X86::PSUBSBrr, X86::PSUBSBrm },
792 { X86::PSUBSWrr, X86::PSUBSWrm },
793 { X86::PSUBWrr, X86::PSUBWrm },
794 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
795 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
796 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
797 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
798 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
799 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
800 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
801 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
802 { X86::PXORrr, X86::PXORrm },
803 { X86::RCPPSr, X86::RCPPSm },
804 { X86::RSQRTPSr, X86::RSQRTPSm },
805 { X86::SBB32rr, X86::SBB32rm },
806 { X86::SBB64rr, X86::SBB64rm },
807 { X86::SHUFPDrri, X86::SHUFPDrmi },
808 { X86::SHUFPSrri, X86::SHUFPSrmi },
809 { X86::SQRTPDr, X86::SQRTPDm },
810 { X86::SQRTPSr, X86::SQRTPSm },
811 { X86::SQRTSDr, X86::SQRTSDm },
812 { X86::SQRTSSr, X86::SQRTSSm },
813 { X86::SUB16rr, X86::SUB16rm },
814 { X86::SUB32rr, X86::SUB32rm },
815 { X86::SUB64rr, X86::SUB64rm },
816 { X86::SUB8rr, X86::SUB8rm },
817 { X86::SUBPDrr, X86::SUBPDrm },
818 { X86::SUBPSrr, X86::SUBPSrm },
819 { X86::SUBSDrr, X86::SUBSDrm },
820 { X86::SUBSSrr, X86::SUBSSrm },
821 // FIXME: TEST*rr -> swapped operand of TEST*mr.
822 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
823 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
824 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
825 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
826 { X86::XOR16rr, X86::XOR16rm },
827 { X86::XOR32rr, X86::XOR32rm },
828 { X86::XOR64rr, X86::XOR64rm },
829 { X86::XOR8rr, X86::XOR8rm },
830 { X86::XORPDrr, X86::XORPDrm },
831 { X86::XORPSrr, X86::XORPSrm }
833 ASSERT_SORTED(OpcodeTable);
834 OpcodeTablePtr = OpcodeTable;
835 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
838 // If table selected...
839 if (OpcodeTablePtr) {
840 // Find the Opcode to fuse
841 unsigned fromOpcode = MI->getOpcode();
842 // Lookup fromOpcode in table
843 if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
846 NewMI = FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII);
848 NewMI = FuseInst(Entry->to, i, FrameIndex, MI, TII);
849 NewMI->copyKillDeadInfo(MI);
855 if (PrintFailedFusing)
856 cerr << "We failed to fuse ("
857 << ((i == 1) ? "r" : "s") << "): " << *MI;
862 const unsigned *X86RegisterInfo::getCalleeSavedRegs() const {
863 static const unsigned CalleeSavedRegs32Bit[] = {
864 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
866 static const unsigned CalleeSavedRegs64Bit[] = {
867 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
870 return Is64Bit ? CalleeSavedRegs64Bit : CalleeSavedRegs32Bit;
873 const TargetRegisterClass* const*
874 X86RegisterInfo::getCalleeSavedRegClasses() const {
875 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
876 &X86::GR32RegClass, &X86::GR32RegClass,
877 &X86::GR32RegClass, &X86::GR32RegClass, 0
879 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
880 &X86::GR64RegClass, &X86::GR64RegClass,
881 &X86::GR64RegClass, &X86::GR64RegClass,
882 &X86::GR64RegClass, &X86::GR64RegClass, 0
885 return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
888 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
889 BitVector Reserved(getNumRegs());
890 Reserved.set(X86::RSP);
891 Reserved.set(X86::ESP);
892 Reserved.set(X86::SP);
893 Reserved.set(X86::SPL);
895 Reserved.set(X86::RBP);
896 Reserved.set(X86::EBP);
897 Reserved.set(X86::BP);
898 Reserved.set(X86::BPL);
903 //===----------------------------------------------------------------------===//
904 // Stack Frame Processing methods
905 //===----------------------------------------------------------------------===//
907 // hasFP - Return true if the specified function should have a dedicated frame
908 // pointer register. This is true if the function has variable sized allocas or
909 // if frame pointer elimination is disabled.
911 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
912 return (NoFramePointerElim ||
913 MF.getFrameInfo()->hasVarSizedObjects() ||
914 MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
917 void X86RegisterInfo::
918 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
919 MachineBasicBlock::iterator I) const {
921 // If we have a frame pointer, turn the adjcallstackup instruction into a
922 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
924 MachineInstr *Old = I;
925 unsigned Amount = Old->getOperand(0).getImmedValue();
927 // We need to keep the stack aligned properly. To do this, we round the
928 // amount of space needed for the outgoing arguments up to the next
929 // alignment boundary.
930 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
931 Amount = (Amount+Align-1)/Align*Align;
933 MachineInstr *New = 0;
934 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
935 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
936 .addReg(StackPtr).addImm(Amount);
938 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
939 // factor out the amount the callee already popped.
940 unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
943 unsigned Opc = (Amount < 128) ?
944 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
945 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
946 New = BuildMI(TII.get(Opc), StackPtr)
947 .addReg(StackPtr).addImm(Amount);
951 // Replace the pseudo instruction with a new instruction...
952 if (New) MBB.insert(I, New);
954 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
955 // If we are performing frame pointer elimination and if the callee pops
956 // something off the stack pointer, add it back. We do this until we have
957 // more advanced stack pointer tracking ability.
958 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
959 unsigned Opc = (CalleeAmt < 128) ?
960 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
961 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
963 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
971 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
973 MachineInstr &MI = *II;
974 MachineFunction &MF = *MI.getParent()->getParent();
975 while (!MI.getOperand(i).isFrameIndex()) {
977 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
980 int FrameIndex = MI.getOperand(i).getFrameIndex();
981 // This must be part of a four operand memory reference. Replace the
982 // FrameIndex with base register with EBP. Add an offset to the offset.
983 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
985 // Now add the frame object offset to the offset from EBP.
986 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
987 MI.getOperand(i+3).getImmedValue()+SlotSize;
990 Offset += MF.getFrameInfo()->getStackSize();
992 Offset += SlotSize; // Skip the saved EBP
994 MI.getOperand(i+3).ChangeToImmediate(Offset);
998 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
1000 // Create a frame entry for the EBP register that must be saved.
1001 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,SlotSize * -2);
1002 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
1003 "Slot for EBP register must be last in order to be found!");
1007 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
1008 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1009 MachineBasicBlock::iterator MBBI = MBB.begin();
1010 MachineFrameInfo *MFI = MF.getFrameInfo();
1011 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1012 const Function* Fn = MF.getFunction();
1013 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
1015 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1017 // Prepare for frame info.
1018 unsigned FrameLabelId = 0;
1020 // Get the number of bytes to allocate from the FrameInfo
1021 unsigned NumBytes = MFI->getStackSize();
1023 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
1024 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1025 // Function prologue calls _alloca to probe the stack when allocating
1026 // more than 4k bytes in one go. Touching the stack at 4K increments is
1027 // necessary to ensure that the guard pages used by the OS virtual memory
1028 // manager are allocated in correct sequence.
1029 MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
1030 MBB.insert(MBBI, MI);
1031 MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1032 MBB.insert(MBBI, MI);
1034 unsigned Opc = (NumBytes < 128) ?
1035 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1036 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1037 MI= BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
1038 MBB.insert(MBBI, MI);
1042 if (MMI && MMI->needsFrameInfo()) {
1043 // Mark effective beginning of when frame pointer becomes valid.
1044 FrameLabelId = MMI->NextLabelID();
1045 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
1049 // Get the offset of the stack slot for the EBP register... which is
1050 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1051 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+SlotSize;
1052 // Update the frame offset adjustment.
1053 MFI->setOffsetAdjustment(SlotSize-NumBytes);
1055 // Save EBP into the appropriate stack slot...
1056 // mov [ESP-<offset>], EBP
1057 MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::MOV64mr : X86::MOV32mr)),
1058 StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
1059 MBB.insert(MBBI, MI);
1061 // Update EBP with the new base value...
1062 if (NumBytes == SlotSize) // mov EBP, ESP
1063 MI = BuildMI(TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr).
1065 else // lea EBP, [ESP+StackSize]
1066 MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::LEA64r : X86::LEA32r),
1067 FramePtr), StackPtr, NumBytes-SlotSize);
1069 MBB.insert(MBBI, MI);
1072 if (MMI && MMI->needsFrameInfo()) {
1073 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1076 // Show update of SP.
1077 MachineLocation SPDst(MachineLocation::VirtualFP);
1078 MachineLocation SPSrc(MachineLocation::VirtualFP, -NumBytes);
1079 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1081 MachineLocation SP(StackPtr);
1082 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1085 // Add callee saved registers to move list.
1086 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1087 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1088 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1089 unsigned Reg = CSI[I].getReg();
1090 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1091 MachineLocation CSSrc(Reg);
1092 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1095 // Mark effective beginning of when frame pointer is ready.
1096 unsigned ReadyLabelId = MMI->NextLabelID();
1097 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
1099 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
1100 MachineLocation FPSrc(MachineLocation::VirtualFP);
1101 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1104 // If it's main() on Cygwin\Mingw32 we should align stack as well
1105 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1106 Subtarget->isTargetCygMing()) {
1107 MI= BuildMI(TII.get(X86::AND32ri), X86::ESP)
1108 .addReg(X86::ESP).addImm(-Align);
1109 MBB.insert(MBBI, MI);
1112 MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(Align);
1113 MBB.insert(MBBI, MI);
1114 MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1115 MBB.insert(MBBI, MI);
1119 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1120 MachineBasicBlock &MBB) const {
1121 const MachineFrameInfo *MFI = MF.getFrameInfo();
1122 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1124 switch (MBBI->getOpcode()) {
1129 case X86::TAILJMPm: break; // These are ok
1131 assert(0 && "Can only insert epilog into returning blocks");
1136 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1140 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1142 // Get the number of bytes allocated from the FrameInfo...
1143 unsigned NumBytes = MFI->getStackSize();
1145 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
1146 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1147 // instruction, merge the two instructions.
1148 if (MBBI != MBB.begin()) {
1149 MachineBasicBlock::iterator PI = prior(MBBI);
1150 unsigned Opc = PI->getOpcode();
1151 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1152 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1153 PI->getOperand(0).getReg() == StackPtr) {
1154 NumBytes += PI->getOperand(2).getImmedValue();
1156 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1157 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1158 PI->getOperand(0).getReg() == StackPtr) {
1159 NumBytes -= PI->getOperand(2).getImmedValue();
1165 unsigned Opc = (NumBytes < 128) ?
1166 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1167 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1168 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
1169 .addReg(StackPtr).addImm(NumBytes);
1170 } else if ((int)NumBytes < 0) {
1171 unsigned Opc = (-NumBytes < 128) ?
1172 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1173 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1174 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
1175 .addReg(StackPtr).addImm(-NumBytes);
1181 unsigned X86RegisterInfo::getRARegister() const {
1182 return X86::ST0; // use a non-register register
1185 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1186 return hasFP(MF) ? FramePtr : StackPtr;
1189 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1191 // Initial state of the frame pointer is esp.
1192 MachineLocation Dst(MachineLocation::VirtualFP);
1193 MachineLocation Src(StackPtr, 0);
1194 Moves.push_back(MachineMove(0, Dst, Src));
1197 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1198 assert(0 && "What is the exception register");
1202 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1203 assert(0 && "What is the exception handler register");
1208 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
1210 default: return Reg;
1215 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1217 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1219 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1221 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1227 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1229 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1231 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1233 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1235 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1237 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1239 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1241 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1243 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1245 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1247 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1249 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1251 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1253 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1255 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1257 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1263 default: return Reg;
1264 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1266 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1268 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1270 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1272 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1274 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1276 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1278 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1280 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1282 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1284 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1286 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1288 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1290 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1292 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1294 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1299 default: return Reg;
1300 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1302 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1304 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1306 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1308 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1310 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1312 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1314 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1316 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1318 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1320 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1322 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1324 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1326 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1328 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1330 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1335 default: return Reg;
1336 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1338 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1340 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1342 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1344 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1346 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1348 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1350 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1352 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1354 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1356 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1358 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1360 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1362 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1364 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1366 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1375 #include "X86GenRegisterInfo.inc"