1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
41 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
42 const TargetInstrInfo &tii)
43 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
45 // Cache some information.
46 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
47 Is64Bit = Subtarget->is64Bit();
48 IsWin64 = Subtarget->isTargetWin64();
49 StackAlign = TM.getFrameInfo()->getStackAlignment();
61 // getDwarfRegNum - This function maps LLVM register identifiers to the
62 // Dwarf specific numbering, used in debug info and exception tables.
64 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
65 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
66 unsigned Flavour = DWARFFlavour::X86_64;
67 if (!Subtarget->is64Bit()) {
68 if (Subtarget->isTargetDarwin()) {
70 Flavour = DWARFFlavour::X86_32_DarwinEH;
72 Flavour = DWARFFlavour::X86_32_Generic;
73 } else if (Subtarget->isTargetCygMing()) {
74 // Unsupported by now, just quick fallback
75 Flavour = DWARFFlavour::X86_32_Generic;
77 Flavour = DWARFFlavour::X86_32_Generic;
81 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
84 // getX86RegNum - This function maps LLVM register identifiers to their X86
85 // specific numbering, which is used in various places encoding instructions.
87 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const {
89 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
90 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
91 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
92 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
93 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
95 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
97 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
99 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
102 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
106 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
108 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
110 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
112 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
114 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
116 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
119 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
120 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
121 return RegNo-X86::ST0;
123 case X86::XMM0: case X86::XMM8: case X86::MM0:
125 case X86::XMM1: case X86::XMM9: case X86::MM1:
127 case X86::XMM2: case X86::XMM10: case X86::MM2:
129 case X86::XMM3: case X86::XMM11: case X86::MM3:
131 case X86::XMM4: case X86::XMM12: case X86::MM4:
133 case X86::XMM5: case X86::XMM13: case X86::MM5:
135 case X86::XMM6: case X86::XMM14: case X86::MM6:
137 case X86::XMM7: case X86::XMM15: case X86::MM7:
141 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
142 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
147 const TargetRegisterClass *
148 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
149 if (RC == &X86::CCRRegClass) {
151 return &X86::GR64RegClass;
153 return &X86::GR32RegClass;
158 void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
159 MachineBasicBlock::iterator I,
161 const MachineInstr *Orig) const {
162 // MOV32r0 etc. are implemented with xor which clobbers condition code.
163 // Re-materialize them as movri instructions to avoid side effects.
164 switch (Orig->getOpcode()) {
166 BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
169 BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
172 BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
175 BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
178 MachineInstr *MI = Orig->clone();
179 MI->getOperand(0).setReg(DestReg);
187 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
188 static const unsigned CalleeSavedRegs32Bit[] = {
189 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
192 static const unsigned CalleeSavedRegs32EHRet[] = {
193 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
196 static const unsigned CalleeSavedRegs64Bit[] = {
197 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
200 static const unsigned CalleeSavedRegsWin64[] = {
201 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
202 X86::R12, X86::R13, X86::R14, X86::R15, 0
207 return CalleeSavedRegsWin64;
209 return CalleeSavedRegs64Bit;
212 MachineFrameInfo *MFI = MF->getFrameInfo();
213 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
214 if (MMI && MMI->callsEHReturn())
215 return CalleeSavedRegs32EHRet;
217 return CalleeSavedRegs32Bit;
221 const TargetRegisterClass* const*
222 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
223 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
224 &X86::GR32RegClass, &X86::GR32RegClass,
225 &X86::GR32RegClass, &X86::GR32RegClass, 0
227 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
228 &X86::GR32RegClass, &X86::GR32RegClass,
229 &X86::GR32RegClass, &X86::GR32RegClass,
230 &X86::GR32RegClass, &X86::GR32RegClass, 0
232 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
233 &X86::GR64RegClass, &X86::GR64RegClass,
234 &X86::GR64RegClass, &X86::GR64RegClass,
235 &X86::GR64RegClass, &X86::GR64RegClass, 0
237 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
238 &X86::GR64RegClass, &X86::GR64RegClass,
239 &X86::GR64RegClass, &X86::GR64RegClass,
240 &X86::GR64RegClass, &X86::GR64RegClass,
241 &X86::GR64RegClass, &X86::GR64RegClass, 0
246 return CalleeSavedRegClassesWin64;
248 return CalleeSavedRegClasses64Bit;
251 MachineFrameInfo *MFI = MF->getFrameInfo();
252 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
253 if (MMI && MMI->callsEHReturn())
254 return CalleeSavedRegClasses32EHRet;
256 return CalleeSavedRegClasses32Bit;
261 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
262 BitVector Reserved(getNumRegs());
263 Reserved.set(X86::RSP);
264 Reserved.set(X86::ESP);
265 Reserved.set(X86::SP);
266 Reserved.set(X86::SPL);
268 Reserved.set(X86::RBP);
269 Reserved.set(X86::EBP);
270 Reserved.set(X86::BP);
271 Reserved.set(X86::BPL);
276 //===----------------------------------------------------------------------===//
277 // Stack Frame Processing methods
278 //===----------------------------------------------------------------------===//
280 // hasFP - Return true if the specified function should have a dedicated frame
281 // pointer register. This is true if the function has variable sized allocas or
282 // if frame pointer elimination is disabled.
284 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
285 MachineFrameInfo *MFI = MF.getFrameInfo();
286 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
288 return (NoFramePointerElim ||
289 MFI->hasVarSizedObjects() ||
290 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
291 (MMI && MMI->callsUnwindInit()));
294 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
295 return !MF.getFrameInfo()->hasVarSizedObjects();
298 void X86RegisterInfo::
299 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
300 MachineBasicBlock::iterator I) const {
301 if (!hasReservedCallFrame(MF)) {
302 // If the stack pointer can be changed after prologue, turn the
303 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
304 // adjcallstackdown instruction into 'add ESP, <amt>'
305 // TODO: consider using push / pop instead of sub + store / add
306 MachineInstr *Old = I;
307 uint64_t Amount = Old->getOperand(0).getImm();
309 // We need to keep the stack aligned properly. To do this, we round the
310 // amount of space needed for the outgoing arguments up to the next
311 // alignment boundary.
312 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
314 MachineInstr *New = 0;
315 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
316 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
317 .addReg(StackPtr).addImm(Amount);
319 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
320 // factor out the amount the callee already popped.
321 uint64_t CalleeAmt = Old->getOperand(1).getImm();
324 unsigned Opc = (Amount < 128) ?
325 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
326 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
327 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
331 // Replace the pseudo instruction with a new instruction...
332 if (New) MBB.insert(I, New);
334 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
335 // If we are performing frame pointer elimination and if the callee pops
336 // something off the stack pointer, add it back. We do this until we have
337 // more advanced stack pointer tracking ability.
338 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
339 unsigned Opc = (CalleeAmt < 128) ?
340 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
341 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
343 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
351 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
352 int SPAdj, RegScavenger *RS) const{
353 assert(SPAdj == 0 && "Unexpected");
356 MachineInstr &MI = *II;
357 MachineFunction &MF = *MI.getParent()->getParent();
358 while (!MI.getOperand(i).isFrameIndex()) {
360 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
363 int FrameIndex = MI.getOperand(i).getIndex();
364 // This must be part of a four operand memory reference. Replace the
365 // FrameIndex with base register with EBP. Add an offset to the offset.
366 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
368 // Now add the frame object offset to the offset from EBP.
369 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
370 MI.getOperand(i+3).getImm()+SlotSize;
373 Offset += MF.getFrameInfo()->getStackSize();
375 Offset += SlotSize; // Skip the saved EBP
376 // Skip the RETADDR move area
377 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
378 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
379 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
382 MI.getOperand(i+3).ChangeToImmediate(Offset);
386 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
387 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
388 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
389 if (TailCallReturnAddrDelta < 0) {
390 // create RETURNADDR area
400 CreateFixedObject(-TailCallReturnAddrDelta,
401 (-1*SlotSize)+TailCallReturnAddrDelta);
404 assert((TailCallReturnAddrDelta <= 0) &&
405 "The Delta should always be zero or negative");
406 // Create a frame entry for the EBP register that must be saved.
407 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
409 TailCallReturnAddrDelta);
410 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
411 "Slot for EBP register must be last in order to be found!");
415 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
416 /// stack pointer by a constant value.
418 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
419 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
420 const TargetInstrInfo &TII) {
421 bool isSub = NumBytes < 0;
422 uint64_t Offset = isSub ? -NumBytes : NumBytes;
425 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
426 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
428 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
429 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
430 uint64_t Chunk = (1LL << 31) - 1;
433 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
434 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
439 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
441 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
442 unsigned StackPtr, uint64_t *NumBytes = NULL) {
443 if (MBBI == MBB.begin()) return;
445 MachineBasicBlock::iterator PI = prior(MBBI);
446 unsigned Opc = PI->getOpcode();
447 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
448 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
449 PI->getOperand(0).getReg() == StackPtr) {
451 *NumBytes += PI->getOperand(2).getImm();
453 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
454 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
455 PI->getOperand(0).getReg() == StackPtr) {
457 *NumBytes -= PI->getOperand(2).getImm();
462 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
464 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
465 MachineBasicBlock::iterator &MBBI,
466 unsigned StackPtr, uint64_t *NumBytes = NULL) {
469 if (MBBI == MBB.end()) return;
471 MachineBasicBlock::iterator NI = next(MBBI);
472 if (NI == MBB.end()) return;
474 unsigned Opc = NI->getOpcode();
475 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
476 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
477 NI->getOperand(0).getReg() == StackPtr) {
479 *NumBytes -= NI->getOperand(2).getImm();
482 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
483 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
484 NI->getOperand(0).getReg() == StackPtr) {
486 *NumBytes += NI->getOperand(2).getImm();
492 /// mergeSPUpdates - Checks the instruction before/after the passed
493 /// instruction. If it is an ADD/SUB instruction it is deleted
494 /// argument and the stack adjustment is returned as a positive value for ADD
495 /// and a negative for SUB.
496 static int mergeSPUpdates(MachineBasicBlock &MBB,
497 MachineBasicBlock::iterator &MBBI,
499 bool doMergeWithPrevious) {
501 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
502 (!doMergeWithPrevious && MBBI == MBB.end()))
507 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
508 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
509 unsigned Opc = PI->getOpcode();
510 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
511 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
512 PI->getOperand(0).getReg() == StackPtr){
513 Offset += PI->getOperand(2).getImm();
515 if (!doMergeWithPrevious) MBBI = NI;
516 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
517 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
518 PI->getOperand(0).getReg() == StackPtr) {
519 Offset -= PI->getOperand(2).getImm();
521 if (!doMergeWithPrevious) MBBI = NI;
527 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
528 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
529 MachineFrameInfo *MFI = MF.getFrameInfo();
530 const Function* Fn = MF.getFunction();
531 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
532 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
533 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
534 MachineBasicBlock::iterator MBBI = MBB.begin();
536 // Prepare for frame info.
537 unsigned FrameLabelId = 0;
539 // Get the number of bytes to allocate from the FrameInfo.
540 uint64_t StackSize = MFI->getStackSize();
541 // Add RETADDR move area to callee saved frame size.
542 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
543 if (TailCallReturnAddrDelta < 0)
544 X86FI->setCalleeSavedFrameSize(
545 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
546 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
548 // Insert stack pointer adjustment for later moving of return addr. Only
549 // applies to tail call optimized functions where the callee argument stack
550 // size is bigger than the callers.
551 if (TailCallReturnAddrDelta < 0) {
552 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
553 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
557 // Get the offset of the stack slot for the EBP register... which is
558 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
559 // Update the frame offset adjustment.
560 MFI->setOffsetAdjustment(SlotSize-NumBytes);
562 // Save EBP into the appropriate stack slot...
563 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
565 NumBytes -= SlotSize;
567 if (MMI && MMI->needsFrameInfo()) {
568 // Mark effective beginning of when frame pointer becomes valid.
569 FrameLabelId = MMI->NextLabelID();
570 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
573 // Update EBP with the new base value...
574 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
578 unsigned ReadyLabelId = 0;
579 if (MMI && MMI->needsFrameInfo()) {
580 // Mark effective beginning of when frame pointer is ready.
581 ReadyLabelId = MMI->NextLabelID();
582 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
585 // Skip the callee-saved push instructions.
586 while (MBBI != MBB.end() &&
587 (MBBI->getOpcode() == X86::PUSH32r ||
588 MBBI->getOpcode() == X86::PUSH64r))
591 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
592 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
593 // Check, whether EAX is livein for this function
594 bool isEAXAlive = false;
595 for (MachineRegisterInfo::livein_iterator
596 II = MF.getRegInfo().livein_begin(),
597 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
598 unsigned Reg = II->first;
599 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
600 Reg == X86::AH || Reg == X86::AL);
603 // Function prologue calls _alloca to probe the stack when allocating
604 // more than 4k bytes in one go. Touching the stack at 4K increments is
605 // necessary to ensure that the guard pages used by the OS virtual memory
606 // manager are allocated in correct sequence.
608 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
609 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
610 .addExternalSymbol("_alloca");
613 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
614 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
615 // allocated bytes for EAX.
616 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
617 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
618 .addExternalSymbol("_alloca");
620 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
621 StackPtr, NumBytes-4);
622 MBB.insert(MBBI, MI);
625 // If there is an SUB32ri of ESP immediately before this instruction,
626 // merge the two. This can be the case when tail call elimination is
627 // enabled and the callee has more arguments then the caller.
628 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
629 // If there is an ADD32ri or SUB32ri of ESP immediately after this
630 // instruction, merge the two instructions.
631 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
634 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
638 if (MMI && MMI->needsFrameInfo()) {
639 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
640 const TargetData *TD = MF.getTarget().getTargetData();
642 // Calculate amount of bytes used for return address storing
644 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
645 TargetFrameInfo::StackGrowsUp ?
646 TD->getPointerSize() : -TD->getPointerSize());
649 // Show update of SP.
652 MachineLocation SPDst(MachineLocation::VirtualFP);
653 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
654 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
656 MachineLocation SPDst(MachineLocation::VirtualFP);
657 MachineLocation SPSrc(MachineLocation::VirtualFP,
658 -StackSize+stackGrowth);
659 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
662 //FIXME: Verify & implement for FP
663 MachineLocation SPDst(StackPtr);
664 MachineLocation SPSrc(StackPtr, stackGrowth);
665 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
668 // Add callee saved registers to move list.
669 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
671 // FIXME: This is dirty hack. The code itself is pretty mess right now.
672 // It should be rewritten from scratch and generalized sometimes.
674 // Determine maximum offset (minumum due to stack growth)
675 int64_t MaxOffset = 0;
676 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
677 MaxOffset = std::min(MaxOffset,
678 MFI->getObjectOffset(CSI[I].getFrameIdx()));
681 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
682 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
683 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
684 unsigned Reg = CSI[I].getReg();
685 Offset = (MaxOffset-Offset+saveAreaOffset);
686 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
687 MachineLocation CSSrc(Reg);
688 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
693 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
694 MachineLocation FPSrc(FramePtr);
695 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
698 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
699 MachineLocation FPSrc(MachineLocation::VirtualFP);
700 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
703 // If it's main() on Cygwin\Mingw32 we should align stack as well
704 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
705 Subtarget->isTargetCygMing()) {
706 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
707 .addReg(X86::ESP).addImm(-StackAlign);
710 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
711 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
715 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
716 MachineBasicBlock &MBB) const {
717 const MachineFrameInfo *MFI = MF.getFrameInfo();
718 const Function* Fn = MF.getFunction();
719 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
720 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
721 MachineBasicBlock::iterator MBBI = prior(MBB.end());
722 unsigned RetOpcode = MBBI->getOpcode();
727 case X86::TCRETURNdi:
728 case X86::TCRETURNri:
729 case X86::TCRETURNri64:
730 case X86::TCRETURNdi64:
734 case X86::TAILJMPm: break; // These are ok
736 assert(0 && "Can only insert epilog into returning blocks");
739 // Get the number of bytes to allocate from the FrameInfo
740 uint64_t StackSize = MFI->getStackSize();
741 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
742 uint64_t NumBytes = StackSize - CSSize;
746 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
747 NumBytes -= SlotSize;
750 // Skip the callee-saved pop instructions.
751 while (MBBI != MBB.begin()) {
752 MachineBasicBlock::iterator PI = prior(MBBI);
753 unsigned Opc = PI->getOpcode();
754 if (Opc != X86::POP32r && Opc != X86::POP64r &&
755 !PI->getDesc().isTerminator())
760 // If there is an ADD32ri or SUB32ri of ESP immediately before this
761 // instruction, merge the two instructions.
762 if (NumBytes || MFI->hasVarSizedObjects())
763 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
765 // If dynamic alloca is used, then reset esp to point to the last callee-saved
766 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
767 // aligned stack in the prologue, - revert stack changes back. Note: we're
768 // assuming, that frame pointer was forced for main()
769 if (MFI->hasVarSizedObjects() ||
770 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
771 Subtarget->isTargetCygMing())) {
772 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
774 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
776 MBB.insert(MBBI, MI);
778 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
784 // adjust stack pointer back: ESP += numbytes
786 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
788 // We're returning from function via eh_return.
789 if (RetOpcode == X86::EH_RETURN) {
790 MBBI = prior(MBB.end());
791 MachineOperand &DestAddr = MBBI->getOperand(0);
792 assert(DestAddr.isRegister() && "Offset should be in register!");
793 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
794 addReg(DestAddr.getReg());
795 // Tail call return: adjust the stack pointer and jump to callee
796 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
797 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
798 MBBI = prior(MBB.end());
799 MachineOperand &JumpTarget = MBBI->getOperand(0);
800 MachineOperand &StackAdjust = MBBI->getOperand(1);
801 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
803 // Adjust stack pointer.
804 int StackAdj = StackAdjust.getImm();
805 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
807 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
808 // Incoporate the retaddr area.
809 Offset = StackAdj-MaxTCDelta;
810 assert(Offset >= 0 && "Offset should never be negative");
812 // Check for possible merge with preceeding ADD instruction.
813 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
814 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
816 // Jump to label or value in register.
817 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
818 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
819 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
820 else if (RetOpcode== X86::TCRETURNri64) {
821 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
823 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
824 // Delete the pseudo instruction TCRETURN.
826 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
827 (X86FI->getTCReturnAddrDelta() < 0)) {
828 // Add the return addr area delta back since we are not tail calling.
829 int delta = -1*X86FI->getTCReturnAddrDelta();
830 MBBI = prior(MBB.end());
831 // Check for possible merge with preceeding ADD instruction.
832 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
833 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
837 unsigned X86RegisterInfo::getRARegister() const {
839 return X86::RIP; // Should have dwarf #16
841 return X86::EIP; // Should have dwarf #8
844 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
845 return hasFP(MF) ? FramePtr : StackPtr;
849 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
850 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
852 return Offset + MF.getFrameInfo()->getStackSize();
854 Offset += SlotSize; // Skip the saved EBP
855 // Skip the RETADDR move area
856 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
857 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
858 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
862 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
864 // Calculate amount of bytes used for return address storing
865 int stackGrowth = (Is64Bit ? -8 : -4);
867 // Initial state of the frame pointer is esp+4.
868 MachineLocation Dst(MachineLocation::VirtualFP);
869 MachineLocation Src(StackPtr, stackGrowth);
870 Moves.push_back(MachineMove(0, Dst, Src));
872 // Add return address to move list
873 MachineLocation CSDst(StackPtr, stackGrowth);
874 MachineLocation CSSrc(getRARegister());
875 Moves.push_back(MachineMove(0, CSDst, CSSrc));
878 unsigned X86RegisterInfo::getEHExceptionRegister() const {
879 assert(0 && "What is the exception register");
883 unsigned X86RegisterInfo::getEHHandlerRegister() const {
884 assert(0 && "What is the exception handler register");
889 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
896 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
898 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
900 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
902 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
908 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
910 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
912 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
914 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
916 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
918 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
920 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
922 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
924 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
926 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
928 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
930 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
932 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
934 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
936 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
938 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
945 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
947 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
949 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
951 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
953 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
955 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
957 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
959 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
961 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
963 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
965 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
967 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
969 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
971 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
973 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
975 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
981 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
983 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
985 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
987 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
989 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
991 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
993 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
995 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
997 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
999 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1001 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1003 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1005 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1007 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1009 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1011 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1016 default: return Reg;
1017 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1019 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1021 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1023 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1025 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1027 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1029 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1031 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1033 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1035 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1037 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1039 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1041 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1043 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1045 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1047 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1056 #include "X86GenRegisterInfo.inc"