1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
41 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
42 const TargetInstrInfo &tii)
43 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
45 // Cache some information.
46 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
47 Is64Bit = Subtarget->is64Bit();
48 IsWin64 = Subtarget->isTargetWin64();
49 StackAlign = TM.getFrameInfo()->getStackAlignment();
61 // getDwarfRegNum - This function maps LLVM register identifiers to the
62 // Dwarf specific numbering, used in debug info and exception tables.
64 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
65 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
66 unsigned Flavour = DWARFFlavour::X86_64;
67 if (!Subtarget->is64Bit()) {
68 if (Subtarget->isTargetDarwin()) {
70 Flavour = DWARFFlavour::X86_32_DarwinEH;
72 Flavour = DWARFFlavour::X86_32_Generic;
73 } else if (Subtarget->isTargetCygMing()) {
74 // Unsupported by now, just quick fallback
75 Flavour = DWARFFlavour::X86_32_Generic;
77 Flavour = DWARFFlavour::X86_32_Generic;
81 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
84 // getX86RegNum - This function maps LLVM register identifiers to their X86
85 // specific numbering, which is used in various places encoding instructions.
87 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
89 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
90 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
91 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
92 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
93 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
95 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
97 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
99 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
102 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
106 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
108 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
110 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
112 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
114 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
116 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
119 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
120 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
121 return RegNo-X86::ST0;
123 case X86::XMM0: case X86::XMM8: case X86::MM0:
125 case X86::XMM1: case X86::XMM9: case X86::MM1:
127 case X86::XMM2: case X86::XMM10: case X86::MM2:
129 case X86::XMM3: case X86::XMM11: case X86::MM3:
131 case X86::XMM4: case X86::XMM12: case X86::MM4:
133 case X86::XMM5: case X86::XMM13: case X86::MM5:
135 case X86::XMM6: case X86::XMM14: case X86::MM6:
137 case X86::XMM7: case X86::XMM15: case X86::MM7:
141 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
142 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
147 const TargetRegisterClass *
148 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
149 if (RC == &X86::CCRRegClass) {
151 return &X86::GR64RegClass;
153 return &X86::GR32RegClass;
159 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
160 static const unsigned CalleeSavedRegs32Bit[] = {
161 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
164 static const unsigned CalleeSavedRegs32EHRet[] = {
165 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
168 static const unsigned CalleeSavedRegs64Bit[] = {
169 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
172 static const unsigned CalleeSavedRegsWin64[] = {
173 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
174 X86::R12, X86::R13, X86::R14, X86::R15, 0
179 return CalleeSavedRegsWin64;
181 return CalleeSavedRegs64Bit;
184 MachineFrameInfo *MFI = MF->getFrameInfo();
185 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
186 if (MMI && MMI->callsEHReturn())
187 return CalleeSavedRegs32EHRet;
189 return CalleeSavedRegs32Bit;
193 const TargetRegisterClass* const*
194 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
195 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
196 &X86::GR32RegClass, &X86::GR32RegClass,
197 &X86::GR32RegClass, &X86::GR32RegClass, 0
199 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
200 &X86::GR32RegClass, &X86::GR32RegClass,
201 &X86::GR32RegClass, &X86::GR32RegClass,
202 &X86::GR32RegClass, &X86::GR32RegClass, 0
204 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
205 &X86::GR64RegClass, &X86::GR64RegClass,
206 &X86::GR64RegClass, &X86::GR64RegClass,
207 &X86::GR64RegClass, &X86::GR64RegClass, 0
209 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
210 &X86::GR64RegClass, &X86::GR64RegClass,
211 &X86::GR64RegClass, &X86::GR64RegClass,
212 &X86::GR64RegClass, &X86::GR64RegClass,
213 &X86::GR64RegClass, &X86::GR64RegClass, 0
218 return CalleeSavedRegClassesWin64;
220 return CalleeSavedRegClasses64Bit;
223 MachineFrameInfo *MFI = MF->getFrameInfo();
224 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225 if (MMI && MMI->callsEHReturn())
226 return CalleeSavedRegClasses32EHRet;
228 return CalleeSavedRegClasses32Bit;
233 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
234 BitVector Reserved(getNumRegs());
235 Reserved.set(X86::RSP);
236 Reserved.set(X86::ESP);
237 Reserved.set(X86::SP);
238 Reserved.set(X86::SPL);
240 Reserved.set(X86::RBP);
241 Reserved.set(X86::EBP);
242 Reserved.set(X86::BP);
243 Reserved.set(X86::BPL);
248 //===----------------------------------------------------------------------===//
249 // Stack Frame Processing methods
250 //===----------------------------------------------------------------------===//
252 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
253 unsigned MaxAlign = 0;
254 for (int i = FFI->getObjectIndexBegin(),
255 e = FFI->getObjectIndexEnd(); i != e; ++i) {
256 if (FFI->isDeadObjectIndex(i))
258 unsigned Align = FFI->getObjectAlignment(i);
259 MaxAlign = std::max(MaxAlign, Align);
265 // hasFP - Return true if the specified function should have a dedicated frame
266 // pointer register. This is true if the function has variable sized allocas or
267 // if frame pointer elimination is disabled.
269 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
270 MachineFrameInfo *MFI = MF.getFrameInfo();
271 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
273 return (NoFramePointerElim ||
274 needsStackRealignment(MF) ||
275 MFI->hasVarSizedObjects() ||
276 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
277 (MMI && MMI->callsUnwindInit()));
280 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
281 MachineFrameInfo *MFI = MF.getFrameInfo();;
283 // FIXME: This is really really ugly, but it seems we need to decide, whether
284 // we will need stack realignment or not too early (during RA stage).
285 unsigned MaxAlign = MFI->getMaxAlignment();
287 MaxAlign = calculateMaxStackAlignment(MFI);
289 // FIXME: Currently we don't support stack realignment for functions with
290 // variable-sized allocas
291 return (RealignStack &&
292 (MaxAlign > StackAlign &&
293 !MFI->hasVarSizedObjects()));
296 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
297 return !MF.getFrameInfo()->hasVarSizedObjects();
301 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
302 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
303 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
305 if (needsStackRealignment(MF)) {
307 // Skip the saved EBP
310 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment();
312 (StackSize - SlotSize + MaxAlign - 1)/MaxAlign*MaxAlign;
314 return Offset + FrameSize - SlotSize;
317 // FIXME: Support tail calls
320 return Offset + StackSize;
322 // Skip the saved EBP
325 // Skip the RETADDR move area
326 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
327 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
328 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
334 void X86RegisterInfo::
335 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
336 MachineBasicBlock::iterator I) const {
337 if (!hasReservedCallFrame(MF)) {
338 // If the stack pointer can be changed after prologue, turn the
339 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
340 // adjcallstackdown instruction into 'add ESP, <amt>'
341 // TODO: consider using push / pop instead of sub + store / add
342 MachineInstr *Old = I;
343 uint64_t Amount = Old->getOperand(0).getImm();
345 // We need to keep the stack aligned properly. To do this, we round the
346 // amount of space needed for the outgoing arguments up to the next
347 // alignment boundary.
348 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
350 MachineInstr *New = 0;
351 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
352 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
353 .addReg(StackPtr).addImm(Amount);
355 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
356 // factor out the amount the callee already popped.
357 uint64_t CalleeAmt = Old->getOperand(1).getImm();
360 unsigned Opc = (Amount < 128) ?
361 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
362 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
363 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
367 // Replace the pseudo instruction with a new instruction...
368 if (New) MBB.insert(I, New);
370 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
371 // If we are performing frame pointer elimination and if the callee pops
372 // something off the stack pointer, add it back. We do this until we have
373 // more advanced stack pointer tracking ability.
374 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
375 unsigned Opc = (CalleeAmt < 128) ?
376 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
377 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
379 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
387 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
388 int SPAdj, RegScavenger *RS) const{
389 assert(SPAdj == 0 && "Unexpected");
392 MachineInstr &MI = *II;
393 MachineFunction &MF = *MI.getParent()->getParent();
394 while (!MI.getOperand(i).isFrameIndex()) {
396 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
399 int FrameIndex = MI.getOperand(i).getIndex();
402 if (needsStackRealignment(MF))
403 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
405 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
407 // This must be part of a four operand memory reference. Replace the
408 // FrameIndex with base register with EBP. Add an offset to the offset.
409 MI.getOperand(i).ChangeToRegister(BasePtr, false);
411 // Now add the frame object offset to the offset from EBP.
412 int64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
413 MI.getOperand(i+3).getImm();
415 MI.getOperand(i+3).ChangeToImmediate(Offset);
419 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
420 RegScavenger *RS) const {
421 MachineFrameInfo *FFI = MF.getFrameInfo();
423 // Calculate and set max stack object alignment early, so we can decide
424 // whether we will need stack realignment (and thus FP).
425 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
427 FFI->setMaxAlignment(MaxAlign);
431 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
432 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
433 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
434 if (TailCallReturnAddrDelta < 0) {
435 // create RETURNADDR area
445 CreateFixedObject(-TailCallReturnAddrDelta,
446 (-1*SlotSize)+TailCallReturnAddrDelta);
449 assert((TailCallReturnAddrDelta <= 0) &&
450 "The Delta should always be zero or negative");
451 // Create a frame entry for the EBP register that must be saved.
452 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
454 TailCallReturnAddrDelta);
455 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
456 "Slot for EBP register must be last in order to be found!");
460 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
461 /// stack pointer by a constant value.
463 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
464 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
465 const TargetInstrInfo &TII) {
466 bool isSub = NumBytes < 0;
467 uint64_t Offset = isSub ? -NumBytes : NumBytes;
470 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
471 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
473 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
474 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
475 uint64_t Chunk = (1LL << 31) - 1;
478 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
479 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
484 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
486 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
487 unsigned StackPtr, uint64_t *NumBytes = NULL) {
488 if (MBBI == MBB.begin()) return;
490 MachineBasicBlock::iterator PI = prior(MBBI);
491 unsigned Opc = PI->getOpcode();
492 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
493 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
494 PI->getOperand(0).getReg() == StackPtr) {
496 *NumBytes += PI->getOperand(2).getImm();
498 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
499 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
500 PI->getOperand(0).getReg() == StackPtr) {
502 *NumBytes -= PI->getOperand(2).getImm();
507 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
509 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
510 MachineBasicBlock::iterator &MBBI,
511 unsigned StackPtr, uint64_t *NumBytes = NULL) {
514 if (MBBI == MBB.end()) return;
516 MachineBasicBlock::iterator NI = next(MBBI);
517 if (NI == MBB.end()) return;
519 unsigned Opc = NI->getOpcode();
520 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
521 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
522 NI->getOperand(0).getReg() == StackPtr) {
524 *NumBytes -= NI->getOperand(2).getImm();
527 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
528 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
529 NI->getOperand(0).getReg() == StackPtr) {
531 *NumBytes += NI->getOperand(2).getImm();
537 /// mergeSPUpdates - Checks the instruction before/after the passed
538 /// instruction. If it is an ADD/SUB instruction it is deleted
539 /// argument and the stack adjustment is returned as a positive value for ADD
540 /// and a negative for SUB.
541 static int mergeSPUpdates(MachineBasicBlock &MBB,
542 MachineBasicBlock::iterator &MBBI,
544 bool doMergeWithPrevious) {
546 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
547 (!doMergeWithPrevious && MBBI == MBB.end()))
552 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
553 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
554 unsigned Opc = PI->getOpcode();
555 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
556 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
557 PI->getOperand(0).getReg() == StackPtr){
558 Offset += PI->getOperand(2).getImm();
560 if (!doMergeWithPrevious) MBBI = NI;
561 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
562 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
563 PI->getOperand(0).getReg() == StackPtr) {
564 Offset -= PI->getOperand(2).getImm();
566 if (!doMergeWithPrevious) MBBI = NI;
572 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
573 unsigned FrameLabelId,
574 unsigned ReadyLabelId) const {
575 MachineFrameInfo *MFI = MF.getFrameInfo();
576 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
580 uint64_t StackSize = MFI->getStackSize();
581 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
582 const TargetData *TD = MF.getTarget().getTargetData();
584 // Calculate amount of bytes used for return address storing
586 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
587 TargetFrameInfo::StackGrowsUp ?
588 TD->getPointerSize() : -TD->getPointerSize());
591 // Show update of SP.
594 MachineLocation SPDst(MachineLocation::VirtualFP);
595 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
596 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
598 MachineLocation SPDst(MachineLocation::VirtualFP);
599 MachineLocation SPSrc(MachineLocation::VirtualFP,
600 -StackSize+stackGrowth);
601 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
604 //FIXME: Verify & implement for FP
605 MachineLocation SPDst(StackPtr);
606 MachineLocation SPSrc(StackPtr, stackGrowth);
607 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
610 // Add callee saved registers to move list.
611 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
613 // FIXME: This is dirty hack. The code itself is pretty mess right now.
614 // It should be rewritten from scratch and generalized sometimes.
616 // Determine maximum offset (minumum due to stack growth)
617 int64_t MaxOffset = 0;
618 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
619 MaxOffset = std::min(MaxOffset,
620 MFI->getObjectOffset(CSI[I].getFrameIdx()));
623 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
624 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
625 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
626 unsigned Reg = CSI[I].getReg();
627 Offset = (MaxOffset-Offset+saveAreaOffset);
628 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
629 MachineLocation CSSrc(Reg);
630 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
635 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
636 MachineLocation FPSrc(FramePtr);
637 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
640 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
641 MachineLocation FPSrc(MachineLocation::VirtualFP);
642 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
646 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
647 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
648 MachineFrameInfo *MFI = MF.getFrameInfo();
649 const Function* Fn = MF.getFunction();
650 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
651 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
652 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
653 MachineBasicBlock::iterator MBBI = MBB.begin();
654 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
655 !Fn->doesNotThrow() ||
656 UnwindTablesMandatory;
657 // Prepare for frame info.
658 unsigned FrameLabelId = 0;
660 // Get the number of bytes to allocate from the FrameInfo.
661 uint64_t StackSize = MFI->getStackSize();
662 // Get desired stack alignment
663 uint64_t MaxAlign = MFI->getMaxAlignment();
665 // Add RETADDR move area to callee saved frame size.
666 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
667 if (TailCallReturnAddrDelta < 0)
668 X86FI->setCalleeSavedFrameSize(
669 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
671 // Insert stack pointer adjustment for later moving of return addr. Only
672 // applies to tail call optimized functions where the callee argument stack
673 // size is bigger than the callers.
674 if (TailCallReturnAddrDelta < 0) {
675 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
676 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
679 uint64_t NumBytes = 0;
681 // Calculate required stack adjustment
682 uint64_t FrameSize = StackSize - SlotSize;
683 if (needsStackRealignment(MF))
684 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
686 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
688 // Get the offset of the stack slot for the EBP register... which is
689 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
690 // Update the frame offset adjustment.
691 MFI->setOffsetAdjustment(-NumBytes);
693 // Save EBP into the appropriate stack slot...
694 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
697 if (needsFrameMoves) {
698 // Mark effective beginning of when frame pointer becomes valid.
699 FrameLabelId = MMI->NextLabelID();
700 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
703 // Update EBP with the new base value...
704 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
708 if (needsStackRealignment(MF))
710 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
711 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
713 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
715 unsigned ReadyLabelId = 0;
716 if (needsFrameMoves) {
717 // Mark effective beginning of when frame pointer is ready.
718 ReadyLabelId = MMI->NextLabelID();
719 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
722 // Skip the callee-saved push instructions.
723 while (MBBI != MBB.end() &&
724 (MBBI->getOpcode() == X86::PUSH32r ||
725 MBBI->getOpcode() == X86::PUSH64r))
728 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
729 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
730 // Check, whether EAX is livein for this function
731 bool isEAXAlive = false;
732 for (MachineRegisterInfo::livein_iterator
733 II = MF.getRegInfo().livein_begin(),
734 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
735 unsigned Reg = II->first;
736 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
737 Reg == X86::AH || Reg == X86::AL);
740 // Function prologue calls _alloca to probe the stack when allocating
741 // more than 4k bytes in one go. Touching the stack at 4K increments is
742 // necessary to ensure that the guard pages used by the OS virtual memory
743 // manager are allocated in correct sequence.
745 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
746 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
747 .addExternalSymbol("_alloca");
750 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
751 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
752 // allocated bytes for EAX.
753 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
754 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
755 .addExternalSymbol("_alloca");
757 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
758 StackPtr, NumBytes-4);
759 MBB.insert(MBBI, MI);
762 // If there is an SUB32ri of ESP immediately before this instruction,
763 // merge the two. This can be the case when tail call elimination is
764 // enabled and the callee has more arguments then the caller.
765 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
766 // If there is an ADD32ri or SUB32ri of ESP immediately after this
767 // instruction, merge the two instructions.
768 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
771 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
776 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
779 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
780 MachineBasicBlock &MBB) const {
781 const MachineFrameInfo *MFI = MF.getFrameInfo();
782 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
783 MachineBasicBlock::iterator MBBI = prior(MBB.end());
784 unsigned RetOpcode = MBBI->getOpcode();
789 case X86::TCRETURNdi:
790 case X86::TCRETURNri:
791 case X86::TCRETURNri64:
792 case X86::TCRETURNdi64:
796 case X86::TAILJMPm: break; // These are ok
798 assert(0 && "Can only insert epilog into returning blocks");
801 // Get the number of bytes to allocate from the FrameInfo
802 uint64_t StackSize = MFI->getStackSize();
803 uint64_t MaxAlign = MFI->getMaxAlignment();
804 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
805 uint64_t NumBytes = 0;
808 // Calculate required stack adjustment
809 uint64_t FrameSize = StackSize - SlotSize;
810 if (needsStackRealignment(MF))
811 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
813 NumBytes = FrameSize - CSSize;
816 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
818 NumBytes = StackSize - CSSize;
820 // Skip the callee-saved pop instructions.
821 MachineBasicBlock::iterator LastCSPop = MBBI;
822 while (MBBI != MBB.begin()) {
823 MachineBasicBlock::iterator PI = prior(MBBI);
824 unsigned Opc = PI->getOpcode();
825 if (Opc != X86::POP32r && Opc != X86::POP64r &&
826 !PI->getDesc().isTerminator())
831 // If there is an ADD32ri or SUB32ri of ESP immediately before this
832 // instruction, merge the two instructions.
833 if (NumBytes || MFI->hasVarSizedObjects())
834 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
836 // If dynamic alloca is used, then reset esp to point to the last callee-saved
837 // slot before popping them off! Same applies for the case, when stack was
839 if (needsStackRealignment(MF)) {
840 // We cannot use LEA here, because stack pointer was realigned. We need to
841 // deallocate local frame back
843 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
844 MBBI = prior(LastCSPop);
848 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
849 StackPtr).addReg(FramePtr);
850 } else if (MFI->hasVarSizedObjects()) {
852 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
853 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
855 MBB.insert(MBBI, MI);
857 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
861 // adjust stack pointer back: ESP += numbytes
863 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
866 // We're returning from function via eh_return.
867 if (RetOpcode == X86::EH_RETURN) {
868 MBBI = prior(MBB.end());
869 MachineOperand &DestAddr = MBBI->getOperand(0);
870 assert(DestAddr.isRegister() && "Offset should be in register!");
871 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
872 addReg(DestAddr.getReg());
873 // Tail call return: adjust the stack pointer and jump to callee
874 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
875 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
876 MBBI = prior(MBB.end());
877 MachineOperand &JumpTarget = MBBI->getOperand(0);
878 MachineOperand &StackAdjust = MBBI->getOperand(1);
879 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
881 // Adjust stack pointer.
882 int StackAdj = StackAdjust.getImm();
883 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
885 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
886 // Incoporate the retaddr area.
887 Offset = StackAdj-MaxTCDelta;
888 assert(Offset >= 0 && "Offset should never be negative");
890 // Check for possible merge with preceeding ADD instruction.
891 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
892 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
894 // Jump to label or value in register.
895 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
896 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
897 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
898 else if (RetOpcode== X86::TCRETURNri64) {
899 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
901 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
902 // Delete the pseudo instruction TCRETURN.
904 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
905 (X86FI->getTCReturnAddrDelta() < 0)) {
906 // Add the return addr area delta back since we are not tail calling.
907 int delta = -1*X86FI->getTCReturnAddrDelta();
908 MBBI = prior(MBB.end());
909 // Check for possible merge with preceeding ADD instruction.
910 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
911 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
915 unsigned X86RegisterInfo::getRARegister() const {
917 return X86::RIP; // Should have dwarf #16
919 return X86::EIP; // Should have dwarf #8
922 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
923 return hasFP(MF) ? FramePtr : StackPtr;
926 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
928 // Calculate amount of bytes used for return address storing
929 int stackGrowth = (Is64Bit ? -8 : -4);
931 // Initial state of the frame pointer is esp+4.
932 MachineLocation Dst(MachineLocation::VirtualFP);
933 MachineLocation Src(StackPtr, stackGrowth);
934 Moves.push_back(MachineMove(0, Dst, Src));
936 // Add return address to move list
937 MachineLocation CSDst(StackPtr, stackGrowth);
938 MachineLocation CSSrc(getRARegister());
939 Moves.push_back(MachineMove(0, CSDst, CSSrc));
942 unsigned X86RegisterInfo::getEHExceptionRegister() const {
943 assert(0 && "What is the exception register");
947 unsigned X86RegisterInfo::getEHHandlerRegister() const {
948 assert(0 && "What is the exception handler register");
953 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
960 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
962 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
964 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
966 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
972 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
974 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
976 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
978 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
980 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
982 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
984 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
986 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
988 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
990 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
992 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
994 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
996 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
998 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1000 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1002 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1008 default: return Reg;
1009 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1011 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1013 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1015 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1017 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1019 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1021 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1023 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1025 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1027 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1029 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1031 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1033 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1035 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1037 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1039 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1044 default: return Reg;
1045 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1047 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1049 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1051 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1053 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1055 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1057 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1059 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1061 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1063 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1065 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1067 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1069 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1071 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1073 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1075 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1080 default: return Reg;
1081 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1083 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1085 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1087 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1089 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1091 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1093 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1095 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1097 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1099 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1101 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1103 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1105 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1107 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1109 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1111 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1120 #include "X86GenRegisterInfo.inc"