1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
47 // Cache some information.
48 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
49 Is64Bit = Subtarget->is64Bit();
50 IsWin64 = Subtarget->isTargetWin64();
51 StackAlign = TM.getFrameInfo()->getStackAlignment();
63 // getDwarfRegNum - This function maps LLVM register identifiers to the
64 // Dwarf specific numbering, used in debug info and exception tables.
66 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
67 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
68 unsigned Flavour = DWARFFlavour::X86_64;
69 if (!Subtarget->is64Bit()) {
70 if (Subtarget->isTargetDarwin()) {
72 Flavour = DWARFFlavour::X86_32_DarwinEH;
74 Flavour = DWARFFlavour::X86_32_Generic;
75 } else if (Subtarget->isTargetCygMing()) {
76 // Unsupported by now, just quick fallback
77 Flavour = DWARFFlavour::X86_32_Generic;
79 Flavour = DWARFFlavour::X86_32_Generic;
83 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
86 // getX86RegNum - This function maps LLVM register identifiers to their X86
87 // specific numbering, which is used in various places encoding instructions.
89 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
91 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
92 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
93 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
94 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
95 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
97 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
99 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
101 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
104 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
106 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
108 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
110 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
112 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
114 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
116 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
118 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
121 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
122 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
123 return RegNo-X86::ST0;
125 case X86::XMM0: case X86::XMM8: case X86::MM0:
127 case X86::XMM1: case X86::XMM9: case X86::MM1:
129 case X86::XMM2: case X86::XMM10: case X86::MM2:
131 case X86::XMM3: case X86::XMM11: case X86::MM3:
133 case X86::XMM4: case X86::XMM12: case X86::MM4:
135 case X86::XMM5: case X86::XMM13: case X86::MM5:
137 case X86::XMM6: case X86::XMM14: case X86::MM6:
139 case X86::XMM7: case X86::XMM15: case X86::MM7:
143 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
144 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
149 const TargetRegisterClass *
150 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
151 if (RC == &X86::CCRRegClass) {
153 return &X86::GR64RegClass;
155 return &X86::GR32RegClass;
161 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
162 bool callsEHReturn = false;
165 const MachineFrameInfo *MFI = MF->getFrameInfo();
166 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
167 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
170 static const unsigned CalleeSavedRegs32Bit[] = {
171 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
174 static const unsigned CalleeSavedRegs32EHRet[] = {
175 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
178 static const unsigned CalleeSavedRegs64Bit[] = {
179 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
182 static const unsigned CalleeSavedRegs64EHRet[] = {
183 X86::RAX, X86::RDX, X86::RBX, X86::R12,
184 X86::R13, X86::R14, X86::R15, X86::RBP, 0
187 static const unsigned CalleeSavedRegsWin64[] = {
188 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
189 X86::R12, X86::R13, X86::R14, X86::R15,
190 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
191 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
192 X86::XMM14, X86::XMM15, 0
197 return CalleeSavedRegsWin64;
199 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
201 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
205 const TargetRegisterClass* const*
206 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
207 bool callsEHReturn = false;
210 const MachineFrameInfo *MFI = MF->getFrameInfo();
211 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
212 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
215 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
216 &X86::GR32RegClass, &X86::GR32RegClass,
217 &X86::GR32RegClass, &X86::GR32RegClass, 0
219 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
220 &X86::GR32RegClass, &X86::GR32RegClass,
221 &X86::GR32RegClass, &X86::GR32RegClass,
222 &X86::GR32RegClass, &X86::GR32RegClass, 0
224 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
225 &X86::GR64RegClass, &X86::GR64RegClass,
226 &X86::GR64RegClass, &X86::GR64RegClass,
227 &X86::GR64RegClass, &X86::GR64RegClass, 0
229 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
230 &X86::GR64RegClass, &X86::GR64RegClass,
231 &X86::GR64RegClass, &X86::GR64RegClass,
232 &X86::GR64RegClass, &X86::GR64RegClass,
233 &X86::GR64RegClass, &X86::GR64RegClass, 0
235 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
236 &X86::GR64RegClass, &X86::GR64RegClass,
237 &X86::GR64RegClass, &X86::GR64RegClass,
238 &X86::GR64RegClass, &X86::GR64RegClass,
239 &X86::GR64RegClass, &X86::GR64RegClass,
240 &X86::VR128RegClass, &X86::VR128RegClass,
241 &X86::VR128RegClass, &X86::VR128RegClass,
242 &X86::VR128RegClass, &X86::VR128RegClass,
243 &X86::VR128RegClass, &X86::VR128RegClass,
244 &X86::VR128RegClass, &X86::VR128RegClass, 0
249 return CalleeSavedRegClassesWin64;
251 return (callsEHReturn ?
252 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
254 return (callsEHReturn ?
255 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
259 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
260 BitVector Reserved(getNumRegs());
261 Reserved.set(X86::RSP);
262 Reserved.set(X86::ESP);
263 Reserved.set(X86::SP);
264 Reserved.set(X86::SPL);
266 Reserved.set(X86::RBP);
267 Reserved.set(X86::EBP);
268 Reserved.set(X86::BP);
269 Reserved.set(X86::BPL);
274 //===----------------------------------------------------------------------===//
275 // Stack Frame Processing methods
276 //===----------------------------------------------------------------------===//
278 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
279 unsigned MaxAlign = 0;
280 for (int i = FFI->getObjectIndexBegin(),
281 e = FFI->getObjectIndexEnd(); i != e; ++i) {
282 if (FFI->isDeadObjectIndex(i))
284 unsigned Align = FFI->getObjectAlignment(i);
285 MaxAlign = std::max(MaxAlign, Align);
291 // hasFP - Return true if the specified function should have a dedicated frame
292 // pointer register. This is true if the function has variable sized allocas or
293 // if frame pointer elimination is disabled.
295 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
296 const MachineFrameInfo *MFI = MF.getFrameInfo();
297 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
299 return (NoFramePointerElim ||
300 needsStackRealignment(MF) ||
301 MFI->hasVarSizedObjects() ||
302 MFI->isFrameAddressTaken() ||
303 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
304 (MMI && MMI->callsUnwindInit()));
307 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
308 const MachineFrameInfo *MFI = MF.getFrameInfo();;
310 // FIXME: Currently we don't support stack realignment for functions with
311 // variable-sized allocas
312 return (RealignStack &&
313 (MFI->getMaxAlignment() > StackAlign &&
314 !MFI->hasVarSizedObjects()));
317 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
318 return !MF.getFrameInfo()->hasVarSizedObjects();
322 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
323 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
324 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
326 if (needsStackRealignment(MF)) {
328 // Skip the saved EBP
331 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
332 assert( (-(Offset + StackSize)) % Align == 0);
333 return Offset + StackSize;
336 // FIXME: Support tail calls
339 return Offset + StackSize;
341 // Skip the saved EBP
344 // Skip the RETADDR move area
345 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
346 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
347 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
353 void X86RegisterInfo::
354 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
355 MachineBasicBlock::iterator I) const {
356 if (!hasReservedCallFrame(MF)) {
357 // If the stack pointer can be changed after prologue, turn the
358 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
359 // adjcallstackdown instruction into 'add ESP, <amt>'
360 // TODO: consider using push / pop instead of sub + store / add
361 MachineInstr *Old = I;
362 uint64_t Amount = Old->getOperand(0).getImm();
364 // We need to keep the stack aligned properly. To do this, we round the
365 // amount of space needed for the outgoing arguments up to the next
366 // alignment boundary.
367 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
369 MachineInstr *New = 0;
370 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
371 New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
372 StackPtr).addReg(StackPtr).addImm(Amount);
374 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
375 // factor out the amount the callee already popped.
376 uint64_t CalleeAmt = Old->getOperand(1).getImm();
379 unsigned Opc = (Amount < 128) ?
380 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
381 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
382 New = BuildMI(MF, TII.get(Opc), StackPtr)
383 .addReg(StackPtr).addImm(Amount);
387 // Replace the pseudo instruction with a new instruction...
388 if (New) MBB.insert(I, New);
390 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
391 // If we are performing frame pointer elimination and if the callee pops
392 // something off the stack pointer, add it back. We do this until we have
393 // more advanced stack pointer tracking ability.
394 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
395 unsigned Opc = (CalleeAmt < 128) ?
396 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
397 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
399 BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
407 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
408 int SPAdj, RegScavenger *RS) const{
409 assert(SPAdj == 0 && "Unexpected");
412 MachineInstr &MI = *II;
413 MachineFunction &MF = *MI.getParent()->getParent();
414 while (!MI.getOperand(i).isFrameIndex()) {
416 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
419 int FrameIndex = MI.getOperand(i).getIndex();
422 if (needsStackRealignment(MF))
423 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
425 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
427 // This must be part of a four operand memory reference. Replace the
428 // FrameIndex with base register with EBP. Add an offset to the offset.
429 MI.getOperand(i).ChangeToRegister(BasePtr, false);
431 // Now add the frame object offset to the offset from EBP. Offset is a
433 int Offset = getFrameIndexOffset(MF, FrameIndex) +
434 (int)(MI.getOperand(i+3).getImm());
436 MI.getOperand(i+3).ChangeToImmediate(Offset);
440 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
441 RegScavenger *RS) const {
442 MachineFrameInfo *FFI = MF.getFrameInfo();
444 // Calculate and set max stack object alignment early, so we can decide
445 // whether we will need stack realignment (and thus FP).
446 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
447 calculateMaxStackAlignment(FFI));
449 FFI->setMaxAlignment(MaxAlign);
453 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
454 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
455 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
456 if (TailCallReturnAddrDelta < 0) {
457 // create RETURNADDR area
467 CreateFixedObject(-TailCallReturnAddrDelta,
468 (-1*SlotSize)+TailCallReturnAddrDelta);
471 assert((TailCallReturnAddrDelta <= 0) &&
472 "The Delta should always be zero or negative");
473 // Create a frame entry for the EBP register that must be saved.
474 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
476 TailCallReturnAddrDelta);
477 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
478 "Slot for EBP register must be last in order to be found!");
482 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
483 /// stack pointer by a constant value.
485 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
486 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
487 const TargetInstrInfo &TII) {
488 bool isSub = NumBytes < 0;
489 uint64_t Offset = isSub ? -NumBytes : NumBytes;
492 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
493 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
495 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
496 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
497 uint64_t Chunk = (1LL << 31) - 1;
500 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
501 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
506 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
508 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
509 unsigned StackPtr, uint64_t *NumBytes = NULL) {
510 if (MBBI == MBB.begin()) return;
512 MachineBasicBlock::iterator PI = prior(MBBI);
513 unsigned Opc = PI->getOpcode();
514 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
515 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
516 PI->getOperand(0).getReg() == StackPtr) {
518 *NumBytes += PI->getOperand(2).getImm();
520 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
521 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
522 PI->getOperand(0).getReg() == StackPtr) {
524 *NumBytes -= PI->getOperand(2).getImm();
529 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
531 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
532 MachineBasicBlock::iterator &MBBI,
533 unsigned StackPtr, uint64_t *NumBytes = NULL) {
536 if (MBBI == MBB.end()) return;
538 MachineBasicBlock::iterator NI = next(MBBI);
539 if (NI == MBB.end()) return;
541 unsigned Opc = NI->getOpcode();
542 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
543 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
544 NI->getOperand(0).getReg() == StackPtr) {
546 *NumBytes -= NI->getOperand(2).getImm();
549 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
550 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
551 NI->getOperand(0).getReg() == StackPtr) {
553 *NumBytes += NI->getOperand(2).getImm();
559 /// mergeSPUpdates - Checks the instruction before/after the passed
560 /// instruction. If it is an ADD/SUB instruction it is deleted
561 /// argument and the stack adjustment is returned as a positive value for ADD
562 /// and a negative for SUB.
563 static int mergeSPUpdates(MachineBasicBlock &MBB,
564 MachineBasicBlock::iterator &MBBI,
566 bool doMergeWithPrevious) {
568 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
569 (!doMergeWithPrevious && MBBI == MBB.end()))
574 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
575 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
576 unsigned Opc = PI->getOpcode();
577 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
578 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
579 PI->getOperand(0).getReg() == StackPtr){
580 Offset += PI->getOperand(2).getImm();
582 if (!doMergeWithPrevious) MBBI = NI;
583 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
584 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
585 PI->getOperand(0).getReg() == StackPtr) {
586 Offset -= PI->getOperand(2).getImm();
588 if (!doMergeWithPrevious) MBBI = NI;
594 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
595 unsigned FrameLabelId,
596 unsigned ReadyLabelId) const {
597 MachineFrameInfo *MFI = MF.getFrameInfo();
598 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
602 uint64_t StackSize = MFI->getStackSize();
603 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
604 const TargetData *TD = MF.getTarget().getTargetData();
606 // Calculate amount of bytes used for return address storing
608 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
609 TargetFrameInfo::StackGrowsUp ?
610 TD->getPointerSize() : -TD->getPointerSize());
613 // Show update of SP.
616 MachineLocation SPDst(MachineLocation::VirtualFP);
617 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
618 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
620 MachineLocation SPDst(MachineLocation::VirtualFP);
621 MachineLocation SPSrc(MachineLocation::VirtualFP,
622 -StackSize+stackGrowth);
623 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
626 //FIXME: Verify & implement for FP
627 MachineLocation SPDst(StackPtr);
628 MachineLocation SPSrc(StackPtr, stackGrowth);
629 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
632 // Add callee saved registers to move list.
633 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
635 // FIXME: This is dirty hack. The code itself is pretty mess right now.
636 // It should be rewritten from scratch and generalized sometimes.
638 // Determine maximum offset (minumum due to stack growth)
639 int64_t MaxOffset = 0;
640 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
641 MaxOffset = std::min(MaxOffset,
642 MFI->getObjectOffset(CSI[I].getFrameIdx()));
645 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
646 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
647 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
648 unsigned Reg = CSI[I].getReg();
649 Offset = (MaxOffset-Offset+saveAreaOffset);
650 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
651 MachineLocation CSSrc(Reg);
652 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
657 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
658 MachineLocation FPSrc(FramePtr);
659 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
662 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
663 MachineLocation FPSrc(MachineLocation::VirtualFP);
664 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
668 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
669 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
670 MachineFrameInfo *MFI = MF.getFrameInfo();
671 const Function* Fn = MF.getFunction();
672 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
673 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
674 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
675 MachineBasicBlock::iterator MBBI = MBB.begin();
676 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
677 !Fn->doesNotThrow() ||
678 UnwindTablesMandatory;
679 // Prepare for frame info.
680 unsigned FrameLabelId = 0;
682 // Get the number of bytes to allocate from the FrameInfo.
683 uint64_t StackSize = MFI->getStackSize();
684 // Get desired stack alignment
685 uint64_t MaxAlign = MFI->getMaxAlignment();
687 // Add RETADDR move area to callee saved frame size.
688 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
689 if (TailCallReturnAddrDelta < 0)
690 X86FI->setCalleeSavedFrameSize(
691 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
693 // Insert stack pointer adjustment for later moving of return addr. Only
694 // applies to tail call optimized functions where the callee argument stack
695 // size is bigger than the callers.
696 if (TailCallReturnAddrDelta < 0) {
697 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
698 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
701 uint64_t NumBytes = 0;
703 // Calculate required stack adjustment
704 uint64_t FrameSize = StackSize - SlotSize;
705 if (needsStackRealignment(MF))
706 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
708 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
710 // Get the offset of the stack slot for the EBP register... which is
711 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
712 // Update the frame offset adjustment.
713 MFI->setOffsetAdjustment(-NumBytes);
715 // Save EBP into the appropriate stack slot...
716 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
719 if (needsFrameMoves) {
720 // Mark effective beginning of when frame pointer becomes valid.
721 FrameLabelId = MMI->NextLabelID();
722 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
725 // Update EBP with the new base value...
726 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
730 if (needsStackRealignment(MF))
732 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
733 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
735 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
737 unsigned ReadyLabelId = 0;
738 if (needsFrameMoves) {
739 // Mark effective beginning of when frame pointer is ready.
740 ReadyLabelId = MMI->NextLabelID();
741 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
744 // Skip the callee-saved push instructions.
745 while (MBBI != MBB.end() &&
746 (MBBI->getOpcode() == X86::PUSH32r ||
747 MBBI->getOpcode() == X86::PUSH64r))
750 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
751 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
752 // Check, whether EAX is livein for this function
753 bool isEAXAlive = false;
754 for (MachineRegisterInfo::livein_iterator
755 II = MF.getRegInfo().livein_begin(),
756 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
757 unsigned Reg = II->first;
758 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
759 Reg == X86::AH || Reg == X86::AL);
762 // Function prologue calls _alloca to probe the stack when allocating
763 // more than 4k bytes in one go. Touching the stack at 4K increments is
764 // necessary to ensure that the guard pages used by the OS virtual memory
765 // manager are allocated in correct sequence.
767 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
768 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
769 .addExternalSymbol("_alloca");
772 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
773 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
774 // allocated bytes for EAX.
775 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
776 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
777 .addExternalSymbol("_alloca");
779 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
780 StackPtr, false, NumBytes-4);
781 MBB.insert(MBBI, MI);
784 // If there is an SUB32ri of ESP immediately before this instruction,
785 // merge the two. This can be the case when tail call elimination is
786 // enabled and the callee has more arguments then the caller.
787 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
788 // If there is an ADD32ri or SUB32ri of ESP immediately after this
789 // instruction, merge the two instructions.
790 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
793 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
798 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
801 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
802 MachineBasicBlock &MBB) const {
803 const MachineFrameInfo *MFI = MF.getFrameInfo();
804 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
805 MachineBasicBlock::iterator MBBI = prior(MBB.end());
806 unsigned RetOpcode = MBBI->getOpcode();
811 case X86::TCRETURNdi:
812 case X86::TCRETURNri:
813 case X86::TCRETURNri64:
814 case X86::TCRETURNdi64:
816 case X86::EH_RETURN64:
819 case X86::TAILJMPm: break; // These are ok
821 assert(0 && "Can only insert epilog into returning blocks");
824 // Get the number of bytes to allocate from the FrameInfo
825 uint64_t StackSize = MFI->getStackSize();
826 uint64_t MaxAlign = MFI->getMaxAlignment();
827 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
828 uint64_t NumBytes = 0;
831 // Calculate required stack adjustment
832 uint64_t FrameSize = StackSize - SlotSize;
833 if (needsStackRealignment(MF))
834 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
836 NumBytes = FrameSize - CSSize;
839 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
841 NumBytes = StackSize - CSSize;
843 // Skip the callee-saved pop instructions.
844 MachineBasicBlock::iterator LastCSPop = MBBI;
845 while (MBBI != MBB.begin()) {
846 MachineBasicBlock::iterator PI = prior(MBBI);
847 unsigned Opc = PI->getOpcode();
848 if (Opc != X86::POP32r && Opc != X86::POP64r &&
849 !PI->getDesc().isTerminator())
854 // If there is an ADD32ri or SUB32ri of ESP immediately before this
855 // instruction, merge the two instructions.
856 if (NumBytes || MFI->hasVarSizedObjects())
857 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
859 // If dynamic alloca is used, then reset esp to point to the last callee-saved
860 // slot before popping them off! Same applies for the case, when stack was
862 if (needsStackRealignment(MF)) {
863 // We cannot use LEA here, because stack pointer was realigned. We need to
864 // deallocate local frame back
866 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
867 MBBI = prior(LastCSPop);
871 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
872 StackPtr).addReg(FramePtr);
873 } else if (MFI->hasVarSizedObjects()) {
875 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
876 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
877 FramePtr, false, -CSSize);
878 MBB.insert(MBBI, MI);
880 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
881 StackPtr).addReg(FramePtr);
884 // adjust stack pointer back: ESP += numbytes
886 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
889 // We're returning from function via eh_return.
890 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
891 MBBI = prior(MBB.end());
892 MachineOperand &DestAddr = MBBI->getOperand(0);
893 assert(DestAddr.isRegister() && "Offset should be in register!");
895 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
896 StackPtr).addReg(DestAddr.getReg());
897 // Tail call return: adjust the stack pointer and jump to callee
898 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
899 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
900 MBBI = prior(MBB.end());
901 MachineOperand &JumpTarget = MBBI->getOperand(0);
902 MachineOperand &StackAdjust = MBBI->getOperand(1);
903 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
905 // Adjust stack pointer.
906 int StackAdj = StackAdjust.getImm();
907 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
909 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
910 // Incoporate the retaddr area.
911 Offset = StackAdj-MaxTCDelta;
912 assert(Offset >= 0 && "Offset should never be negative");
914 // Check for possible merge with preceeding ADD instruction.
915 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
916 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
918 // Jump to label or value in register.
919 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
920 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
921 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
922 else if (RetOpcode== X86::TCRETURNri64) {
923 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
925 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
926 // Delete the pseudo instruction TCRETURN.
928 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
929 (X86FI->getTCReturnAddrDelta() < 0)) {
930 // Add the return addr area delta back since we are not tail calling.
931 int delta = -1*X86FI->getTCReturnAddrDelta();
932 MBBI = prior(MBB.end());
933 // Check for possible merge with preceeding ADD instruction.
934 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
935 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
939 unsigned X86RegisterInfo::getRARegister() const {
941 return X86::RIP; // Should have dwarf #16
943 return X86::EIP; // Should have dwarf #8
946 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
947 return hasFP(MF) ? FramePtr : StackPtr;
950 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
952 // Calculate amount of bytes used for return address storing
953 int stackGrowth = (Is64Bit ? -8 : -4);
955 // Initial state of the frame pointer is esp+4.
956 MachineLocation Dst(MachineLocation::VirtualFP);
957 MachineLocation Src(StackPtr, stackGrowth);
958 Moves.push_back(MachineMove(0, Dst, Src));
960 // Add return address to move list
961 MachineLocation CSDst(StackPtr, stackGrowth);
962 MachineLocation CSSrc(getRARegister());
963 Moves.push_back(MachineMove(0, CSDst, CSSrc));
966 unsigned X86RegisterInfo::getEHExceptionRegister() const {
967 assert(0 && "What is the exception register");
971 unsigned X86RegisterInfo::getEHHandlerRegister() const {
972 assert(0 && "What is the exception handler register");
977 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
978 switch (VT.getSimpleVT()) {
984 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
986 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
988 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
990 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
996 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
998 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1000 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1002 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1004 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1006 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1008 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1010 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1012 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1014 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1016 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1018 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1020 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1022 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1024 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1026 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1032 default: return Reg;
1033 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1035 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1037 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1039 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1041 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1043 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1045 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1047 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1049 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1051 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1053 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1055 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1057 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1059 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1061 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1063 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1068 default: return Reg;
1069 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1071 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1073 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1075 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1077 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1079 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1081 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1083 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1085 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1087 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1089 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1091 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1093 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1095 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1097 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1099 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1104 default: return Reg;
1105 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1107 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1109 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1111 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1113 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1115 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1117 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1119 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1121 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1123 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1125 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1127 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1129 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1131 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1133 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1135 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1144 #include "X86GenRegisterInfo.inc"
1147 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1149 MSAC() : MachineFunctionPass(&ID) {}
1151 virtual bool runOnMachineFunction(MachineFunction &MF) {
1152 MachineFrameInfo *FFI = MF.getFrameInfo();
1153 MachineRegisterInfo &RI = MF.getRegInfo();
1155 // Calculate max stack alignment of all already allocated stack objects.
1156 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1158 // Be over-conservative: scan over all vreg defs and find, whether vector
1159 // registers are used. If yes - there is probability, that vector register
1160 // will be spilled and thus stack needs to be aligned properly.
1161 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1162 RegNum < RI.getLastVirtReg(); ++RegNum)
1163 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1165 FFI->setMaxAlignment(MaxAlign);
1170 virtual const char *getPassName() const {
1171 return "X86 Maximal Stack Alignment Calculator";
1179 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }