1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/ErrorHandling.h"
45 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
46 const TargetInstrInfo &tii)
47 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
48 X86::ADJCALLSTACKDOWN64 :
49 X86::ADJCALLSTACKDOWN32,
50 tm.getSubtarget<X86Subtarget>().is64Bit() ?
51 X86::ADJCALLSTACKUP64 :
52 X86::ADJCALLSTACKUP32),
54 // Cache some information.
55 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
56 Is64Bit = Subtarget->is64Bit();
57 IsWin64 = Subtarget->isTargetWin64();
58 StackAlign = TM.getFrameInfo()->getStackAlignment();
70 // getDwarfRegNum - This function maps LLVM register identifiers to the
71 // Dwarf specific numbering, used in debug info and exception tables.
73 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
74 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
75 unsigned Flavour = DWARFFlavour::X86_64;
76 if (!Subtarget->is64Bit()) {
77 if (Subtarget->isTargetDarwin()) {
79 Flavour = DWARFFlavour::X86_32_DarwinEH;
81 Flavour = DWARFFlavour::X86_32_Generic;
82 } else if (Subtarget->isTargetCygMing()) {
83 // Unsupported by now, just quick fallback
84 Flavour = DWARFFlavour::X86_32_Generic;
86 Flavour = DWARFFlavour::X86_32_Generic;
90 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
93 // getX86RegNum - This function maps LLVM register identifiers to their X86
94 // specific numbering, which is used in various places encoding instructions.
96 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
98 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
99 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
100 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
101 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
102 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
104 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
106 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
108 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
111 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
113 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
115 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
117 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
119 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
121 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
123 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
125 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
128 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
129 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
130 return RegNo-X86::ST0;
132 case X86::XMM0: case X86::XMM8: case X86::MM0:
134 case X86::XMM1: case X86::XMM9: case X86::MM1:
136 case X86::XMM2: case X86::XMM10: case X86::MM2:
138 case X86::XMM3: case X86::XMM11: case X86::MM3:
140 case X86::XMM4: case X86::XMM12: case X86::MM4:
142 case X86::XMM5: case X86::XMM13: case X86::MM5:
144 case X86::XMM6: case X86::XMM14: case X86::MM6:
146 case X86::XMM7: case X86::XMM15: case X86::MM7:
150 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
151 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
156 const TargetRegisterClass *
157 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
158 const TargetRegisterClass *B,
159 unsigned SubIdx) const {
164 if (B == &X86::GR8RegClass) {
165 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
167 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
168 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
169 A == &X86::GR64_NOREXRegClass ||
170 A == &X86::GR64_NOSPRegClass ||
171 A == &X86::GR64_NOREX_NOSPRegClass)
172 return &X86::GR64_ABCDRegClass;
173 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
174 A == &X86::GR32_NOREXRegClass ||
175 A == &X86::GR32_NOSPRegClass)
176 return &X86::GR32_ABCDRegClass;
177 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
178 A == &X86::GR16_NOREXRegClass)
179 return &X86::GR16_ABCDRegClass;
180 } else if (B == &X86::GR8_NOREXRegClass) {
181 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
182 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
183 return &X86::GR64_NOREXRegClass;
184 else if (A == &X86::GR64_ABCDRegClass)
185 return &X86::GR64_ABCDRegClass;
186 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
187 A == &X86::GR32_NOSPRegClass)
188 return &X86::GR32_NOREXRegClass;
189 else if (A == &X86::GR32_ABCDRegClass)
190 return &X86::GR32_ABCDRegClass;
191 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
192 return &X86::GR16_NOREXRegClass;
193 else if (A == &X86::GR16_ABCDRegClass)
194 return &X86::GR16_ABCDRegClass;
199 if (B == &X86::GR8_ABCD_HRegClass) {
200 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
201 A == &X86::GR64_NOREXRegClass ||
202 A == &X86::GR64_NOSPRegClass ||
203 A == &X86::GR64_NOREX_NOSPRegClass)
204 return &X86::GR64_ABCDRegClass;
205 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
206 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
207 return &X86::GR32_ABCDRegClass;
208 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
209 A == &X86::GR16_NOREXRegClass)
210 return &X86::GR16_ABCDRegClass;
215 if (B == &X86::GR16RegClass) {
216 if (A->getSize() == 4 || A->getSize() == 8)
218 } else if (B == &X86::GR16_ABCDRegClass) {
219 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
220 A == &X86::GR64_NOREXRegClass ||
221 A == &X86::GR64_NOSPRegClass ||
222 A == &X86::GR64_NOREX_NOSPRegClass)
223 return &X86::GR64_ABCDRegClass;
224 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
225 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
226 return &X86::GR32_ABCDRegClass;
227 } else if (B == &X86::GR16_NOREXRegClass) {
228 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
229 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
230 return &X86::GR64_NOREXRegClass;
231 else if (A == &X86::GR64_ABCDRegClass)
232 return &X86::GR64_ABCDRegClass;
233 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
234 A == &X86::GR32_NOSPRegClass)
235 return &X86::GR32_NOREXRegClass;
236 else if (A == &X86::GR32_ABCDRegClass)
237 return &X86::GR64_ABCDRegClass;
242 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
243 if (A->getSize() == 8)
245 } else if (B == &X86::GR32_ABCDRegClass) {
246 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
247 A == &X86::GR64_NOREXRegClass ||
248 A == &X86::GR64_NOSPRegClass ||
249 A == &X86::GR64_NOREX_NOSPRegClass)
250 return &X86::GR64_ABCDRegClass;
251 } else if (B == &X86::GR32_NOREXRegClass) {
252 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
253 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
254 return &X86::GR64_NOREXRegClass;
255 else if (A == &X86::GR64_ABCDRegClass)
256 return &X86::GR64_ABCDRegClass;
263 const TargetRegisterClass *X86RegisterInfo::
264 getPointerRegClass(unsigned Kind) const {
266 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
267 case 0: // Normal GPRs.
268 if (TM.getSubtarget<X86Subtarget>().is64Bit())
269 return &X86::GR64RegClass;
270 return &X86::GR32RegClass;
271 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
272 if (TM.getSubtarget<X86Subtarget>().is64Bit())
273 return &X86::GR64_NOSPRegClass;
274 return &X86::GR32_NOSPRegClass;
278 const TargetRegisterClass *
279 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
280 if (RC == &X86::CCRRegClass) {
282 return &X86::GR64RegClass;
284 return &X86::GR32RegClass;
290 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
291 bool callsEHReturn = false;
294 const MachineFrameInfo *MFI = MF->getFrameInfo();
295 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
296 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
299 static const unsigned CalleeSavedRegs32Bit[] = {
300 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
303 static const unsigned CalleeSavedRegs32EHRet[] = {
304 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
307 static const unsigned CalleeSavedRegs64Bit[] = {
308 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
311 static const unsigned CalleeSavedRegs64EHRet[] = {
312 X86::RAX, X86::RDX, X86::RBX, X86::R12,
313 X86::R13, X86::R14, X86::R15, X86::RBP, 0
316 static const unsigned CalleeSavedRegsWin64[] = {
317 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
318 X86::R12, X86::R13, X86::R14, X86::R15,
319 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
320 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
321 X86::XMM14, X86::XMM15, 0
326 return CalleeSavedRegsWin64;
328 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
330 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
334 const TargetRegisterClass* const*
335 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
336 bool callsEHReturn = false;
339 const MachineFrameInfo *MFI = MF->getFrameInfo();
340 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
341 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
344 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
345 &X86::GR32RegClass, &X86::GR32RegClass,
346 &X86::GR32RegClass, &X86::GR32RegClass, 0
348 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
349 &X86::GR32RegClass, &X86::GR32RegClass,
350 &X86::GR32RegClass, &X86::GR32RegClass,
351 &X86::GR32RegClass, &X86::GR32RegClass, 0
353 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
354 &X86::GR64RegClass, &X86::GR64RegClass,
355 &X86::GR64RegClass, &X86::GR64RegClass,
356 &X86::GR64RegClass, &X86::GR64RegClass, 0
358 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
359 &X86::GR64RegClass, &X86::GR64RegClass,
360 &X86::GR64RegClass, &X86::GR64RegClass,
361 &X86::GR64RegClass, &X86::GR64RegClass,
362 &X86::GR64RegClass, &X86::GR64RegClass, 0
364 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
365 &X86::GR64RegClass, &X86::GR64RegClass,
366 &X86::GR64RegClass, &X86::GR64RegClass,
367 &X86::GR64RegClass, &X86::GR64RegClass,
368 &X86::GR64RegClass, &X86::GR64RegClass,
369 &X86::VR128RegClass, &X86::VR128RegClass,
370 &X86::VR128RegClass, &X86::VR128RegClass,
371 &X86::VR128RegClass, &X86::VR128RegClass,
372 &X86::VR128RegClass, &X86::VR128RegClass,
373 &X86::VR128RegClass, &X86::VR128RegClass, 0
378 return CalleeSavedRegClassesWin64;
380 return (callsEHReturn ?
381 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
383 return (callsEHReturn ?
384 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
388 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
389 BitVector Reserved(getNumRegs());
390 // Set the stack-pointer register and its aliases as reserved.
391 Reserved.set(X86::RSP);
392 Reserved.set(X86::ESP);
393 Reserved.set(X86::SP);
394 Reserved.set(X86::SPL);
395 // Set the frame-pointer register and its aliases as reserved if needed.
397 Reserved.set(X86::RBP);
398 Reserved.set(X86::EBP);
399 Reserved.set(X86::BP);
400 Reserved.set(X86::BPL);
402 // Mark the x87 stack registers as reserved, since they don't
403 // behave normally with respect to liveness. We don't fully
404 // model the effects of x87 stack pushes and pops after
406 Reserved.set(X86::ST0);
407 Reserved.set(X86::ST1);
408 Reserved.set(X86::ST2);
409 Reserved.set(X86::ST3);
410 Reserved.set(X86::ST4);
411 Reserved.set(X86::ST5);
412 Reserved.set(X86::ST6);
413 Reserved.set(X86::ST7);
417 //===----------------------------------------------------------------------===//
418 // Stack Frame Processing methods
419 //===----------------------------------------------------------------------===//
421 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
422 unsigned MaxAlign = 0;
423 for (int i = FFI->getObjectIndexBegin(),
424 e = FFI->getObjectIndexEnd(); i != e; ++i) {
425 if (FFI->isDeadObjectIndex(i))
427 unsigned Align = FFI->getObjectAlignment(i);
428 MaxAlign = std::max(MaxAlign, Align);
434 // hasFP - Return true if the specified function should have a dedicated frame
435 // pointer register. This is true if the function has variable sized allocas or
436 // if frame pointer elimination is disabled.
438 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
439 const MachineFrameInfo *MFI = MF.getFrameInfo();
440 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
442 return (NoFramePointerElim ||
443 needsStackRealignment(MF) ||
444 MFI->hasVarSizedObjects() ||
445 MFI->isFrameAddressTaken() ||
446 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
447 (MMI && MMI->callsUnwindInit()));
450 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
451 const MachineFrameInfo *MFI = MF.getFrameInfo();
453 // FIXME: Currently we don't support stack realignment for functions with
454 // variable-sized allocas
455 return (RealignStack &&
456 (MFI->getMaxAlignment() > StackAlign &&
457 !MFI->hasVarSizedObjects()));
460 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
461 return !MF.getFrameInfo()->hasVarSizedObjects();
464 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
465 int &FrameIdx) const {
466 if (Reg == FramePtr && hasFP(MF)) {
467 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
475 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
476 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
477 MachineFrameInfo *MFI = MF.getFrameInfo();
479 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
480 uint64_t StackSize = MFI->getStackSize();
482 if (needsStackRealignment(MF)) {
484 // Skip the saved EBP
487 unsigned Align = MFI->getObjectAlignment(FI);
488 assert( (-(Offset + StackSize)) % Align == 0);
490 return Offset + StackSize;
493 // FIXME: Support tail calls
496 return Offset + StackSize;
498 // Skip the saved EBP
501 // Skip the RETADDR move area
502 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
503 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
504 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
510 void X86RegisterInfo::
511 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
512 MachineBasicBlock::iterator I) const {
513 if (!hasReservedCallFrame(MF)) {
514 // If the stack pointer can be changed after prologue, turn the
515 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
516 // adjcallstackdown instruction into 'add ESP, <amt>'
517 // TODO: consider using push / pop instead of sub + store / add
518 MachineInstr *Old = I;
519 uint64_t Amount = Old->getOperand(0).getImm();
521 // We need to keep the stack aligned properly. To do this, we round the
522 // amount of space needed for the outgoing arguments up to the next
523 // alignment boundary.
524 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
526 MachineInstr *New = 0;
527 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
528 New = BuildMI(MF, Old->getDebugLoc(),
529 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
530 StackPtr).addReg(StackPtr).addImm(Amount);
532 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
533 // factor out the amount the callee already popped.
534 uint64_t CalleeAmt = Old->getOperand(1).getImm();
537 unsigned Opc = (Amount < 128) ?
538 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
539 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
540 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
541 .addReg(StackPtr).addImm(Amount);
546 // The EFLAGS implicit def is dead.
547 New->getOperand(3).setIsDead();
549 // Replace the pseudo instruction with a new instruction...
553 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
554 // If we are performing frame pointer elimination and if the callee pops
555 // something off the stack pointer, add it back. We do this until we have
556 // more advanced stack pointer tracking ability.
557 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
558 unsigned Opc = (CalleeAmt < 128) ?
559 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
560 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
561 MachineInstr *Old = I;
563 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
564 StackPtr).addReg(StackPtr).addImm(CalleeAmt);
565 // The EFLAGS implicit def is dead.
566 New->getOperand(3).setIsDead();
575 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
576 int SPAdj, RegScavenger *RS) const{
577 assert(SPAdj == 0 && "Unexpected");
580 MachineInstr &MI = *II;
581 MachineFunction &MF = *MI.getParent()->getParent();
582 while (!MI.getOperand(i).isFI()) {
584 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
587 int FrameIndex = MI.getOperand(i).getIndex();
590 if (needsStackRealignment(MF))
591 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
593 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
595 // This must be part of a four operand memory reference. Replace the
596 // FrameIndex with base register with EBP. Add an offset to the offset.
597 MI.getOperand(i).ChangeToRegister(BasePtr, false);
599 // Now add the frame object offset to the offset from EBP.
600 if (MI.getOperand(i+3).isImm()) {
601 // Offset is a 32-bit integer.
602 int Offset = getFrameIndexOffset(MF, FrameIndex) +
603 (int)(MI.getOperand(i+3).getImm());
605 MI.getOperand(i+3).ChangeToImmediate(Offset);
607 // Offset is symbolic. This is extremely rare.
608 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
609 (uint64_t)MI.getOperand(i+3).getOffset();
610 MI.getOperand(i+3).setOffset(Offset);
615 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
616 RegScavenger *RS) const {
617 MachineFrameInfo *MFI = MF.getFrameInfo();
619 // Calculate and set max stack object alignment early, so we can decide
620 // whether we will need stack realignment (and thus FP).
621 unsigned MaxAlign = std::max(MFI->getMaxAlignment(),
622 calculateMaxStackAlignment(MFI));
624 MFI->setMaxAlignment(MaxAlign);
626 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
627 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
628 if (TailCallReturnAddrDelta < 0) {
629 // create RETURNADDR area
638 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
639 (-1*SlotSize)+TailCallReturnAddrDelta);
643 assert((TailCallReturnAddrDelta <= 0) &&
644 "The Delta should always be zero or negative");
645 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
646 // Create a frame entry for the EBP register that must be saved.
647 int FrameIdx = MFI->CreateFixedObject(SlotSize,
649 TFI.getOffsetOfLocalArea() +
650 TailCallReturnAddrDelta);
651 assert(FrameIdx == MFI->getObjectIndexBegin() &&
652 "Slot for EBP register must be last in order to be found!");
657 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
658 /// stack pointer by a constant value.
660 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
661 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
662 const TargetInstrInfo &TII) {
663 bool isSub = NumBytes < 0;
664 uint64_t Offset = isSub ? -NumBytes : NumBytes;
667 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
668 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
670 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
671 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
672 uint64_t Chunk = (1LL << 31) - 1;
673 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
674 DebugLoc::getUnknownLoc());
677 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
679 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
682 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
687 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
689 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
690 unsigned StackPtr, uint64_t *NumBytes = NULL) {
691 if (MBBI == MBB.begin()) return;
693 MachineBasicBlock::iterator PI = prior(MBBI);
694 unsigned Opc = PI->getOpcode();
695 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
696 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
697 PI->getOperand(0).getReg() == StackPtr) {
699 *NumBytes += PI->getOperand(2).getImm();
701 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
702 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
703 PI->getOperand(0).getReg() == StackPtr) {
705 *NumBytes -= PI->getOperand(2).getImm();
710 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
712 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
713 MachineBasicBlock::iterator &MBBI,
714 unsigned StackPtr, uint64_t *NumBytes = NULL) {
715 // FIXME: THIS ISN'T RUN!!!
718 if (MBBI == MBB.end()) return;
720 MachineBasicBlock::iterator NI = next(MBBI);
721 if (NI == MBB.end()) return;
723 unsigned Opc = NI->getOpcode();
724 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
725 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
726 NI->getOperand(0).getReg() == StackPtr) {
728 *NumBytes -= NI->getOperand(2).getImm();
731 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
732 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
733 NI->getOperand(0).getReg() == StackPtr) {
735 *NumBytes += NI->getOperand(2).getImm();
741 /// mergeSPUpdates - Checks the instruction before/after the passed
742 /// instruction. If it is an ADD/SUB instruction it is deleted
743 /// argument and the stack adjustment is returned as a positive value for ADD
744 /// and a negative for SUB.
745 static int mergeSPUpdates(MachineBasicBlock &MBB,
746 MachineBasicBlock::iterator &MBBI,
748 bool doMergeWithPrevious) {
750 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
751 (!doMergeWithPrevious && MBBI == MBB.end()))
756 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
757 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
758 unsigned Opc = PI->getOpcode();
759 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
760 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
761 PI->getOperand(0).getReg() == StackPtr){
762 Offset += PI->getOperand(2).getImm();
764 if (!doMergeWithPrevious) MBBI = NI;
765 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
766 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
767 PI->getOperand(0).getReg() == StackPtr) {
768 Offset -= PI->getOperand(2).getImm();
770 if (!doMergeWithPrevious) MBBI = NI;
776 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
778 unsigned FramePtr) const {
779 MachineFrameInfo *MFI = MF.getFrameInfo();
780 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
783 // Add callee saved registers to move list.
784 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
785 if (CSI.empty()) return;
787 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
788 const TargetData *TD = MF.getTarget().getTargetData();
789 bool HasFP = hasFP(MF);
791 // Calculate amount of bytes used for return address storing
793 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
794 TargetFrameInfo::StackGrowsUp ?
795 TD->getPointerSize() : -TD->getPointerSize());
797 // FIXME: This is dirty hack. The code itself is pretty mess right now.
798 // It should be rewritten from scratch and generalized sometimes.
800 // Determine maximum offset (minumum due to stack growth)
801 int64_t MaxOffset = 0;
802 for (std::vector<CalleeSavedInfo>::const_iterator
803 I = CSI.begin(), E = CSI.end(); I != E; ++I)
804 MaxOffset = std::min(MaxOffset,
805 MFI->getObjectOffset(I->getFrameIdx()));
807 // Calculate offsets.
808 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
809 for (std::vector<CalleeSavedInfo>::const_iterator
810 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
811 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
812 unsigned Reg = I->getReg();
813 Offset = MaxOffset - Offset + saveAreaOffset;
815 // Don't output a new machine move if we're re-saving the frame
816 // pointer. This happens when the PrologEpilogInserter has inserted an extra
817 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
818 // generates one when frame pointers are used. If we generate a "machine
819 // move" for this extra "PUSH", the linker will lose track of the fact that
820 // the frame pointer should have the value of the first "PUSH" when it's
823 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
824 // another bug. I.e., one where we generate a prolog like this:
832 // The immediate re-push of EBP is unnecessary. At the least, it's an
833 // optimization bug. EBP can be used as a scratch register in certain
834 // cases, but probably not when we have a frame pointer.
835 if (HasFP && FramePtr == Reg)
838 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
839 MachineLocation CSSrc(Reg);
840 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
844 /// emitPrologue - Push callee-saved registers onto the stack, which
845 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
846 /// space for local variables. Also emit labels used by the exception handler to
847 /// generate the exception handling frames.
848 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
849 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
850 MachineBasicBlock::iterator MBBI = MBB.begin();
851 MachineFrameInfo *MFI = MF.getFrameInfo();
852 const Function *Fn = MF.getFunction();
853 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
854 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
855 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
856 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
857 !Fn->doesNotThrow() || UnwindTablesMandatory;
858 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
859 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
860 bool HasFP = hasFP(MF);
863 // Add RETADDR move area to callee saved frame size.
864 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
865 if (TailCallReturnAddrDelta < 0)
866 X86FI->setCalleeSavedFrameSize(
867 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
869 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
870 // function, and use up to 128 bytes of stack space, don't have a frame
871 // pointer, calls, or dynamic alloca then we do not need to adjust the
872 // stack pointer (we fit in the Red Zone).
873 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
874 !needsStackRealignment(MF) &&
875 !MFI->hasVarSizedObjects() && // No dynamic alloca.
876 !MFI->hasCalls() && // No calls.
877 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
878 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
879 if (HasFP) MinSize += SlotSize;
880 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
881 MFI->setStackSize(StackSize);
882 } else if (Subtarget->isTargetWin64()) {
883 // We need to always allocate 32 bytes as register spill area.
884 // FIXME: We might reuse these 32 bytes for leaf functions.
886 MFI->setStackSize(StackSize);
889 // Insert stack pointer adjustment for later moving of return addr. Only
890 // applies to tail call optimized functions where the callee argument stack
891 // size is bigger than the callers.
892 if (TailCallReturnAddrDelta < 0) {
894 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
897 .addImm(-TailCallReturnAddrDelta);
898 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
901 // Mapping for machine moves:
903 // DST: VirtualFP AND
904 // SRC: VirtualFP => DW_CFA_def_cfa_offset
905 // ELSE => DW_CFA_def_cfa
907 // SRC: VirtualFP AND
908 // DST: Register => DW_CFA_def_cfa_register
911 // OFFSET < 0 => DW_CFA_offset_extended_sf
912 // REG < 64 => DW_CFA_offset + Reg
913 // ELSE => DW_CFA_offset_extended
915 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
916 const TargetData *TD = MF.getTarget().getTargetData();
917 uint64_t NumBytes = 0;
919 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
920 TargetFrameInfo::StackGrowsUp ?
921 TD->getPointerSize() : -TD->getPointerSize());
924 // Calculate required stack adjustment.
925 uint64_t FrameSize = StackSize - SlotSize;
926 if (needsStackRealignment(MF))
927 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
929 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
931 // Get the offset of the stack slot for the EBP register, which is
932 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
933 // Update the frame offset adjustment.
934 MFI->setOffsetAdjustment(-NumBytes);
936 // Save EBP/RBP into the appropriate stack slot.
937 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
938 .addReg(FramePtr, RegState::Kill);
940 if (needsFrameMoves) {
941 // Mark the place where EBP/RBP was saved.
942 unsigned FrameLabelId = MMI->NextLabelID();
943 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
945 // Define the current CFA rule to use the provided offset.
947 MachineLocation SPDst(MachineLocation::VirtualFP);
948 MachineLocation SPSrc(MachineLocation::VirtualFP,
950 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
952 // FIXME: Verify & implement for FP
953 MachineLocation SPDst(StackPtr);
954 MachineLocation SPSrc(StackPtr, stackGrowth);
955 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
958 // Change the rule for the FramePtr to be an "offset" rule.
959 MachineLocation FPDst(MachineLocation::VirtualFP,
961 MachineLocation FPSrc(FramePtr);
962 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
965 // Update EBP with the new base value...
966 BuildMI(MBB, MBBI, DL,
967 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
970 if (needsFrameMoves) {
971 // Mark effective beginning of when frame pointer becomes valid.
972 unsigned FrameLabelId = MMI->NextLabelID();
973 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
975 // Define the current CFA to use the EBP/RBP register.
976 MachineLocation FPDst(FramePtr);
977 MachineLocation FPSrc(MachineLocation::VirtualFP);
978 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
981 // Mark the FramePtr as live-in in every block except the entry.
982 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
984 I->addLiveIn(FramePtr);
987 if (needsStackRealignment(MF)) {
989 BuildMI(MBB, MBBI, DL,
990 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
991 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
993 // The EFLAGS implicit def is dead.
994 MI->getOperand(3).setIsDead();
997 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1000 // Skip the callee-saved push instructions.
1001 bool PushedRegs = false;
1002 int StackOffset = 2 * stackGrowth;
1004 while (MBBI != MBB.end() &&
1005 (MBBI->getOpcode() == X86::PUSH32r ||
1006 MBBI->getOpcode() == X86::PUSH64r)) {
1010 if (!HasFP && needsFrameMoves) {
1011 // Mark callee-saved push instruction.
1012 unsigned LabelId = MMI->NextLabelID();
1013 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1015 // Define the current CFA rule to use the provided offset.
1016 unsigned Ptr = StackSize ?
1017 MachineLocation::VirtualFP : StackPtr;
1018 MachineLocation SPDst(Ptr);
1019 MachineLocation SPSrc(Ptr, StackOffset);
1020 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1021 StackOffset += stackGrowth;
1025 if (MBBI != MBB.end())
1026 DL = MBBI->getDebugLoc();
1028 // Adjust stack pointer: ESP -= numbytes.
1029 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1030 // Check, whether EAX is livein for this function.
1031 bool isEAXAlive = false;
1032 for (MachineRegisterInfo::livein_iterator
1033 II = MF.getRegInfo().livein_begin(),
1034 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1035 unsigned Reg = II->first;
1036 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1037 Reg == X86::AH || Reg == X86::AL);
1040 // Function prologue calls _alloca to probe the stack when allocating more
1041 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1042 // to ensure that the guard pages used by the OS virtual memory manager are
1043 // allocated in correct sequence.
1045 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1047 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1048 .addExternalSymbol("_alloca");
1051 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1052 .addReg(X86::EAX, RegState::Kill);
1054 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1055 // allocated bytes for EAX.
1056 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1057 .addImm(NumBytes - 4);
1058 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1059 .addExternalSymbol("_alloca");
1062 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1064 StackPtr, false, NumBytes - 4);
1065 MBB.insert(MBBI, MI);
1067 } else if (NumBytes) {
1068 // If there is an SUB32ri of ESP immediately before this instruction, merge
1069 // the two. This can be the case when tail call elimination is enabled and
1070 // the callee has more arguments then the caller.
1071 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1073 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1074 // instruction, merge the two instructions.
1075 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1078 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1081 if (NumBytes && needsFrameMoves) {
1082 // Mark end of stack pointer adjustment.
1083 unsigned LabelId = MMI->NextLabelID();
1084 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1087 // Define the current CFA rule to use the provided offset.
1089 MachineLocation SPDst(MachineLocation::VirtualFP);
1090 MachineLocation SPSrc(MachineLocation::VirtualFP,
1091 -StackSize + stackGrowth);
1092 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1094 // FIXME: Verify & implement for FP
1095 MachineLocation SPDst(StackPtr);
1096 MachineLocation SPSrc(StackPtr, stackGrowth);
1097 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1101 // Emit DWARF info specifying the offsets of the callee-saved registers.
1103 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1107 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1108 MachineBasicBlock &MBB) const {
1109 const MachineFrameInfo *MFI = MF.getFrameInfo();
1110 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1111 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1112 unsigned RetOpcode = MBBI->getOpcode();
1113 DebugLoc DL = MBBI->getDebugLoc();
1115 switch (RetOpcode) {
1118 case X86::TCRETURNdi:
1119 case X86::TCRETURNri:
1120 case X86::TCRETURNri64:
1121 case X86::TCRETURNdi64:
1122 case X86::EH_RETURN:
1123 case X86::EH_RETURN64:
1126 case X86::TAILJMPm: break; // These are ok
1128 llvm_unreachable("Can only insert epilog into returning blocks");
1131 // Get the number of bytes to allocate from the FrameInfo
1132 uint64_t StackSize = MFI->getStackSize();
1133 uint64_t MaxAlign = MFI->getMaxAlignment();
1134 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1135 uint64_t NumBytes = 0;
1138 // Calculate required stack adjustment
1139 uint64_t FrameSize = StackSize - SlotSize;
1140 if (needsStackRealignment(MF))
1141 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1143 NumBytes = FrameSize - CSSize;
1146 BuildMI(MBB, MBBI, DL,
1147 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1149 NumBytes = StackSize - CSSize;
1152 // Skip the callee-saved pop instructions.
1153 MachineBasicBlock::iterator LastCSPop = MBBI;
1154 while (MBBI != MBB.begin()) {
1155 MachineBasicBlock::iterator PI = prior(MBBI);
1156 unsigned Opc = PI->getOpcode();
1157 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1158 !PI->getDesc().isTerminator())
1163 DL = MBBI->getDebugLoc();
1165 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1166 // instruction, merge the two instructions.
1167 if (NumBytes || MFI->hasVarSizedObjects())
1168 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1170 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1171 // slot before popping them off! Same applies for the case, when stack was
1173 if (needsStackRealignment(MF)) {
1174 // We cannot use LEA here, because stack pointer was realigned. We need to
1175 // deallocate local frame back
1177 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1178 MBBI = prior(LastCSPop);
1181 BuildMI(MBB, MBBI, DL,
1182 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1183 StackPtr).addReg(FramePtr);
1184 } else if (MFI->hasVarSizedObjects()) {
1186 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1187 MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1188 FramePtr, false, -CSSize);
1189 MBB.insert(MBBI, MI);
1191 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1192 StackPtr).addReg(FramePtr);
1195 // adjust stack pointer back: ESP += numbytes
1197 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1200 // We're returning from function via eh_return.
1201 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1202 MBBI = prior(MBB.end());
1203 MachineOperand &DestAddr = MBBI->getOperand(0);
1204 assert(DestAddr.isReg() && "Offset should be in register!");
1205 BuildMI(MBB, MBBI, DL,
1206 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1207 StackPtr).addReg(DestAddr.getReg());
1208 // Tail call return: adjust the stack pointer and jump to callee
1209 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1210 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1211 MBBI = prior(MBB.end());
1212 MachineOperand &JumpTarget = MBBI->getOperand(0);
1213 MachineOperand &StackAdjust = MBBI->getOperand(1);
1214 assert(StackAdjust.isImm() && "Expecting immediate value.");
1216 // Adjust stack pointer.
1217 int StackAdj = StackAdjust.getImm();
1218 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1220 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1221 // Incoporate the retaddr area.
1222 Offset = StackAdj-MaxTCDelta;
1223 assert(Offset >= 0 && "Offset should never be negative");
1226 // Check for possible merge with preceeding ADD instruction.
1227 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1228 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1231 // Jump to label or value in register.
1232 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1233 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1234 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1235 else if (RetOpcode== X86::TCRETURNri64)
1236 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1238 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1240 // Delete the pseudo instruction TCRETURN.
1242 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1243 (X86FI->getTCReturnAddrDelta() < 0)) {
1244 // Add the return addr area delta back since we are not tail calling.
1245 int delta = -1*X86FI->getTCReturnAddrDelta();
1246 MBBI = prior(MBB.end());
1247 // Check for possible merge with preceeding ADD instruction.
1248 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1249 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1253 unsigned X86RegisterInfo::getRARegister() const {
1255 return X86::RIP; // Should have dwarf #16
1257 return X86::EIP; // Should have dwarf #8
1260 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1261 return hasFP(MF) ? FramePtr : StackPtr;
1264 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1266 // Calculate amount of bytes used for return address storing
1267 int stackGrowth = (Is64Bit ? -8 : -4);
1269 // Initial state of the frame pointer is esp+4.
1270 MachineLocation Dst(MachineLocation::VirtualFP);
1271 MachineLocation Src(StackPtr, stackGrowth);
1272 Moves.push_back(MachineMove(0, Dst, Src));
1274 // Add return address to move list
1275 MachineLocation CSDst(StackPtr, stackGrowth);
1276 MachineLocation CSSrc(getRARegister());
1277 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1280 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1281 llvm_unreachable("What is the exception register");
1285 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1286 llvm_unreachable("What is the exception handler register");
1291 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1292 switch (VT.getSimpleVT().SimpleTy) {
1293 default: return Reg;
1298 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1300 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1302 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1304 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1310 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1312 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1314 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1316 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1318 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1320 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1322 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1324 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1326 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1328 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1330 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1332 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1334 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1336 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1338 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1340 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1346 default: return Reg;
1347 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1349 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1351 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1353 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1355 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1357 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1359 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1361 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1363 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1365 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1367 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1369 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1371 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1373 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1375 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1377 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1382 default: return Reg;
1383 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1385 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1387 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1389 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1391 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1393 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1395 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1397 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1399 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1401 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1403 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1405 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1407 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1409 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1411 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1413 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1418 default: return Reg;
1419 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1421 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1423 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1425 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1427 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1429 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1431 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1433 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1435 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1437 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1439 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1441 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1443 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1445 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1447 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1449 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1458 #include "X86GenRegisterInfo.inc"
1461 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1463 MSAC() : MachineFunctionPass(&ID) {}
1465 virtual bool runOnMachineFunction(MachineFunction &MF) {
1466 MachineFrameInfo *FFI = MF.getFrameInfo();
1467 MachineRegisterInfo &RI = MF.getRegInfo();
1469 // Calculate max stack alignment of all already allocated stack objects.
1470 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1472 // Be over-conservative: scan over all vreg defs and find, whether vector
1473 // registers are used. If yes - there is probability, that vector register
1474 // will be spilled and thus stack needs to be aligned properly.
1475 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1476 RegNum < RI.getLastVirtReg(); ++RegNum)
1477 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1479 if (FFI->getMaxAlignment() == MaxAlign)
1482 FFI->setMaxAlignment(MaxAlign);
1486 virtual const char *getPassName() const {
1487 return "X86 Maximal Stack Alignment Calculator";
1490 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1491 AU.setPreservesCFG();
1492 MachineFunctionPass::getAnalysisUsage(AU);
1500 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }