1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Target/TargetAsmInfo.h"
32 #include "llvm/Target/TargetFrameInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
40 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
41 const TargetInstrInfo &tii)
42 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
44 // Cache some information.
45 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
46 Is64Bit = Subtarget->is64Bit();
47 StackAlign = TM.getFrameInfo()->getStackAlignment();
59 // getDwarfRegNum - This function maps LLVM register identifiers to the
60 // Dwarf specific numbering, used in debug info and exception tables.
62 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
63 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
64 unsigned Flavour = DWARFFlavour::X86_64;
65 if (!Subtarget->is64Bit()) {
66 if (Subtarget->isTargetDarwin()) {
67 Flavour = DWARFFlavour::X86_32_Darwin;
68 } else if (Subtarget->isTargetCygMing()) {
69 // Unsupported by now, just quick fallback
70 Flavour = DWARFFlavour::X86_32_ELF;
72 Flavour = DWARFFlavour::X86_32_ELF;
76 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
79 // getX86RegNum - This function maps LLVM register identifiers to their X86
80 // specific numbering, which is used in various places encoding instructions.
82 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
84 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
85 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
86 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
87 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
88 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
90 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
92 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
94 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
97 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
99 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
101 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
103 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
105 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
107 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
109 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
111 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
114 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
115 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
116 return RegNo-X86::ST0;
118 case X86::XMM0: case X86::XMM8: case X86::MM0:
120 case X86::XMM1: case X86::XMM9: case X86::MM1:
122 case X86::XMM2: case X86::XMM10: case X86::MM2:
124 case X86::XMM3: case X86::XMM11: case X86::MM3:
126 case X86::XMM4: case X86::XMM12: case X86::MM4:
128 case X86::XMM5: case X86::XMM13: case X86::MM5:
130 case X86::XMM6: case X86::XMM14: case X86::MM6:
132 case X86::XMM7: case X86::XMM15: case X86::MM7:
136 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
137 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
142 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
143 MachineOperand &MO) {
145 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
146 false, false, MO.getSubReg());
147 else if (MO.isImmediate())
148 MIB = MIB.addImm(MO.getImm());
149 else if (MO.isFrameIndex())
150 MIB = MIB.addFrameIndex(MO.getIndex());
151 else if (MO.isGlobalAddress())
152 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
153 else if (MO.isConstantPoolIndex())
154 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
155 else if (MO.isJumpTableIndex())
156 MIB = MIB.addJumpTableIndex(MO.getIndex());
157 else if (MO.isExternalSymbol())
158 MIB = MIB.addExternalSymbol(MO.getSymbolName());
160 assert(0 && "Unknown operand for X86InstrAddOperand!");
165 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
166 unsigned StackAlign) {
168 if (RC == &X86::GR64RegClass) {
170 } else if (RC == &X86::GR32RegClass) {
172 } else if (RC == &X86::GR16RegClass) {
174 } else if (RC == &X86::GR8RegClass) {
176 } else if (RC == &X86::GR32_RegClass) {
178 } else if (RC == &X86::GR16_RegClass) {
180 } else if (RC == &X86::RFP80RegClass) {
181 Opc = X86::ST_FpP80m; // pops
182 } else if (RC == &X86::RFP64RegClass) {
184 } else if (RC == &X86::RFP32RegClass) {
186 } else if (RC == &X86::FR32RegClass) {
188 } else if (RC == &X86::FR64RegClass) {
190 } else if (RC == &X86::VR128RegClass) {
191 // FIXME: Use movaps once we are capable of selectively
192 // aligning functions that spill SSE registers on 16-byte boundaries.
193 Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
194 } else if (RC == &X86::VR64RegClass) {
195 Opc = X86::MMX_MOVQ64mr;
197 assert(0 && "Unknown regclass");
204 const TargetRegisterClass *
205 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
206 if (RC == &X86::CCRRegClass)
208 return &X86::GR64RegClass;
210 return &X86::GR32RegClass;
214 void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
215 MachineBasicBlock::iterator I,
217 const MachineInstr *Orig) const {
218 // MOV32r0 etc. are implemented with xor which clobbers condition code.
219 // Re-materialize them as movri instructions to avoid side effects.
220 switch (Orig->getOpcode()) {
222 BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
225 BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
228 BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
231 BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
234 MachineInstr *MI = Orig->clone();
235 MI->getOperand(0).setReg(DestReg);
243 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
244 static const unsigned CalleeSavedRegs32Bit[] = {
245 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
248 static const unsigned CalleeSavedRegs32EHRet[] = {
249 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
252 static const unsigned CalleeSavedRegs64Bit[] = {
253 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
257 return CalleeSavedRegs64Bit;
260 MachineFrameInfo *MFI = MF->getFrameInfo();
261 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
262 if (MMI && MMI->callsEHReturn())
263 return CalleeSavedRegs32EHRet;
265 return CalleeSavedRegs32Bit;
269 const TargetRegisterClass* const*
270 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
271 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
272 &X86::GR32RegClass, &X86::GR32RegClass,
273 &X86::GR32RegClass, &X86::GR32RegClass, 0
275 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
276 &X86::GR32RegClass, &X86::GR32RegClass,
277 &X86::GR32RegClass, &X86::GR32RegClass,
278 &X86::GR32RegClass, &X86::GR32RegClass, 0
280 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
281 &X86::GR64RegClass, &X86::GR64RegClass,
282 &X86::GR64RegClass, &X86::GR64RegClass,
283 &X86::GR64RegClass, &X86::GR64RegClass, 0
287 return CalleeSavedRegClasses64Bit;
290 MachineFrameInfo *MFI = MF->getFrameInfo();
291 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
292 if (MMI && MMI->callsEHReturn())
293 return CalleeSavedRegClasses32EHRet;
295 return CalleeSavedRegClasses32Bit;
300 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
301 BitVector Reserved(getNumRegs());
302 Reserved.set(X86::RSP);
303 Reserved.set(X86::ESP);
304 Reserved.set(X86::SP);
305 Reserved.set(X86::SPL);
307 Reserved.set(X86::RBP);
308 Reserved.set(X86::EBP);
309 Reserved.set(X86::BP);
310 Reserved.set(X86::BPL);
315 //===----------------------------------------------------------------------===//
316 // Stack Frame Processing methods
317 //===----------------------------------------------------------------------===//
319 // hasFP - Return true if the specified function should have a dedicated frame
320 // pointer register. This is true if the function has variable sized allocas or
321 // if frame pointer elimination is disabled.
323 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
324 MachineFrameInfo *MFI = MF.getFrameInfo();
325 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
327 return (NoFramePointerElim ||
328 MFI->hasVarSizedObjects() ||
329 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
330 (MMI && MMI->callsUnwindInit()));
333 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
334 return !MF.getFrameInfo()->hasVarSizedObjects();
337 void X86RegisterInfo::
338 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
339 MachineBasicBlock::iterator I) const {
340 if (!hasReservedCallFrame(MF)) {
341 // If the stack pointer can be changed after prologue, turn the
342 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
343 // adjcallstackdown instruction into 'add ESP, <amt>'
344 // TODO: consider using push / pop instead of sub + store / add
345 MachineInstr *Old = I;
346 uint64_t Amount = Old->getOperand(0).getImm();
348 // We need to keep the stack aligned properly. To do this, we round the
349 // amount of space needed for the outgoing arguments up to the next
350 // alignment boundary.
351 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
353 MachineInstr *New = 0;
354 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
355 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
356 .addReg(StackPtr).addImm(Amount);
358 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
359 // factor out the amount the callee already popped.
360 uint64_t CalleeAmt = Old->getOperand(1).getImm();
363 unsigned Opc = (Amount < 128) ?
364 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
365 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
366 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
370 // Replace the pseudo instruction with a new instruction...
371 if (New) MBB.insert(I, New);
373 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
374 // If we are performing frame pointer elimination and if the callee pops
375 // something off the stack pointer, add it back. We do this until we have
376 // more advanced stack pointer tracking ability.
377 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
378 unsigned Opc = (CalleeAmt < 128) ?
379 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
380 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
382 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
390 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
391 int SPAdj, RegScavenger *RS) const{
392 assert(SPAdj == 0 && "Unexpected");
395 MachineInstr &MI = *II;
396 MachineFunction &MF = *MI.getParent()->getParent();
397 while (!MI.getOperand(i).isFrameIndex()) {
399 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
402 int FrameIndex = MI.getOperand(i).getIndex();
403 // This must be part of a four operand memory reference. Replace the
404 // FrameIndex with base register with EBP. Add an offset to the offset.
405 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
407 // Now add the frame object offset to the offset from EBP.
408 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
409 MI.getOperand(i+3).getImm()+SlotSize;
412 Offset += MF.getFrameInfo()->getStackSize();
414 Offset += SlotSize; // Skip the saved EBP
415 // Skip the RETADDR move area
416 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
417 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
418 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
421 MI.getOperand(i+3).ChangeToImmediate(Offset);
425 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
426 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
427 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
428 if (TailCallReturnAddrDelta < 0) {
429 // create RETURNADDR area
439 CreateFixedObject(-TailCallReturnAddrDelta,
440 (-1*SlotSize)+TailCallReturnAddrDelta);
443 assert((TailCallReturnAddrDelta <= 0) &&
444 "The Delta should always be zero or negative");
445 // Create a frame entry for the EBP register that must be saved.
446 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
448 TailCallReturnAddrDelta);
449 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
450 "Slot for EBP register must be last in order to be found!");
454 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
455 /// stack pointer by a constant value.
457 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
458 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
459 const TargetInstrInfo &TII) {
460 bool isSub = NumBytes < 0;
461 uint64_t Offset = isSub ? -NumBytes : NumBytes;
464 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
465 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
467 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
468 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
469 uint64_t Chunk = (1LL << 31) - 1;
472 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
473 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
478 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
480 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
481 unsigned StackPtr, uint64_t *NumBytes = NULL) {
482 if (MBBI == MBB.begin()) return;
484 MachineBasicBlock::iterator PI = prior(MBBI);
485 unsigned Opc = PI->getOpcode();
486 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
487 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
488 PI->getOperand(0).getReg() == StackPtr) {
490 *NumBytes += PI->getOperand(2).getImm();
492 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
493 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
494 PI->getOperand(0).getReg() == StackPtr) {
496 *NumBytes -= PI->getOperand(2).getImm();
501 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
503 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
504 MachineBasicBlock::iterator &MBBI,
505 unsigned StackPtr, uint64_t *NumBytes = NULL) {
508 if (MBBI == MBB.end()) return;
510 MachineBasicBlock::iterator NI = next(MBBI);
511 if (NI == MBB.end()) return;
513 unsigned Opc = NI->getOpcode();
514 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
515 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
516 NI->getOperand(0).getReg() == StackPtr) {
518 *NumBytes -= NI->getOperand(2).getImm();
521 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
522 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
523 NI->getOperand(0).getReg() == StackPtr) {
525 *NumBytes += NI->getOperand(2).getImm();
531 /// mergeSPUpdates - Checks the instruction before/after the passed
532 /// instruction. If it is an ADD/SUB instruction it is deleted
533 /// argument and the stack adjustment is returned as a positive value for ADD
534 /// and a negative for SUB.
535 static int mergeSPUpdates(MachineBasicBlock &MBB,
536 MachineBasicBlock::iterator &MBBI,
538 bool doMergeWithPrevious) {
540 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
541 (!doMergeWithPrevious && MBBI == MBB.end()))
546 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
547 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
548 unsigned Opc = PI->getOpcode();
549 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
550 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
551 PI->getOperand(0).getReg() == StackPtr){
552 Offset += PI->getOperand(2).getImm();
554 if (!doMergeWithPrevious) MBBI = NI;
555 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
556 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
557 PI->getOperand(0).getReg() == StackPtr) {
558 Offset -= PI->getOperand(2).getImm();
560 if (!doMergeWithPrevious) MBBI = NI;
566 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
567 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
568 MachineFrameInfo *MFI = MF.getFrameInfo();
569 const Function* Fn = MF.getFunction();
570 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
571 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
572 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
573 MachineBasicBlock::iterator MBBI = MBB.begin();
575 // Prepare for frame info.
576 unsigned FrameLabelId = 0;
578 // Get the number of bytes to allocate from the FrameInfo.
579 uint64_t StackSize = MFI->getStackSize();
580 // Add RETADDR move area to callee saved frame size.
581 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
582 if (TailCallReturnAddrDelta < 0)
583 X86FI->setCalleeSavedFrameSize(
584 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
585 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
587 // Insert stack pointer adjustment for later moving of return addr. Only
588 // applies to tail call optimized functions where the callee argument stack
589 // size is bigger than the callers.
590 if (TailCallReturnAddrDelta < 0) {
591 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
592 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
596 // Get the offset of the stack slot for the EBP register... which is
597 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
598 // Update the frame offset adjustment.
599 MFI->setOffsetAdjustment(SlotSize-NumBytes);
601 // Save EBP into the appropriate stack slot...
602 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
604 NumBytes -= SlotSize;
606 if (MMI && MMI->needsFrameInfo()) {
607 // Mark effective beginning of when frame pointer becomes valid.
608 FrameLabelId = MMI->NextLabelID();
609 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
612 // Update EBP with the new base value...
613 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
617 unsigned ReadyLabelId = 0;
618 if (MMI && MMI->needsFrameInfo()) {
619 // Mark effective beginning of when frame pointer is ready.
620 ReadyLabelId = MMI->NextLabelID();
621 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
624 // Skip the callee-saved push instructions.
625 while (MBBI != MBB.end() &&
626 (MBBI->getOpcode() == X86::PUSH32r ||
627 MBBI->getOpcode() == X86::PUSH64r))
630 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
631 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
632 // Check, whether EAX is livein for this function
633 bool isEAXAlive = false;
634 for (MachineRegisterInfo::livein_iterator
635 II = MF.getRegInfo().livein_begin(),
636 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
637 unsigned Reg = II->first;
638 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
639 Reg == X86::AH || Reg == X86::AL);
642 // Function prologue calls _alloca to probe the stack when allocating
643 // more than 4k bytes in one go. Touching the stack at 4K increments is
644 // necessary to ensure that the guard pages used by the OS virtual memory
645 // manager are allocated in correct sequence.
647 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
648 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
649 .addExternalSymbol("_alloca");
652 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
653 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
654 // allocated bytes for EAX.
655 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
656 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
657 .addExternalSymbol("_alloca");
659 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
660 StackPtr, NumBytes-4);
661 MBB.insert(MBBI, MI);
664 // If there is an SUB32ri of ESP immediately before this instruction,
665 // merge the two. This can be the case when tail call elimination is
666 // enabled and the callee has more arguments then the caller.
667 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
668 // If there is an ADD32ri or SUB32ri of ESP immediately after this
669 // instruction, merge the two instructions.
670 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
673 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
677 if (MMI && MMI->needsFrameInfo()) {
678 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
679 const TargetData *TD = MF.getTarget().getTargetData();
681 // Calculate amount of bytes used for return address storing
683 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
684 TargetFrameInfo::StackGrowsUp ?
685 TD->getPointerSize() : -TD->getPointerSize());
688 // Show update of SP.
691 MachineLocation SPDst(MachineLocation::VirtualFP);
692 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
693 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
695 MachineLocation SPDst(MachineLocation::VirtualFP);
696 MachineLocation SPSrc(MachineLocation::VirtualFP,
697 -StackSize+stackGrowth);
698 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
701 //FIXME: Verify & implement for FP
702 MachineLocation SPDst(StackPtr);
703 MachineLocation SPSrc(StackPtr, stackGrowth);
704 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
707 // Add callee saved registers to move list.
708 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
710 // FIXME: This is dirty hack. The code itself is pretty mess right now.
711 // It should be rewritten from scratch and generalized sometimes.
713 // Determine maximum offset (minumum due to stack growth)
714 int64_t MaxOffset = 0;
715 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
716 MaxOffset = std::min(MaxOffset,
717 MFI->getObjectOffset(CSI[I].getFrameIdx()));
720 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
721 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
722 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
723 unsigned Reg = CSI[I].getReg();
724 Offset = (MaxOffset-Offset+saveAreaOffset);
725 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
726 MachineLocation CSSrc(Reg);
727 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
732 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
733 MachineLocation FPSrc(FramePtr);
734 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
737 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
738 MachineLocation FPSrc(MachineLocation::VirtualFP);
739 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
742 // If it's main() on Cygwin\Mingw32 we should align stack as well
743 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
744 Subtarget->isTargetCygMing()) {
745 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
746 .addReg(X86::ESP).addImm(-StackAlign);
749 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
750 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
754 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
755 MachineBasicBlock &MBB) const {
756 const MachineFrameInfo *MFI = MF.getFrameInfo();
757 const Function* Fn = MF.getFunction();
758 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
759 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
760 MachineBasicBlock::iterator MBBI = prior(MBB.end());
761 unsigned RetOpcode = MBBI->getOpcode();
766 case X86::TCRETURNdi:
767 case X86::TCRETURNri:
768 case X86::TCRETURNri64:
769 case X86::TCRETURNdi64:
773 case X86::TAILJMPm: break; // These are ok
775 assert(0 && "Can only insert epilog into returning blocks");
778 // Get the number of bytes to allocate from the FrameInfo
779 uint64_t StackSize = MFI->getStackSize();
780 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
781 uint64_t NumBytes = StackSize - CSSize;
785 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
786 NumBytes -= SlotSize;
789 // Skip the callee-saved pop instructions.
790 while (MBBI != MBB.begin()) {
791 MachineBasicBlock::iterator PI = prior(MBBI);
792 unsigned Opc = PI->getOpcode();
793 if (Opc != X86::POP32r && Opc != X86::POP64r && !TII.isTerminatorInstr(Opc))
798 // If there is an ADD32ri or SUB32ri of ESP immediately before this
799 // instruction, merge the two instructions.
800 if (NumBytes || MFI->hasVarSizedObjects())
801 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
803 // If dynamic alloca is used, then reset esp to point to the last callee-saved
804 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
805 // aligned stack in the prologue, - revert stack changes back. Note: we're
806 // assuming, that frame pointer was forced for main()
807 if (MFI->hasVarSizedObjects() ||
808 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
809 Subtarget->isTargetCygMing())) {
810 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
812 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
814 MBB.insert(MBBI, MI);
816 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
822 // adjust stack pointer back: ESP += numbytes
824 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
826 // We're returning from function via eh_return.
827 if (RetOpcode == X86::EH_RETURN) {
828 MBBI = prior(MBB.end());
829 MachineOperand &DestAddr = MBBI->getOperand(0);
830 assert(DestAddr.isRegister() && "Offset should be in register!");
831 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
832 addReg(DestAddr.getReg());
833 // Tail call return: adjust the stack pointer and jump to callee
834 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
835 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
836 MBBI = prior(MBB.end());
837 MachineOperand &JumpTarget = MBBI->getOperand(0);
838 MachineOperand &StackAdjust = MBBI->getOperand(1);
839 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
841 // Adjust stack pointer.
842 int StackAdj = StackAdjust.getImm();
843 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
845 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
846 // Incoporate the retaddr area.
847 Offset = StackAdj-MaxTCDelta;
848 assert(Offset >= 0 && "Offset should never be negative");
850 // Check for possible merge with preceeding ADD instruction.
851 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
852 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
854 // Jump to label or value in register.
855 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
856 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
857 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
858 else if (RetOpcode== X86::TCRETURNri64) {
859 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
861 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
862 // Delete the pseudo instruction TCRETURN.
864 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
865 (X86FI->getTCReturnAddrDelta() < 0)) {
866 // Add the return addr area delta back since we are not tail calling.
867 int delta = -1*X86FI->getTCReturnAddrDelta();
868 MBBI = prior(MBB.end());
869 // Check for possible merge with preceeding ADD instruction.
870 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
871 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
875 unsigned X86RegisterInfo::getRARegister() const {
877 return X86::RIP; // Should have dwarf #16
879 return X86::EIP; // Should have dwarf #8
882 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
883 return hasFP(MF) ? FramePtr : StackPtr;
886 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
888 // Calculate amount of bytes used for return address storing
889 int stackGrowth = (Is64Bit ? -8 : -4);
891 // Initial state of the frame pointer is esp+4.
892 MachineLocation Dst(MachineLocation::VirtualFP);
893 MachineLocation Src(StackPtr, stackGrowth);
894 Moves.push_back(MachineMove(0, Dst, Src));
896 // Add return address to move list
897 MachineLocation CSDst(StackPtr, stackGrowth);
898 MachineLocation CSSrc(getRARegister());
899 Moves.push_back(MachineMove(0, CSDst, CSSrc));
902 unsigned X86RegisterInfo::getEHExceptionRegister() const {
903 assert(0 && "What is the exception register");
907 unsigned X86RegisterInfo::getEHHandlerRegister() const {
908 assert(0 && "What is the exception handler register");
913 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
920 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
922 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
924 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
926 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
932 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
934 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
936 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
938 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
940 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
942 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
944 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
946 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
948 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
950 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
952 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
954 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
956 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
958 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
960 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
962 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
969 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
971 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
973 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
975 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
977 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
979 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
981 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
983 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
985 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
987 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
989 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
991 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
993 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
995 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
997 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
999 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1004 default: return Reg;
1005 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1007 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1009 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1011 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1013 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1015 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1017 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1019 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1021 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1023 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1025 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1027 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1029 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1031 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1033 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1035 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1040 default: return Reg;
1041 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1043 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1045 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1047 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1049 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1051 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1053 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1055 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1057 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1059 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1061 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1063 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1065 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1067 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1069 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1071 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1080 #include "X86GenRegisterInfo.inc"