1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/SSARegMap.h"
30 #include "llvm/Target/TargetAsmInfo.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
42 NoFusing("disable-spill-fusing",
43 cl::desc("Disable fusing of spill code into instructions"));
45 PrintFailedFusing("print-failed-fuse-candidates",
46 cl::desc("Print instructions that the allocator wants to"
47 " fuse, but the X86 backend currently can't"),
51 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
52 const TargetInstrInfo &tii)
53 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
55 // Cache some information.
56 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
57 Is64Bit = Subtarget->is64Bit();
58 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 SmallVector<unsigned,16> AmbEntries;
70 static const unsigned OpTbl2Addr[][2] = {
71 { X86::ADC32ri, X86::ADC32mi },
72 { X86::ADC32ri8, X86::ADC32mi8 },
73 { X86::ADC32rr, X86::ADC32mr },
74 { X86::ADC64ri32, X86::ADC64mi32 },
75 { X86::ADC64ri8, X86::ADC64mi8 },
76 { X86::ADC64rr, X86::ADC64mr },
77 { X86::ADD16ri, X86::ADD16mi },
78 { X86::ADD16ri8, X86::ADD16mi8 },
79 { X86::ADD16rr, X86::ADD16mr },
80 { X86::ADD32ri, X86::ADD32mi },
81 { X86::ADD32ri8, X86::ADD32mi8 },
82 { X86::ADD32rr, X86::ADD32mr },
83 { X86::ADD64ri32, X86::ADD64mi32 },
84 { X86::ADD64ri8, X86::ADD64mi8 },
85 { X86::ADD64rr, X86::ADD64mr },
86 { X86::ADD8ri, X86::ADD8mi },
87 { X86::ADD8rr, X86::ADD8mr },
88 { X86::AND16ri, X86::AND16mi },
89 { X86::AND16ri8, X86::AND16mi8 },
90 { X86::AND16rr, X86::AND16mr },
91 { X86::AND32ri, X86::AND32mi },
92 { X86::AND32ri8, X86::AND32mi8 },
93 { X86::AND32rr, X86::AND32mr },
94 { X86::AND64ri32, X86::AND64mi32 },
95 { X86::AND64ri8, X86::AND64mi8 },
96 { X86::AND64rr, X86::AND64mr },
97 { X86::AND8ri, X86::AND8mi },
98 { X86::AND8rr, X86::AND8mr },
99 { X86::DEC16r, X86::DEC16m },
100 { X86::DEC32r, X86::DEC32m },
101 { X86::DEC64_16r, X86::DEC64_16m },
102 { X86::DEC64_32r, X86::DEC64_32m },
103 { X86::DEC64r, X86::DEC64m },
104 { X86::DEC8r, X86::DEC8m },
105 { X86::INC16r, X86::INC16m },
106 { X86::INC32r, X86::INC32m },
107 { X86::INC64_16r, X86::INC64_16m },
108 { X86::INC64_32r, X86::INC64_32m },
109 { X86::INC64r, X86::INC64m },
110 { X86::INC8r, X86::INC8m },
111 { X86::NEG16r, X86::NEG16m },
112 { X86::NEG32r, X86::NEG32m },
113 { X86::NEG64r, X86::NEG64m },
114 { X86::NEG8r, X86::NEG8m },
115 { X86::NOT16r, X86::NOT16m },
116 { X86::NOT32r, X86::NOT32m },
117 { X86::NOT64r, X86::NOT64m },
118 { X86::NOT8r, X86::NOT8m },
119 { X86::OR16ri, X86::OR16mi },
120 { X86::OR16ri8, X86::OR16mi8 },
121 { X86::OR16rr, X86::OR16mr },
122 { X86::OR32ri, X86::OR32mi },
123 { X86::OR32ri8, X86::OR32mi8 },
124 { X86::OR32rr, X86::OR32mr },
125 { X86::OR64ri32, X86::OR64mi32 },
126 { X86::OR64ri8, X86::OR64mi8 },
127 { X86::OR64rr, X86::OR64mr },
128 { X86::OR8ri, X86::OR8mi },
129 { X86::OR8rr, X86::OR8mr },
130 { X86::ROL16r1, X86::ROL16m1 },
131 { X86::ROL16rCL, X86::ROL16mCL },
132 { X86::ROL16ri, X86::ROL16mi },
133 { X86::ROL32r1, X86::ROL32m1 },
134 { X86::ROL32rCL, X86::ROL32mCL },
135 { X86::ROL32ri, X86::ROL32mi },
136 { X86::ROL64r1, X86::ROL64m1 },
137 { X86::ROL64rCL, X86::ROL64mCL },
138 { X86::ROL64ri, X86::ROL64mi },
139 { X86::ROL8r1, X86::ROL8m1 },
140 { X86::ROL8rCL, X86::ROL8mCL },
141 { X86::ROL8ri, X86::ROL8mi },
142 { X86::ROR16r1, X86::ROR16m1 },
143 { X86::ROR16rCL, X86::ROR16mCL },
144 { X86::ROR16ri, X86::ROR16mi },
145 { X86::ROR32r1, X86::ROR32m1 },
146 { X86::ROR32rCL, X86::ROR32mCL },
147 { X86::ROR32ri, X86::ROR32mi },
148 { X86::ROR64r1, X86::ROR64m1 },
149 { X86::ROR64rCL, X86::ROR64mCL },
150 { X86::ROR64ri, X86::ROR64mi },
151 { X86::ROR8r1, X86::ROR8m1 },
152 { X86::ROR8rCL, X86::ROR8mCL },
153 { X86::ROR8ri, X86::ROR8mi },
154 { X86::SAR16r1, X86::SAR16m1 },
155 { X86::SAR16rCL, X86::SAR16mCL },
156 { X86::SAR16ri, X86::SAR16mi },
157 { X86::SAR32r1, X86::SAR32m1 },
158 { X86::SAR32rCL, X86::SAR32mCL },
159 { X86::SAR32ri, X86::SAR32mi },
160 { X86::SAR64r1, X86::SAR64m1 },
161 { X86::SAR64rCL, X86::SAR64mCL },
162 { X86::SAR64ri, X86::SAR64mi },
163 { X86::SAR8r1, X86::SAR8m1 },
164 { X86::SAR8rCL, X86::SAR8mCL },
165 { X86::SAR8ri, X86::SAR8mi },
166 { X86::SBB32ri, X86::SBB32mi },
167 { X86::SBB32ri8, X86::SBB32mi8 },
168 { X86::SBB32rr, X86::SBB32mr },
169 { X86::SBB64ri32, X86::SBB64mi32 },
170 { X86::SBB64ri8, X86::SBB64mi8 },
171 { X86::SBB64rr, X86::SBB64mr },
172 { X86::SHL16r1, X86::SHL16m1 },
173 { X86::SHL16rCL, X86::SHL16mCL },
174 { X86::SHL16ri, X86::SHL16mi },
175 { X86::SHL32r1, X86::SHL32m1 },
176 { X86::SHL32rCL, X86::SHL32mCL },
177 { X86::SHL32ri, X86::SHL32mi },
178 { X86::SHL64r1, X86::SHL64m1 },
179 { X86::SHL64rCL, X86::SHL64mCL },
180 { X86::SHL64ri, X86::SHL64mi },
181 { X86::SHL8r1, X86::SHL8m1 },
182 { X86::SHL8rCL, X86::SHL8mCL },
183 { X86::SHL8ri, X86::SHL8mi },
184 { X86::SHLD16rrCL, X86::SHLD16mrCL },
185 { X86::SHLD16rri8, X86::SHLD16mri8 },
186 { X86::SHLD32rrCL, X86::SHLD32mrCL },
187 { X86::SHLD32rri8, X86::SHLD32mri8 },
188 { X86::SHLD64rrCL, X86::SHLD64mrCL },
189 { X86::SHLD64rri8, X86::SHLD64mri8 },
190 { X86::SHR16r1, X86::SHR16m1 },
191 { X86::SHR16rCL, X86::SHR16mCL },
192 { X86::SHR16ri, X86::SHR16mi },
193 { X86::SHR32r1, X86::SHR32m1 },
194 { X86::SHR32rCL, X86::SHR32mCL },
195 { X86::SHR32ri, X86::SHR32mi },
196 { X86::SHR64r1, X86::SHR64m1 },
197 { X86::SHR64rCL, X86::SHR64mCL },
198 { X86::SHR64ri, X86::SHR64mi },
199 { X86::SHR8r1, X86::SHR8m1 },
200 { X86::SHR8rCL, X86::SHR8mCL },
201 { X86::SHR8ri, X86::SHR8mi },
202 { X86::SHRD16rrCL, X86::SHRD16mrCL },
203 { X86::SHRD16rri8, X86::SHRD16mri8 },
204 { X86::SHRD32rrCL, X86::SHRD32mrCL },
205 { X86::SHRD32rri8, X86::SHRD32mri8 },
206 { X86::SHRD64rrCL, X86::SHRD64mrCL },
207 { X86::SHRD64rri8, X86::SHRD64mri8 },
208 { X86::SUB16ri, X86::SUB16mi },
209 { X86::SUB16ri8, X86::SUB16mi8 },
210 { X86::SUB16rr, X86::SUB16mr },
211 { X86::SUB32ri, X86::SUB32mi },
212 { X86::SUB32ri8, X86::SUB32mi8 },
213 { X86::SUB32rr, X86::SUB32mr },
214 { X86::SUB64ri32, X86::SUB64mi32 },
215 { X86::SUB64ri8, X86::SUB64mi8 },
216 { X86::SUB64rr, X86::SUB64mr },
217 { X86::SUB8ri, X86::SUB8mi },
218 { X86::SUB8rr, X86::SUB8mr },
219 { X86::XOR16ri, X86::XOR16mi },
220 { X86::XOR16ri8, X86::XOR16mi8 },
221 { X86::XOR16rr, X86::XOR16mr },
222 { X86::XOR32ri, X86::XOR32mi },
223 { X86::XOR32ri8, X86::XOR32mi8 },
224 { X86::XOR32rr, X86::XOR32mr },
225 { X86::XOR64ri32, X86::XOR64mi32 },
226 { X86::XOR64ri8, X86::XOR64mi8 },
227 { X86::XOR64rr, X86::XOR64mr },
228 { X86::XOR8ri, X86::XOR8mi },
229 { X86::XOR8rr, X86::XOR8mr }
232 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
233 unsigned RegOp = OpTbl2Addr[i][0];
234 unsigned MemOp = OpTbl2Addr[i][1];
235 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp)))
236 assert(false && "Duplicated entries?");
237 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
238 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
239 std::make_pair(RegOp, AuxInfo))))
240 AmbEntries.push_back(MemOp);
243 // If the third value is 1, then it's folding either a load or a store.
244 static const unsigned OpTbl0[][3] = {
245 { X86::CALL32r, X86::CALL32m, 1 },
246 { X86::CALL64r, X86::CALL64m, 1 },
247 { X86::CMP16ri, X86::CMP16mi, 1 },
248 { X86::CMP16ri8, X86::CMP16mi8, 1 },
249 { X86::CMP32ri, X86::CMP32mi, 1 },
250 { X86::CMP32ri8, X86::CMP32mi8, 1 },
251 { X86::CMP64ri32, X86::CMP64mi32, 1 },
252 { X86::CMP64ri8, X86::CMP64mi8, 1 },
253 { X86::CMP8ri, X86::CMP8mi, 1 },
254 { X86::DIV16r, X86::DIV16m, 1 },
255 { X86::DIV32r, X86::DIV32m, 1 },
256 { X86::DIV64r, X86::DIV64m, 1 },
257 { X86::DIV8r, X86::DIV8m, 1 },
258 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
259 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
260 { X86::IDIV16r, X86::IDIV16m, 1 },
261 { X86::IDIV32r, X86::IDIV32m, 1 },
262 { X86::IDIV64r, X86::IDIV64m, 1 },
263 { X86::IDIV8r, X86::IDIV8m, 1 },
264 { X86::IMUL16r, X86::IMUL16m, 1 },
265 { X86::IMUL32r, X86::IMUL32m, 1 },
266 { X86::IMUL64r, X86::IMUL64m, 1 },
267 { X86::IMUL8r, X86::IMUL8m, 1 },
268 { X86::JMP32r, X86::JMP32m, 1 },
269 { X86::JMP64r, X86::JMP64m, 1 },
270 { X86::MOV16ri, X86::MOV16mi, 0 },
271 { X86::MOV16rr, X86::MOV16mr, 0 },
272 { X86::MOV16to16_, X86::MOV16_mr, 0 },
273 { X86::MOV32ri, X86::MOV32mi, 0 },
274 { X86::MOV32rr, X86::MOV32mr, 0 },
275 { X86::MOV32to32_, X86::MOV32_mr, 0 },
276 { X86::MOV64ri32, X86::MOV64mi32, 0 },
277 { X86::MOV64rr, X86::MOV64mr, 0 },
278 { X86::MOV8ri, X86::MOV8mi, 0 },
279 { X86::MOV8rr, X86::MOV8mr, 0 },
280 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
281 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
282 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
283 { X86::MOVPQIto64rr,X86::MOVPQIto64mr, 0 },
284 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
285 { X86::MOVSDrr, X86::MOVSDmr, 0 },
286 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
287 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
288 { X86::MOVSSrr, X86::MOVSSmr, 0 },
289 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
290 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
291 { X86::MUL16r, X86::MUL16m, 1 },
292 { X86::MUL32r, X86::MUL32m, 1 },
293 { X86::MUL64r, X86::MUL64m, 1 },
294 { X86::MUL8r, X86::MUL8m, 1 },
295 { X86::SETAEr, X86::SETAEm, 0 },
296 { X86::SETAr, X86::SETAm, 0 },
297 { X86::SETBEr, X86::SETBEm, 0 },
298 { X86::SETBr, X86::SETBm, 0 },
299 { X86::SETEr, X86::SETEm, 0 },
300 { X86::SETGEr, X86::SETGEm, 0 },
301 { X86::SETGr, X86::SETGm, 0 },
302 { X86::SETLEr, X86::SETLEm, 0 },
303 { X86::SETLr, X86::SETLm, 0 },
304 { X86::SETNEr, X86::SETNEm, 0 },
305 { X86::SETNPr, X86::SETNPm, 0 },
306 { X86::SETNSr, X86::SETNSm, 0 },
307 { X86::SETPr, X86::SETPm, 0 },
308 { X86::SETSr, X86::SETSm, 0 },
309 { X86::TAILJMPr, X86::TAILJMPm, 1 },
310 { X86::TEST16ri, X86::TEST16mi, 1 },
311 { X86::TEST32ri, X86::TEST32mi, 1 },
312 { X86::TEST64ri32, X86::TEST64mi32, 1 },
313 { X86::TEST8ri, X86::TEST8mi, 1 },
314 { X86::XCHG16rr, X86::XCHG16mr, 0 },
315 { X86::XCHG32rr, X86::XCHG32mr, 0 },
316 { X86::XCHG64rr, X86::XCHG64mr, 0 },
317 { X86::XCHG8rr, X86::XCHG8mr, 0 }
320 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
321 unsigned RegOp = OpTbl0[i][0];
322 unsigned MemOp = OpTbl0[i][1];
323 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp)))
324 assert(false && "Duplicated entries?");
325 unsigned FoldedLoad = OpTbl0[i][2];
326 // Index 0, folded load or store.
327 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
328 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
329 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
330 std::make_pair(RegOp, AuxInfo))))
331 AmbEntries.push_back(MemOp);
334 static const unsigned OpTbl1[][2] = {
335 { X86::CMP16rr, X86::CMP16rm },
336 { X86::CMP32rr, X86::CMP32rm },
337 { X86::CMP64rr, X86::CMP64rm },
338 { X86::CMP8rr, X86::CMP8rm },
339 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
340 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
341 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
342 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
343 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
344 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
345 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
346 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
347 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
348 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
349 { X86::FsMOVAPDrr, X86::MOVSDrm },
350 { X86::FsMOVAPSrr, X86::MOVSSrm },
351 { X86::IMUL16rri, X86::IMUL16rmi },
352 { X86::IMUL16rri8, X86::IMUL16rmi8 },
353 { X86::IMUL32rri, X86::IMUL32rmi },
354 { X86::IMUL32rri8, X86::IMUL32rmi8 },
355 { X86::IMUL64rri32, X86::IMUL64rmi32 },
356 { X86::IMUL64rri8, X86::IMUL64rmi8 },
357 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
358 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
359 { X86::Int_COMISDrr, X86::Int_COMISDrm },
360 { X86::Int_COMISSrr, X86::Int_COMISSrm },
361 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
362 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
363 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
364 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
365 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
366 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
367 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
368 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
369 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
370 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
371 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
372 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
373 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
374 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
375 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
376 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
377 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
378 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
379 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
380 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
381 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
382 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
383 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
384 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
385 { X86::MOV16rr, X86::MOV16rm },
386 { X86::MOV16to16_, X86::MOV16_rm },
387 { X86::MOV32rr, X86::MOV32rm },
388 { X86::MOV32to32_, X86::MOV32_rm },
389 { X86::MOV64rr, X86::MOV64rm },
390 { X86::MOV64toPQIrr, X86::MOV64toPQIrm },
391 { X86::MOV64toSDrr, X86::MOV64toSDrm },
392 { X86::MOV8rr, X86::MOV8rm },
393 { X86::MOVAPDrr, X86::MOVAPDrm },
394 { X86::MOVAPSrr, X86::MOVAPSrm },
395 { X86::MOVDDUPrr, X86::MOVDDUPrm },
396 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
397 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
398 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
399 { X86::MOVSDrr, X86::MOVSDrm },
400 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
401 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
402 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
403 { X86::MOVSSrr, X86::MOVSSrm },
404 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
405 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
406 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
407 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
408 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
409 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
410 { X86::MOVUPDrr, X86::MOVUPDrm },
411 { X86::MOVUPSrr, X86::MOVUPSrm },
412 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
413 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
414 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
415 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
416 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
417 { X86::PSHUFDri, X86::PSHUFDmi },
418 { X86::PSHUFHWri, X86::PSHUFHWmi },
419 { X86::PSHUFLWri, X86::PSHUFLWmi },
420 { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
421 { X86::RCPPSr, X86::RCPPSm },
422 { X86::RCPPSr_Int, X86::RCPPSm_Int },
423 { X86::RSQRTPSr, X86::RSQRTPSm },
424 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
425 { X86::RSQRTSSr, X86::RSQRTSSm },
426 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
427 { X86::SQRTPDr, X86::SQRTPDm },
428 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
429 { X86::SQRTPSr, X86::SQRTPSm },
430 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
431 { X86::SQRTSDr, X86::SQRTSDm },
432 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
433 { X86::SQRTSSr, X86::SQRTSSm },
434 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
435 { X86::TEST16rr, X86::TEST16rm },
436 { X86::TEST32rr, X86::TEST32rm },
437 { X86::TEST64rr, X86::TEST64rm },
438 { X86::TEST8rr, X86::TEST8rm },
439 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
440 { X86::UCOMISDrr, X86::UCOMISDrm },
441 { X86::UCOMISSrr, X86::UCOMISSrm },
442 { X86::XCHG16rr, X86::XCHG16rm },
443 { X86::XCHG32rr, X86::XCHG32rm },
444 { X86::XCHG64rr, X86::XCHG64rm },
445 { X86::XCHG8rr, X86::XCHG8rm }
448 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
449 unsigned RegOp = OpTbl1[i][0];
450 unsigned MemOp = OpTbl1[i][1];
451 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp)))
452 assert(false && "Duplicated entries?");
453 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
454 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
455 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
456 std::make_pair(RegOp, AuxInfo))))
457 AmbEntries.push_back(MemOp);
460 static const unsigned OpTbl2[][2] = {
461 { X86::ADC32rr, X86::ADC32rm },
462 { X86::ADC64rr, X86::ADC64rm },
463 { X86::ADD16rr, X86::ADD16rm },
464 { X86::ADD32rr, X86::ADD32rm },
465 { X86::ADD64rr, X86::ADD64rm },
466 { X86::ADD8rr, X86::ADD8rm },
467 { X86::ADDPDrr, X86::ADDPDrm },
468 { X86::ADDPSrr, X86::ADDPSrm },
469 { X86::ADDSDrr, X86::ADDSDrm },
470 { X86::ADDSSrr, X86::ADDSSrm },
471 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
472 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
473 { X86::AND16rr, X86::AND16rm },
474 { X86::AND32rr, X86::AND32rm },
475 { X86::AND64rr, X86::AND64rm },
476 { X86::AND8rr, X86::AND8rm },
477 { X86::ANDNPDrr, X86::ANDNPDrm },
478 { X86::ANDNPSrr, X86::ANDNPSrm },
479 { X86::ANDPDrr, X86::ANDPDrm },
480 { X86::ANDPSrr, X86::ANDPSrm },
481 { X86::CMOVA16rr, X86::CMOVA16rm },
482 { X86::CMOVA32rr, X86::CMOVA32rm },
483 { X86::CMOVA64rr, X86::CMOVA64rm },
484 { X86::CMOVAE16rr, X86::CMOVAE16rm },
485 { X86::CMOVAE32rr, X86::CMOVAE32rm },
486 { X86::CMOVAE64rr, X86::CMOVAE64rm },
487 { X86::CMOVB16rr, X86::CMOVB16rm },
488 { X86::CMOVB32rr, X86::CMOVB32rm },
489 { X86::CMOVB64rr, X86::CMOVB64rm },
490 { X86::CMOVBE16rr, X86::CMOVBE16rm },
491 { X86::CMOVBE32rr, X86::CMOVBE32rm },
492 { X86::CMOVBE64rr, X86::CMOVBE64rm },
493 { X86::CMOVE16rr, X86::CMOVE16rm },
494 { X86::CMOVE32rr, X86::CMOVE32rm },
495 { X86::CMOVE64rr, X86::CMOVE64rm },
496 { X86::CMOVG16rr, X86::CMOVG16rm },
497 { X86::CMOVG32rr, X86::CMOVG32rm },
498 { X86::CMOVG64rr, X86::CMOVG64rm },
499 { X86::CMOVGE16rr, X86::CMOVGE16rm },
500 { X86::CMOVGE32rr, X86::CMOVGE32rm },
501 { X86::CMOVGE64rr, X86::CMOVGE64rm },
502 { X86::CMOVL16rr, X86::CMOVL16rm },
503 { X86::CMOVL32rr, X86::CMOVL32rm },
504 { X86::CMOVL64rr, X86::CMOVL64rm },
505 { X86::CMOVLE16rr, X86::CMOVLE16rm },
506 { X86::CMOVLE32rr, X86::CMOVLE32rm },
507 { X86::CMOVLE64rr, X86::CMOVLE64rm },
508 { X86::CMOVNE16rr, X86::CMOVNE16rm },
509 { X86::CMOVNE32rr, X86::CMOVNE32rm },
510 { X86::CMOVNE64rr, X86::CMOVNE64rm },
511 { X86::CMOVNP16rr, X86::CMOVNP16rm },
512 { X86::CMOVNP32rr, X86::CMOVNP32rm },
513 { X86::CMOVNP64rr, X86::CMOVNP64rm },
514 { X86::CMOVNS16rr, X86::CMOVNS16rm },
515 { X86::CMOVNS32rr, X86::CMOVNS32rm },
516 { X86::CMOVNS64rr, X86::CMOVNS64rm },
517 { X86::CMOVP16rr, X86::CMOVP16rm },
518 { X86::CMOVP32rr, X86::CMOVP32rm },
519 { X86::CMOVP64rr, X86::CMOVP64rm },
520 { X86::CMOVS16rr, X86::CMOVS16rm },
521 { X86::CMOVS32rr, X86::CMOVS32rm },
522 { X86::CMOVS64rr, X86::CMOVS64rm },
523 { X86::CMPPDrri, X86::CMPPDrmi },
524 { X86::CMPPSrri, X86::CMPPSrmi },
525 { X86::CMPSDrr, X86::CMPSDrm },
526 { X86::CMPSSrr, X86::CMPSSrm },
527 { X86::DIVPDrr, X86::DIVPDrm },
528 { X86::DIVPSrr, X86::DIVPSrm },
529 { X86::DIVSDrr, X86::DIVSDrm },
530 { X86::DIVSSrr, X86::DIVSSrm },
531 { X86::HADDPDrr, X86::HADDPDrm },
532 { X86::HADDPSrr, X86::HADDPSrm },
533 { X86::HSUBPDrr, X86::HSUBPDrm },
534 { X86::HSUBPSrr, X86::HSUBPSrm },
535 { X86::IMUL16rr, X86::IMUL16rm },
536 { X86::IMUL32rr, X86::IMUL32rm },
537 { X86::IMUL64rr, X86::IMUL64rm },
538 { X86::MAXPDrr, X86::MAXPDrm },
539 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
540 { X86::MAXPSrr, X86::MAXPSrm },
541 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
542 { X86::MAXSDrr, X86::MAXSDrm },
543 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
544 { X86::MAXSSrr, X86::MAXSSrm },
545 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
546 { X86::MINPDrr, X86::MINPDrm },
547 { X86::MINPDrr_Int, X86::MINPDrm_Int },
548 { X86::MINPSrr, X86::MINPSrm },
549 { X86::MINPSrr_Int, X86::MINPSrm_Int },
550 { X86::MINSDrr, X86::MINSDrm },
551 { X86::MINSDrr_Int, X86::MINSDrm_Int },
552 { X86::MINSSrr, X86::MINSSrm },
553 { X86::MINSSrr_Int, X86::MINSSrm_Int },
554 { X86::MULPDrr, X86::MULPDrm },
555 { X86::MULPSrr, X86::MULPSrm },
556 { X86::MULSDrr, X86::MULSDrm },
557 { X86::MULSSrr, X86::MULSSrm },
558 { X86::OR16rr, X86::OR16rm },
559 { X86::OR32rr, X86::OR32rm },
560 { X86::OR64rr, X86::OR64rm },
561 { X86::OR8rr, X86::OR8rm },
562 { X86::ORPDrr, X86::ORPDrm },
563 { X86::ORPSrr, X86::ORPSrm },
564 { X86::PACKSSDWrr, X86::PACKSSDWrm },
565 { X86::PACKSSWBrr, X86::PACKSSWBrm },
566 { X86::PACKUSWBrr, X86::PACKUSWBrm },
567 { X86::PADDBrr, X86::PADDBrm },
568 { X86::PADDDrr, X86::PADDDrm },
569 { X86::PADDQrr, X86::PADDQrm },
570 { X86::PADDSBrr, X86::PADDSBrm },
571 { X86::PADDSWrr, X86::PADDSWrm },
572 { X86::PADDWrr, X86::PADDWrm },
573 { X86::PANDNrr, X86::PANDNrm },
574 { X86::PANDrr, X86::PANDrm },
575 { X86::PAVGBrr, X86::PAVGBrm },
576 { X86::PAVGWrr, X86::PAVGWrm },
577 { X86::PCMPEQBrr, X86::PCMPEQBrm },
578 { X86::PCMPEQDrr, X86::PCMPEQDrm },
579 { X86::PCMPEQWrr, X86::PCMPEQWrm },
580 { X86::PCMPGTBrr, X86::PCMPGTBrm },
581 { X86::PCMPGTDrr, X86::PCMPGTDrm },
582 { X86::PCMPGTWrr, X86::PCMPGTWrm },
583 { X86::PINSRWrri, X86::PINSRWrmi },
584 { X86::PMADDWDrr, X86::PMADDWDrm },
585 { X86::PMAXSWrr, X86::PMAXSWrm },
586 { X86::PMAXUBrr, X86::PMAXUBrm },
587 { X86::PMINSWrr, X86::PMINSWrm },
588 { X86::PMINUBrr, X86::PMINUBrm },
589 { X86::PMULHUWrr, X86::PMULHUWrm },
590 { X86::PMULHWrr, X86::PMULHWrm },
591 { X86::PMULLWrr, X86::PMULLWrm },
592 { X86::PMULUDQrr, X86::PMULUDQrm },
593 { X86::PORrr, X86::PORrm },
594 { X86::PSADBWrr, X86::PSADBWrm },
595 { X86::PSLLDrr, X86::PSLLDrm },
596 { X86::PSLLQrr, X86::PSLLQrm },
597 { X86::PSLLWrr, X86::PSLLWrm },
598 { X86::PSRADrr, X86::PSRADrm },
599 { X86::PSRAWrr, X86::PSRAWrm },
600 { X86::PSRLDrr, X86::PSRLDrm },
601 { X86::PSRLQrr, X86::PSRLQrm },
602 { X86::PSRLWrr, X86::PSRLWrm },
603 { X86::PSUBBrr, X86::PSUBBrm },
604 { X86::PSUBDrr, X86::PSUBDrm },
605 { X86::PSUBSBrr, X86::PSUBSBrm },
606 { X86::PSUBSWrr, X86::PSUBSWrm },
607 { X86::PSUBWrr, X86::PSUBWrm },
608 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
609 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
610 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
611 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
612 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
613 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
614 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
615 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
616 { X86::PXORrr, X86::PXORrm },
617 { X86::SBB32rr, X86::SBB32rm },
618 { X86::SBB64rr, X86::SBB64rm },
619 { X86::SHUFPDrri, X86::SHUFPDrmi },
620 { X86::SHUFPSrri, X86::SHUFPSrmi },
621 { X86::SUB16rr, X86::SUB16rm },
622 { X86::SUB32rr, X86::SUB32rm },
623 { X86::SUB64rr, X86::SUB64rm },
624 { X86::SUB8rr, X86::SUB8rm },
625 { X86::SUBPDrr, X86::SUBPDrm },
626 { X86::SUBPSrr, X86::SUBPSrm },
627 { X86::SUBSDrr, X86::SUBSDrm },
628 { X86::SUBSSrr, X86::SUBSSrm },
629 // FIXME: TEST*rr -> swapped operand of TEST*mr.
630 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
631 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
632 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
633 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
634 { X86::XOR16rr, X86::XOR16rm },
635 { X86::XOR32rr, X86::XOR32rm },
636 { X86::XOR64rr, X86::XOR64rm },
637 { X86::XOR8rr, X86::XOR8rm },
638 { X86::XORPDrr, X86::XORPDrm },
639 { X86::XORPSrr, X86::XORPSrm }
642 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
643 unsigned RegOp = OpTbl2[i][0];
644 unsigned MemOp = OpTbl2[i][1];
645 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp)))
646 assert(false && "Duplicated entries?");
647 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
648 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
649 std::make_pair(RegOp, AuxInfo))))
650 AmbEntries.push_back(MemOp);
653 // Remove ambiguous entries.
654 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
657 // getDwarfRegNum - This function maps LLVM register identifiers to the
658 // Dwarf specific numbering, used in debug info and exception tables.
659 // The registers are given "basic" dwarf numbers in the .td files,
660 // which are for the 64-bit target. These are collected by TableGen
661 // into X86GenRegisterInfo::getDwarfRegNum and overridden here for
663 // FIXME: Comments in gcc indicate that Darwin uses different numbering
664 // for debug info and exception handling info:( The numbering here is
665 // for exception handling.
667 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo) const {
668 int n = X86GenRegisterInfo::getDwarfRegNum(RegNo);
669 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
670 if (!Subtarget->is64Bit()) {
671 // Numbers are all different for 32-bit. Further, some of them
672 // differ between Darwin and other targets.
674 default: assert(0 && "Invalid argument to getDwarfRegNum");
676 case 0: return 0; // ax
677 case 1: return 2; // dx
678 case 2: return 1; // cx
679 case 3: return 3; // bx
680 case 4: return 6; // si
681 case 5: return 7; // di
682 case 6: return (Subtarget->isDarwin) ? 4 : 5; // bp
683 case 7: return (Subtarget->isDarwin) ? 5 : 4; // sp
685 case 8: case 9: case 10: case 11: // r8..r15
686 case 12: case 13: case 14: case 15:
687 assert(0 && "Invalid register in 32-bit mode");
690 case 16: return 8; // ip
692 case 17: case 18: case 19: case 20: // xmm0..xmm7
693 case 21: case 22: case 23: case 24:
696 case 25: case 26: case 27: case 28: // xmm8..xmm15
697 case 29: case 30: case 31: case 32:
698 assert(0 && "Invalid register in 32-bit mode");
701 case 33: case 34: case 35: case 36: // st0..st7
702 case 37: case 38: case 39: case 40:
703 return (Subtarget->isDarwin) ? n-21 : n-22;
705 case 41: case 42: case 43: case 44: // mm0..mm7
706 case 45: case 46: case 47: case 48:
713 // getX86RegNum - This function maps LLVM register identifiers to their X86
714 // specific numbering, which is used in various places encoding instructions.
716 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
718 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
719 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
720 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
721 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
722 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
724 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
726 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
728 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
731 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
733 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
735 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
737 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
739 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
741 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
743 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
745 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
748 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
749 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
750 return RegNo-X86::ST0;
752 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
753 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
754 return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM0);
755 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
756 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
757 return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM8);
760 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
761 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
766 bool X86RegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
767 MachineBasicBlock::iterator MI,
768 const std::vector<CalleeSavedInfo> &CSI) const {
772 MachineFunction &MF = *MBB.getParent();
773 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
774 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
775 unsigned Opc = Is64Bit ? X86::PUSH64r : X86::PUSH32r;
776 for (unsigned i = CSI.size(); i != 0; --i) {
777 unsigned Reg = CSI[i-1].getReg();
778 // Add the callee-saved register as live-in. It's killed at the spill.
780 BuildMI(MBB, MI, TII.get(Opc)).addReg(Reg);
785 bool X86RegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
786 MachineBasicBlock::iterator MI,
787 const std::vector<CalleeSavedInfo> &CSI) const {
791 unsigned Opc = Is64Bit ? X86::POP64r : X86::POP32r;
792 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
793 unsigned Reg = CSI[i].getReg();
794 BuildMI(MBB, MI, TII.get(Opc), Reg);
799 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
800 MachineOperand &MO) {
802 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
803 else if (MO.isImmediate())
804 MIB = MIB.addImm(MO.getImm());
805 else if (MO.isFrameIndex())
806 MIB = MIB.addFrameIndex(MO.getFrameIndex());
807 else if (MO.isGlobalAddress())
808 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
809 else if (MO.isConstantPoolIndex())
810 MIB = MIB.addConstantPoolIndex(MO.getConstantPoolIndex(), MO.getOffset());
811 else if (MO.isJumpTableIndex())
812 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
813 else if (MO.isExternalSymbol())
814 MIB = MIB.addExternalSymbol(MO.getSymbolName());
816 assert(0 && "Unknown operand for X86InstrAddOperand!");
821 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
822 unsigned StackAlign) {
824 if (RC == &X86::GR64RegClass) {
826 } else if (RC == &X86::GR32RegClass) {
828 } else if (RC == &X86::GR16RegClass) {
830 } else if (RC == &X86::GR8RegClass) {
832 } else if (RC == &X86::GR32_RegClass) {
834 } else if (RC == &X86::GR16_RegClass) {
836 } else if (RC == &X86::RFP80RegClass) {
837 Opc = X86::ST_FpP80m; // pops
838 } else if (RC == &X86::RFP64RegClass) {
840 } else if (RC == &X86::RFP32RegClass) {
842 } else if (RC == &X86::FR32RegClass) {
844 } else if (RC == &X86::FR64RegClass) {
846 } else if (RC == &X86::VR128RegClass) {
847 // FIXME: Use movaps once we are capable of selectively
848 // aligning functions that spill SSE registers on 16-byte boundaries.
849 Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
850 } else if (RC == &X86::VR64RegClass) {
851 Opc = X86::MMX_MOVQ64mr;
853 assert(0 && "Unknown regclass");
860 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
861 MachineBasicBlock::iterator MI,
862 unsigned SrcReg, int FrameIdx,
863 const TargetRegisterClass *RC) const {
864 unsigned Opc = getStoreRegOpcode(RC, StackAlign);
865 addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
866 .addReg(SrcReg, false, false, true);
869 void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
870 SmallVectorImpl<MachineOperand> &Addr,
871 const TargetRegisterClass *RC,
872 SmallVectorImpl<MachineInstr*> &NewMIs) const {
873 unsigned Opc = getStoreRegOpcode(RC, StackAlign);
874 MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
875 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
876 MIB = X86InstrAddOperand(MIB, Addr[i]);
877 MIB.addReg(SrcReg, false, false, true);
878 NewMIs.push_back(MIB);
881 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
882 unsigned StackAlign) {
884 if (RC == &X86::GR64RegClass) {
886 } else if (RC == &X86::GR32RegClass) {
888 } else if (RC == &X86::GR16RegClass) {
890 } else if (RC == &X86::GR8RegClass) {
892 } else if (RC == &X86::GR32_RegClass) {
894 } else if (RC == &X86::GR16_RegClass) {
896 } else if (RC == &X86::RFP80RegClass) {
898 } else if (RC == &X86::RFP64RegClass) {
900 } else if (RC == &X86::RFP32RegClass) {
902 } else if (RC == &X86::FR32RegClass) {
904 } else if (RC == &X86::FR64RegClass) {
906 } else if (RC == &X86::VR128RegClass) {
907 // FIXME: Use movaps once we are capable of selectively
908 // aligning functions that spill SSE registers on 16-byte boundaries.
909 Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
910 } else if (RC == &X86::VR64RegClass) {
911 Opc = X86::MMX_MOVQ64rm;
913 assert(0 && "Unknown regclass");
920 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
921 MachineBasicBlock::iterator MI,
922 unsigned DestReg, int FrameIdx,
923 const TargetRegisterClass *RC) const{
924 unsigned Opc = getLoadRegOpcode(RC, StackAlign);
925 addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
928 void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
929 SmallVectorImpl<MachineOperand> &Addr,
930 const TargetRegisterClass *RC,
931 SmallVectorImpl<MachineInstr*> &NewMIs) const {
932 unsigned Opc = getLoadRegOpcode(RC, StackAlign);
933 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
934 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
935 MIB = X86InstrAddOperand(MIB, Addr[i]);
936 NewMIs.push_back(MIB);
939 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
940 MachineBasicBlock::iterator MI,
941 unsigned DestReg, unsigned SrcReg,
942 const TargetRegisterClass *DestRC,
943 const TargetRegisterClass *SrcRC) const {
944 if (DestRC != SrcRC) {
945 // Moving EFLAGS to / from another register requires a push and a pop.
946 if (SrcRC == &X86::CCRRegClass) {
947 assert(SrcReg == X86::EFLAGS);
948 if (DestRC == &X86::GR64RegClass) {
949 BuildMI(MBB, MI, TII.get(X86::PUSHFQ));
950 BuildMI(MBB, MI, TII.get(X86::POP64r), DestReg);
952 } else if (DestRC == &X86::GR32RegClass) {
953 BuildMI(MBB, MI, TII.get(X86::PUSHFD));
954 BuildMI(MBB, MI, TII.get(X86::POP32r), DestReg);
957 } else if (DestRC == &X86::CCRRegClass) {
958 assert(DestReg == X86::EFLAGS);
959 if (SrcRC == &X86::GR64RegClass) {
960 BuildMI(MBB, MI, TII.get(X86::PUSH64r)).addReg(SrcReg);
961 BuildMI(MBB, MI, TII.get(X86::POPFQ));
963 } else if (SrcRC == &X86::GR32RegClass) {
964 BuildMI(MBB, MI, TII.get(X86::PUSH32r)).addReg(SrcReg);
965 BuildMI(MBB, MI, TII.get(X86::POPFD));
969 cerr << "Not yet supported!";
974 if (DestRC == &X86::GR64RegClass) {
976 } else if (DestRC == &X86::GR32RegClass) {
978 } else if (DestRC == &X86::GR16RegClass) {
980 } else if (DestRC == &X86::GR8RegClass) {
982 } else if (DestRC == &X86::GR32_RegClass) {
984 } else if (DestRC == &X86::GR16_RegClass) {
986 } else if (DestRC == &X86::RFP32RegClass) {
987 Opc = X86::MOV_Fp3232;
988 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
989 Opc = X86::MOV_Fp6464;
990 } else if (DestRC == &X86::RFP80RegClass) {
991 Opc = X86::MOV_Fp8080;
992 } else if (DestRC == &X86::FR32RegClass) {
993 Opc = X86::FsMOVAPSrr;
994 } else if (DestRC == &X86::FR64RegClass) {
995 Opc = X86::FsMOVAPDrr;
996 } else if (DestRC == &X86::VR128RegClass) {
998 } else if (DestRC == &X86::VR64RegClass) {
999 Opc = X86::MMX_MOVQ64rr;
1001 assert(0 && "Unknown regclass");
1004 BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
1007 const TargetRegisterClass *
1008 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
1009 if (RC == &X86::CCRRegClass)
1011 return &X86::GR64RegClass;
1013 return &X86::GR32RegClass;
1017 void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
1018 MachineBasicBlock::iterator I,
1020 const MachineInstr *Orig) const {
1021 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1022 // Re-materialize them as movri instructions to avoid side effects.
1023 switch (Orig->getOpcode()) {
1025 BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
1028 BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
1031 BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
1034 BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
1037 MachineInstr *MI = Orig->clone();
1038 MI->getOperand(0).setReg(DestReg);
1045 static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
1046 SmallVector<MachineOperand,4> &MOs,
1047 MachineInstr *MI, const TargetInstrInfo &TII) {
1048 // Create the base instruction with the memory operand as the first part.
1049 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1050 MachineInstrBuilder MIB(NewMI);
1051 unsigned NumAddrOps = MOs.size();
1052 for (unsigned i = 0; i != NumAddrOps; ++i)
1053 MIB = X86InstrAddOperand(MIB, MOs[i]);
1054 if (NumAddrOps < 4) // FrameIndex only
1055 MIB.addImm(1).addReg(0).addImm(0);
1057 // Loop over the rest of the ri operands, converting them over.
1058 unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
1059 for (unsigned i = 0; i != NumOps; ++i) {
1060 MachineOperand &MO = MI->getOperand(i+2);
1061 MIB = X86InstrAddOperand(MIB, MO);
1063 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
1064 MachineOperand &MO = MI->getOperand(i);
1065 MIB = X86InstrAddOperand(MIB, MO);
1070 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
1071 SmallVector<MachineOperand,4> &MOs,
1072 MachineInstr *MI, const TargetInstrInfo &TII) {
1073 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1074 MachineInstrBuilder MIB(NewMI);
1076 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1077 MachineOperand &MO = MI->getOperand(i);
1079 assert(MO.isRegister() && "Expected to fold into reg operand!");
1080 unsigned NumAddrOps = MOs.size();
1081 for (unsigned i = 0; i != NumAddrOps; ++i)
1082 MIB = X86InstrAddOperand(MIB, MOs[i]);
1083 if (NumAddrOps < 4) // FrameIndex only
1084 MIB.addImm(1).addReg(0).addImm(0);
1086 MIB = X86InstrAddOperand(MIB, MO);
1092 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
1093 SmallVector<MachineOperand,4> &MOs,
1095 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
1097 unsigned NumAddrOps = MOs.size();
1098 for (unsigned i = 0; i != NumAddrOps; ++i)
1099 MIB = X86InstrAddOperand(MIB, MOs[i]);
1100 if (NumAddrOps < 4) // FrameIndex only
1101 MIB.addImm(1).addReg(0).addImm(0);
1102 return MIB.addImm(0);
1106 X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
1107 SmallVector<MachineOperand,4> &MOs) const {
1108 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1109 bool isTwoAddrFold = false;
1110 unsigned NumOps = TII.getNumOperands(MI->getOpcode());
1111 bool isTwoAddr = NumOps > 1 &&
1112 MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
1114 MachineInstr *NewMI = NULL;
1115 // Folding a memory location into the two-address part of a two-address
1116 // instruction is different than folding it other places. It requires
1117 // replacing the *two* registers with the memory location.
1118 if (isTwoAddr && NumOps >= 2 && i < 2 &&
1119 MI->getOperand(0).isRegister() &&
1120 MI->getOperand(1).isRegister() &&
1121 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
1122 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1123 isTwoAddrFold = true;
1124 } else if (i == 0) { // If operand 0
1125 if (MI->getOpcode() == X86::MOV16r0)
1126 NewMI = MakeM0Inst(TII, X86::MOV16mi, MOs, MI);
1127 else if (MI->getOpcode() == X86::MOV32r0)
1128 NewMI = MakeM0Inst(TII, X86::MOV32mi, MOs, MI);
1129 else if (MI->getOpcode() == X86::MOV64r0)
1130 NewMI = MakeM0Inst(TII, X86::MOV64mi32, MOs, MI);
1131 else if (MI->getOpcode() == X86::MOV8r0)
1132 NewMI = MakeM0Inst(TII, X86::MOV8mi, MOs, MI);
1134 NewMI->copyKillDeadInfo(MI);
1138 OpcodeTablePtr = &RegOp2MemOpTable0;
1139 } else if (i == 1) {
1140 OpcodeTablePtr = &RegOp2MemOpTable1;
1141 } else if (i == 2) {
1142 OpcodeTablePtr = &RegOp2MemOpTable2;
1145 // If table selected...
1146 if (OpcodeTablePtr) {
1147 // Find the Opcode to fuse
1148 DenseMap<unsigned*, unsigned>::iterator I =
1149 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
1150 if (I != OpcodeTablePtr->end()) {
1152 NewMI = FuseTwoAddrInst(I->second, MOs, MI, TII);
1154 NewMI = FuseInst(I->second, i, MOs, MI, TII);
1155 NewMI->copyKillDeadInfo(MI);
1161 if (PrintFailedFusing)
1162 cerr << "We failed to fuse ("
1163 << ((i == 1) ? "r" : "s") << "): " << *MI;
1168 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
1169 int FrameIndex) const {
1170 // Check switch flag
1171 if (NoFusing) return NULL;
1172 SmallVector<MachineOperand,4> MOs;
1173 MOs.push_back(MachineOperand::CreateFrameIndex(FrameIndex));
1174 return foldMemoryOperand(MI, OpNum, MOs);
1177 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
1178 MachineInstr *LoadMI) const {
1179 // Check switch flag
1180 if (NoFusing) return NULL;
1181 SmallVector<MachineOperand,4> MOs;
1182 unsigned NumOps = TII.getNumOperands(LoadMI->getOpcode());
1183 for (unsigned i = NumOps - 4; i != NumOps; ++i)
1184 MOs.push_back(LoadMI->getOperand(i));
1185 return foldMemoryOperand(MI, OpNum, MOs);
1188 unsigned X86RegisterInfo::getOpcodeAfterMemoryFold(unsigned Opc,
1189 unsigned OpNum) const {
1190 // Check switch flag
1191 if (NoFusing) return 0;
1192 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1193 unsigned NumOps = TII.getNumOperands(Opc);
1194 bool isTwoAddr = NumOps > 1 &&
1195 TII.getOperandConstraint(Opc, 1, TOI::TIED_TO) != -1;
1197 // Folding a memory location into the two-address part of a two-address
1198 // instruction is different than folding it other places. It requires
1199 // replacing the *two* registers with the memory location.
1200 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
1201 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1202 } else if (OpNum == 0) { // If operand 0
1205 return X86::MOV16mi;
1207 return X86::MOV32mi;
1209 return X86::MOV64mi32;
1214 OpcodeTablePtr = &RegOp2MemOpTable0;
1215 } else if (OpNum == 1) {
1216 OpcodeTablePtr = &RegOp2MemOpTable1;
1217 } else if (OpNum == 2) {
1218 OpcodeTablePtr = &RegOp2MemOpTable2;
1221 if (OpcodeTablePtr) {
1222 // Find the Opcode to fuse
1223 DenseMap<unsigned*, unsigned>::iterator I =
1224 OpcodeTablePtr->find((unsigned*)Opc);
1225 if (I != OpcodeTablePtr->end())
1231 bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
1232 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
1233 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1234 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
1235 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
1236 if (I == MemOp2RegOpTable.end())
1238 unsigned Opc = I->second.first;
1239 unsigned Index = I->second.second & 0xf;
1240 bool FoldedLoad = I->second.second & (1 << 4);
1241 bool FoldedStore = I->second.second & (1 << 5);
1242 if (UnfoldLoad && !FoldedLoad)
1244 UnfoldLoad &= FoldedLoad;
1245 if (UnfoldStore && !FoldedStore)
1247 UnfoldStore &= FoldedStore;
1249 const TargetInstrDescriptor &TID = TII.get(Opc);
1250 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1251 const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1252 ? TII.getPointerRegClass() : getRegClass(TOI.RegClass);
1253 SmallVector<MachineOperand,4> AddrOps;
1254 SmallVector<MachineOperand,2> BeforeOps;
1255 SmallVector<MachineOperand,2> AfterOps;
1256 SmallVector<MachineOperand,4> ImpOps;
1257 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1258 MachineOperand &Op = MI->getOperand(i);
1259 if (i >= Index && i < Index+4)
1260 AddrOps.push_back(Op);
1261 else if (Op.isRegister() && Op.isImplicit())
1262 ImpOps.push_back(Op);
1264 BeforeOps.push_back(Op);
1266 AfterOps.push_back(Op);
1269 // Emit the load instruction.
1271 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
1273 // Address operands cannot be marked isKill.
1274 for (unsigned i = 1; i != 5; ++i) {
1275 MachineOperand &MO = NewMIs[0]->getOperand(i);
1276 if (MO.isRegister())
1282 // Emit the data processing instruction.
1283 MachineInstr *DataMI = new MachineInstr(TID, true);
1284 MachineInstrBuilder MIB(DataMI);
1287 MIB.addReg(Reg, true);
1288 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
1289 MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
1292 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
1293 MIB = X86InstrAddOperand(MIB, AfterOps[i]);
1294 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
1295 MachineOperand &MO = ImpOps[i];
1296 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
1298 NewMIs.push_back(MIB);
1300 // Emit the store instruction.
1302 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
1303 const TargetRegisterClass *DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1304 ? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass);
1305 storeRegToAddr(MF, Reg, AddrOps, DstRC, NewMIs);
1313 X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1314 SmallVectorImpl<SDNode*> &NewNodes) const {
1315 if (!N->isTargetOpcode())
1318 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
1319 MemOp2RegOpTable.find((unsigned*)N->getTargetOpcode());
1320 if (I == MemOp2RegOpTable.end())
1322 unsigned Opc = I->second.first;
1323 unsigned Index = I->second.second & 0xf;
1324 bool FoldedLoad = I->second.second & (1 << 4);
1325 bool FoldedStore = I->second.second & (1 << 5);
1326 const TargetInstrDescriptor &TID = TII.get(Opc);
1327 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1328 const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1329 ? TII.getPointerRegClass() : getRegClass(TOI.RegClass);
1330 std::vector<SDOperand> AddrOps;
1331 std::vector<SDOperand> BeforeOps;
1332 std::vector<SDOperand> AfterOps;
1333 unsigned NumOps = N->getNumOperands();
1334 for (unsigned i = 0; i != NumOps-1; ++i) {
1335 SDOperand Op = N->getOperand(i);
1336 if (i >= Index && i < Index+4)
1337 AddrOps.push_back(Op);
1339 BeforeOps.push_back(Op);
1341 AfterOps.push_back(Op);
1343 SDOperand Chain = N->getOperand(NumOps-1);
1344 AddrOps.push_back(Chain);
1346 // Emit the load instruction.
1349 MVT::ValueType VT = *RC->vt_begin();
1350 Load = DAG.getTargetNode(getLoadRegOpcode(RC, StackAlign), VT, MVT::Other,
1351 &AddrOps[0], AddrOps.size());
1352 NewNodes.push_back(Load);
1355 // Emit the data processing instruction.
1356 std::vector<MVT::ValueType> VTs;
1357 const TargetRegisterClass *DstRC = 0;
1358 if (TID.numDefs > 0) {
1359 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
1360 DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1361 ? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass);
1362 VTs.push_back(*DstRC->vt_begin());
1364 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
1365 MVT::ValueType VT = N->getValueType(i);
1366 if (VT != MVT::Other && i >= TID.numDefs)
1370 BeforeOps.push_back(SDOperand(Load, 0));
1371 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
1372 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
1373 NewNodes.push_back(NewNode);
1375 // Emit the store instruction.
1378 AddrOps.push_back(SDOperand(NewNode, 0));
1379 AddrOps.push_back(Chain);
1380 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, StackAlign),
1381 MVT::Other, &AddrOps[0], AddrOps.size());
1382 NewNodes.push_back(Store);
1388 unsigned X86RegisterInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
1389 bool UnfoldLoad, bool UnfoldStore) const {
1390 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
1391 MemOp2RegOpTable.find((unsigned*)Opc);
1392 if (I == MemOp2RegOpTable.end())
1394 bool FoldedLoad = I->second.second & (1 << 4);
1395 bool FoldedStore = I->second.second & (1 << 5);
1396 if (UnfoldLoad && !FoldedLoad)
1398 if (UnfoldStore && !FoldedStore)
1400 return I->second.first;
1404 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
1405 static const unsigned CalleeSavedRegs32Bit[] = {
1406 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
1409 static const unsigned CalleeSavedRegs32EHRet[] = {
1410 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
1413 static const unsigned CalleeSavedRegs64Bit[] = {
1414 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1418 return CalleeSavedRegs64Bit;
1421 MachineFrameInfo *MFI = MF->getFrameInfo();
1422 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1423 if (MMI && MMI->callsEHReturn())
1424 return CalleeSavedRegs32EHRet;
1426 return CalleeSavedRegs32Bit;
1430 const TargetRegisterClass* const*
1431 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
1432 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
1433 &X86::GR32RegClass, &X86::GR32RegClass,
1434 &X86::GR32RegClass, &X86::GR32RegClass, 0
1436 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
1437 &X86::GR32RegClass, &X86::GR32RegClass,
1438 &X86::GR32RegClass, &X86::GR32RegClass,
1439 &X86::GR32RegClass, &X86::GR32RegClass, 0
1441 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
1442 &X86::GR64RegClass, &X86::GR64RegClass,
1443 &X86::GR64RegClass, &X86::GR64RegClass,
1444 &X86::GR64RegClass, &X86::GR64RegClass, 0
1448 return CalleeSavedRegClasses64Bit;
1451 MachineFrameInfo *MFI = MF->getFrameInfo();
1452 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1453 if (MMI && MMI->callsEHReturn())
1454 return CalleeSavedRegClasses32EHRet;
1456 return CalleeSavedRegClasses32Bit;
1461 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
1462 BitVector Reserved(getNumRegs());
1463 Reserved.set(X86::RSP);
1464 Reserved.set(X86::ESP);
1465 Reserved.set(X86::SP);
1466 Reserved.set(X86::SPL);
1468 Reserved.set(X86::RBP);
1469 Reserved.set(X86::EBP);
1470 Reserved.set(X86::BP);
1471 Reserved.set(X86::BPL);
1476 //===----------------------------------------------------------------------===//
1477 // Stack Frame Processing methods
1478 //===----------------------------------------------------------------------===//
1480 // hasFP - Return true if the specified function should have a dedicated frame
1481 // pointer register. This is true if the function has variable sized allocas or
1482 // if frame pointer elimination is disabled.
1484 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
1485 MachineFrameInfo *MFI = MF.getFrameInfo();
1486 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1488 return (NoFramePointerElim ||
1489 MFI->hasVarSizedObjects() ||
1490 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
1491 (MMI && MMI->callsUnwindInit()));
1494 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
1495 return !MF.getFrameInfo()->hasVarSizedObjects();
1498 void X86RegisterInfo::
1499 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1500 MachineBasicBlock::iterator I) const {
1501 if (!hasReservedCallFrame(MF)) {
1502 // If the stack pointer can be changed after prologue, turn the
1503 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1504 // adjcallstackdown instruction into 'add ESP, <amt>'
1505 // TODO: consider using push / pop instead of sub + store / add
1506 MachineInstr *Old = I;
1507 uint64_t Amount = Old->getOperand(0).getImm();
1509 // We need to keep the stack aligned properly. To do this, we round the
1510 // amount of space needed for the outgoing arguments up to the next
1511 // alignment boundary.
1512 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
1514 MachineInstr *New = 0;
1515 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
1516 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
1517 .addReg(StackPtr).addImm(Amount);
1519 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
1520 // factor out the amount the callee already popped.
1521 uint64_t CalleeAmt = Old->getOperand(1).getImm();
1522 Amount -= CalleeAmt;
1524 unsigned Opc = (Amount < 128) ?
1525 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1526 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1527 New = BuildMI(TII.get(Opc), StackPtr)
1528 .addReg(StackPtr).addImm(Amount);
1532 // Replace the pseudo instruction with a new instruction...
1533 if (New) MBB.insert(I, New);
1535 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
1536 // If we are performing frame pointer elimination and if the callee pops
1537 // something off the stack pointer, add it back. We do this until we have
1538 // more advanced stack pointer tracking ability.
1539 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
1540 unsigned Opc = (CalleeAmt < 128) ?
1541 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1542 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1544 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
1552 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1553 int SPAdj, RegScavenger *RS) const{
1554 assert(SPAdj == 0 && "Unexpected");
1557 MachineInstr &MI = *II;
1558 MachineFunction &MF = *MI.getParent()->getParent();
1559 while (!MI.getOperand(i).isFrameIndex()) {
1561 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1564 int FrameIndex = MI.getOperand(i).getFrameIndex();
1565 // This must be part of a four operand memory reference. Replace the
1566 // FrameIndex with base register with EBP. Add an offset to the offset.
1567 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
1569 // Now add the frame object offset to the offset from EBP.
1570 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
1571 MI.getOperand(i+3).getImm()+SlotSize;
1574 Offset += MF.getFrameInfo()->getStackSize();
1576 Offset += SlotSize; // Skip the saved EBP
1577 // Skip the RETADDR move area
1578 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1579 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1580 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
1583 MI.getOperand(i+3).ChangeToImmediate(Offset);
1587 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
1588 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1589 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1590 if (TailCallReturnAddrDelta < 0) {
1591 // create RETURNADDR area
1601 CreateFixedObject(-TailCallReturnAddrDelta,
1602 (-1*SlotSize)+TailCallReturnAddrDelta);
1605 assert((TailCallReturnAddrDelta <= 0) &&
1606 "The Delta should always be zero or negative");
1607 // Create a frame entry for the EBP register that must be saved.
1608 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
1610 TailCallReturnAddrDelta);
1611 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
1612 "Slot for EBP register must be last in order to be found!");
1616 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
1617 /// stack pointer by a constant value.
1619 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1620 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
1621 const TargetInstrInfo &TII) {
1622 bool isSub = NumBytes < 0;
1623 uint64_t Offset = isSub ? -NumBytes : NumBytes;
1624 unsigned Opc = isSub
1626 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1627 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
1629 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1630 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
1631 uint64_t Chunk = (1LL << 31) - 1;
1634 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
1635 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
1640 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
1642 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1643 unsigned StackPtr, uint64_t *NumBytes = NULL) {
1644 if (MBBI == MBB.begin()) return;
1646 MachineBasicBlock::iterator PI = prior(MBBI);
1647 unsigned Opc = PI->getOpcode();
1648 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1649 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1650 PI->getOperand(0).getReg() == StackPtr) {
1652 *NumBytes += PI->getOperand(2).getImm();
1654 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1655 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1656 PI->getOperand(0).getReg() == StackPtr) {
1658 *NumBytes -= PI->getOperand(2).getImm();
1663 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
1665 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
1666 MachineBasicBlock::iterator &MBBI,
1667 unsigned StackPtr, uint64_t *NumBytes = NULL) {
1670 if (MBBI == MBB.end()) return;
1672 MachineBasicBlock::iterator NI = next(MBBI);
1673 if (NI == MBB.end()) return;
1675 unsigned Opc = NI->getOpcode();
1676 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1677 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1678 NI->getOperand(0).getReg() == StackPtr) {
1680 *NumBytes -= NI->getOperand(2).getImm();
1683 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1684 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1685 NI->getOperand(0).getReg() == StackPtr) {
1687 *NumBytes += NI->getOperand(2).getImm();
1693 /// mergeSPUpdates - Checks the instruction before/after the passed
1694 /// instruction. If it is an ADD/SUB instruction it is deleted
1695 /// argument and the stack adjustment is returned as a positive value for ADD
1696 /// and a negative for SUB.
1697 static int mergeSPUpdates(MachineBasicBlock &MBB,
1698 MachineBasicBlock::iterator &MBBI,
1700 bool doMergeWithPrevious) {
1702 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
1703 (!doMergeWithPrevious && MBBI == MBB.end()))
1708 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
1709 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
1710 unsigned Opc = PI->getOpcode();
1711 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1712 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1713 PI->getOperand(0).getReg() == StackPtr){
1714 Offset += PI->getOperand(2).getImm();
1716 if (!doMergeWithPrevious) MBBI = NI;
1717 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1718 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1719 PI->getOperand(0).getReg() == StackPtr) {
1720 Offset -= PI->getOperand(2).getImm();
1722 if (!doMergeWithPrevious) MBBI = NI;
1728 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
1729 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1730 MachineFrameInfo *MFI = MF.getFrameInfo();
1731 const Function* Fn = MF.getFunction();
1732 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
1733 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1734 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1735 MachineBasicBlock::iterator MBBI = MBB.begin();
1737 // Prepare for frame info.
1738 unsigned FrameLabelId = 0;
1740 // Get the number of bytes to allocate from the FrameInfo.
1741 uint64_t StackSize = MFI->getStackSize();
1742 // Add RETADDR move area to callee saved frame size.
1743 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1744 if (TailCallReturnAddrDelta < 0)
1745 X86FI->setCalleeSavedFrameSize(
1746 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
1747 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1749 // Insert stack pointer adjustment for later moving of return addr. Only
1750 // applies to tail call optimized functions where the callee argument stack
1751 // size is bigger than the callers.
1752 if (TailCallReturnAddrDelta < 0) {
1753 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
1754 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
1758 // Get the offset of the stack slot for the EBP register... which is
1759 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1760 // Update the frame offset adjustment.
1761 MFI->setOffsetAdjustment(SlotSize-NumBytes);
1763 // Save EBP into the appropriate stack slot...
1764 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1766 NumBytes -= SlotSize;
1768 if (MMI && MMI->needsFrameInfo()) {
1769 // Mark effective beginning of when frame pointer becomes valid.
1770 FrameLabelId = MMI->NextLabelID();
1771 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
1774 // Update EBP with the new base value...
1775 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1779 unsigned ReadyLabelId = 0;
1780 if (MMI && MMI->needsFrameInfo()) {
1781 // Mark effective beginning of when frame pointer is ready.
1782 ReadyLabelId = MMI->NextLabelID();
1783 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
1786 // Skip the callee-saved push instructions.
1787 while (MBBI != MBB.end() &&
1788 (MBBI->getOpcode() == X86::PUSH32r ||
1789 MBBI->getOpcode() == X86::PUSH64r))
1792 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
1793 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1794 // Check, whether EAX is livein for this function
1795 bool isEAXAlive = false;
1796 for (MachineFunction::livein_iterator II = MF.livein_begin(),
1797 EE = MF.livein_end(); (II != EE) && !isEAXAlive; ++II) {
1798 unsigned Reg = II->first;
1799 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1800 Reg == X86::AH || Reg == X86::AL);
1803 // Function prologue calls _alloca to probe the stack when allocating
1804 // more than 4k bytes in one go. Touching the stack at 4K increments is
1805 // necessary to ensure that the guard pages used by the OS virtual memory
1806 // manager are allocated in correct sequence.
1808 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
1809 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
1810 .addExternalSymbol("_alloca");
1813 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
1814 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1815 // allocated bytes for EAX.
1816 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
1817 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
1818 .addExternalSymbol("_alloca");
1820 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
1821 StackPtr, NumBytes-4);
1822 MBB.insert(MBBI, MI);
1825 // If there is an SUB32ri of ESP immediately before this instruction,
1826 // merge the two. This can be the case when tail call elimination is
1827 // enabled and the callee has more arguments then the caller.
1828 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1829 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1830 // instruction, merge the two instructions.
1831 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1834 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1838 if (MMI && MMI->needsFrameInfo()) {
1839 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1840 const TargetData *TD = MF.getTarget().getTargetData();
1842 // Calculate amount of bytes used for return address storing
1844 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
1845 TargetFrameInfo::StackGrowsUp ?
1846 TD->getPointerSize() : -TD->getPointerSize());
1849 // Show update of SP.
1852 MachineLocation SPDst(MachineLocation::VirtualFP);
1853 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
1854 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1856 MachineLocation SPDst(MachineLocation::VirtualFP);
1857 MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize+stackGrowth);
1858 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1861 //FIXME: Verify & implement for FP
1862 MachineLocation SPDst(StackPtr);
1863 MachineLocation SPSrc(StackPtr, stackGrowth);
1864 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1867 // Add callee saved registers to move list.
1868 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1870 // FIXME: This is dirty hack. The code itself is pretty mess right now.
1871 // It should be rewritten from scratch and generalized sometimes.
1873 // Determine maximum offset (minumum due to stack growth)
1874 int64_t MaxOffset = 0;
1875 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
1876 MaxOffset = std::min(MaxOffset,
1877 MFI->getObjectOffset(CSI[I].getFrameIdx()));
1879 // Calculate offsets
1880 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
1881 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
1882 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1883 unsigned Reg = CSI[I].getReg();
1884 Offset = (MaxOffset-Offset+saveAreaOffset);
1885 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1886 MachineLocation CSSrc(Reg);
1887 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1892 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
1893 MachineLocation FPSrc(FramePtr);
1894 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1897 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
1898 MachineLocation FPSrc(MachineLocation::VirtualFP);
1899 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1902 // If it's main() on Cygwin\Mingw32 we should align stack as well
1903 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1904 Subtarget->isTargetCygMing()) {
1905 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
1906 .addReg(X86::ESP).addImm(-StackAlign);
1909 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
1910 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1914 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1915 MachineBasicBlock &MBB) const {
1916 const MachineFrameInfo *MFI = MF.getFrameInfo();
1917 const Function* Fn = MF.getFunction();
1918 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1919 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
1920 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1921 unsigned RetOpcode = MBBI->getOpcode();
1923 switch (RetOpcode) {
1926 case X86::TCRETURNdi:
1927 case X86::TCRETURNri:
1928 case X86::TCRETURNri64:
1929 case X86::TCRETURNdi64:
1930 case X86::EH_RETURN:
1933 case X86::TAILJMPm: break; // These are ok
1935 assert(0 && "Can only insert epilog into returning blocks");
1938 // Get the number of bytes to allocate from the FrameInfo
1939 uint64_t StackSize = MFI->getStackSize();
1940 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1941 uint64_t NumBytes = StackSize - CSSize;
1945 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1946 NumBytes -= SlotSize;
1949 // Skip the callee-saved pop instructions.
1950 while (MBBI != MBB.begin()) {
1951 MachineBasicBlock::iterator PI = prior(MBBI);
1952 unsigned Opc = PI->getOpcode();
1953 if (Opc != X86::POP32r && Opc != X86::POP64r && !TII.isTerminatorInstr(Opc))
1958 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1959 // instruction, merge the two instructions.
1960 if (NumBytes || MFI->hasVarSizedObjects())
1961 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1963 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1964 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
1965 // aligned stack in the prologue, - revert stack changes back. Note: we're
1966 // assuming, that frame pointer was forced for main()
1967 if (MFI->hasVarSizedObjects() ||
1968 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1969 Subtarget->isTargetCygMing())) {
1970 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1972 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
1974 MBB.insert(MBBI, MI);
1976 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1982 // adjust stack pointer back: ESP += numbytes
1984 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1986 // We're returning from function via eh_return.
1987 if (RetOpcode == X86::EH_RETURN) {
1988 MBBI = prior(MBB.end());
1989 MachineOperand &DestAddr = MBBI->getOperand(0);
1990 assert(DestAddr.isRegister() && "Offset should be in register!");
1991 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1992 addReg(DestAddr.getReg());
1993 // Tail call return: adjust the stack pointer and jump to callee
1994 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1995 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1996 MBBI = prior(MBB.end());
1997 MachineOperand &JumpTarget = MBBI->getOperand(0);
1998 MachineOperand &StackAdjust = MBBI->getOperand(1);
1999 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
2001 // Adjust stack pointer.
2002 int StackAdj = StackAdjust.getImm();
2003 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
2005 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
2006 // Incoporate the retaddr area.
2007 Offset = StackAdj-MaxTCDelta;
2008 assert(Offset >= 0 && "Offset should never be negative");
2010 // Check for possible merge with preceeding ADD instruction.
2011 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
2012 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
2014 // Jump to label or value in register.
2015 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
2016 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
2017 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
2018 else if (RetOpcode== X86::TCRETURNri64) {
2019 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
2021 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
2022 // Delete the pseudo instruction TCRETURN.
2024 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
2025 (X86FI->getTCReturnAddrDelta() < 0)) {
2026 // Add the return addr area delta back since we are not tail calling.
2027 int delta = -1*X86FI->getTCReturnAddrDelta();
2028 MBBI = prior(MBB.end());
2029 // Check for possible merge with preceeding ADD instruction.
2030 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
2031 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
2035 unsigned X86RegisterInfo::getRARegister() const {
2037 return X86::RIP; // Should have dwarf #16
2039 return X86::EIP; // Should have dwarf #8
2042 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
2043 return hasFP(MF) ? FramePtr : StackPtr;
2046 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
2048 // Calculate amount of bytes used for return address storing
2049 int stackGrowth = (Is64Bit ? -8 : -4);
2051 // Initial state of the frame pointer is esp+4.
2052 MachineLocation Dst(MachineLocation::VirtualFP);
2053 MachineLocation Src(StackPtr, stackGrowth);
2054 Moves.push_back(MachineMove(0, Dst, Src));
2056 // Add return address to move list
2057 MachineLocation CSDst(StackPtr, stackGrowth);
2058 MachineLocation CSSrc(getRARegister());
2059 Moves.push_back(MachineMove(0, CSDst, CSSrc));
2062 unsigned X86RegisterInfo::getEHExceptionRegister() const {
2063 assert(0 && "What is the exception register");
2067 unsigned X86RegisterInfo::getEHHandlerRegister() const {
2068 assert(0 && "What is the exception handler register");
2073 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
2075 default: return Reg;
2080 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
2082 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
2084 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
2086 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
2092 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
2094 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
2096 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
2098 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
2100 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
2102 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
2104 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
2106 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
2108 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
2110 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
2112 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
2114 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
2116 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
2118 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
2120 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
2122 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
2128 default: return Reg;
2129 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
2131 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
2133 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
2135 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
2137 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
2139 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
2141 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
2143 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
2145 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
2147 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
2149 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
2151 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
2153 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
2155 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
2157 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
2159 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
2164 default: return Reg;
2165 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
2167 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
2169 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
2171 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
2173 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
2175 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
2177 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
2179 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
2181 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
2183 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
2185 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
2187 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
2189 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
2191 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
2193 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
2195 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
2200 default: return Reg;
2201 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
2203 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
2205 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
2207 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
2209 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
2211 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
2213 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
2215 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
2217 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
2219 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
2221 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
2223 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
2225 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
2227 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
2229 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
2231 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
2240 #include "X86GenRegisterInfo.inc"