1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
41 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
42 const TargetInstrInfo &tii)
43 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
45 // Cache some information.
46 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
47 Is64Bit = Subtarget->is64Bit();
48 IsWin64 = Subtarget->isTargetWin64();
49 StackAlign = TM.getFrameInfo()->getStackAlignment();
61 // getDwarfRegNum - This function maps LLVM register identifiers to the
62 // Dwarf specific numbering, used in debug info and exception tables.
64 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
65 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
66 unsigned Flavour = DWARFFlavour::X86_64;
67 if (!Subtarget->is64Bit()) {
68 if (Subtarget->isTargetDarwin()) {
70 Flavour = DWARFFlavour::X86_32_DarwinEH;
72 Flavour = DWARFFlavour::X86_32_Generic;
73 } else if (Subtarget->isTargetCygMing()) {
74 // Unsupported by now, just quick fallback
75 Flavour = DWARFFlavour::X86_32_Generic;
77 Flavour = DWARFFlavour::X86_32_Generic;
81 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
84 // getX86RegNum - This function maps LLVM register identifiers to their X86
85 // specific numbering, which is used in various places encoding instructions.
87 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
89 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
90 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
91 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
92 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
93 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
95 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
97 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
99 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
102 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
106 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
108 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
110 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
112 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
114 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
116 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
119 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
120 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
121 return RegNo-X86::ST0;
123 case X86::XMM0: case X86::XMM8: case X86::MM0:
125 case X86::XMM1: case X86::XMM9: case X86::MM1:
127 case X86::XMM2: case X86::XMM10: case X86::MM2:
129 case X86::XMM3: case X86::XMM11: case X86::MM3:
131 case X86::XMM4: case X86::XMM12: case X86::MM4:
133 case X86::XMM5: case X86::XMM13: case X86::MM5:
135 case X86::XMM6: case X86::XMM14: case X86::MM6:
137 case X86::XMM7: case X86::XMM15: case X86::MM7:
141 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
142 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
147 const TargetRegisterClass *
148 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
149 if (RC == &X86::CCRRegClass) {
151 return &X86::GR64RegClass;
153 return &X86::GR32RegClass;
159 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
160 static const unsigned CalleeSavedRegs32Bit[] = {
161 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
164 static const unsigned CalleeSavedRegs32EHRet[] = {
165 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
168 static const unsigned CalleeSavedRegs64Bit[] = {
169 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
172 static const unsigned CalleeSavedRegsWin64[] = {
173 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
174 X86::R12, X86::R13, X86::R14, X86::R15, 0
179 return CalleeSavedRegsWin64;
181 return CalleeSavedRegs64Bit;
184 MachineFrameInfo *MFI = MF->getFrameInfo();
185 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
186 if (MMI && MMI->callsEHReturn())
187 return CalleeSavedRegs32EHRet;
189 return CalleeSavedRegs32Bit;
193 const TargetRegisterClass* const*
194 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
195 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
196 &X86::GR32RegClass, &X86::GR32RegClass,
197 &X86::GR32RegClass, &X86::GR32RegClass, 0
199 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
200 &X86::GR32RegClass, &X86::GR32RegClass,
201 &X86::GR32RegClass, &X86::GR32RegClass,
202 &X86::GR32RegClass, &X86::GR32RegClass, 0
204 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
205 &X86::GR64RegClass, &X86::GR64RegClass,
206 &X86::GR64RegClass, &X86::GR64RegClass,
207 &X86::GR64RegClass, &X86::GR64RegClass, 0
209 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
210 &X86::GR64RegClass, &X86::GR64RegClass,
211 &X86::GR64RegClass, &X86::GR64RegClass,
212 &X86::GR64RegClass, &X86::GR64RegClass,
213 &X86::GR64RegClass, &X86::GR64RegClass, 0
218 return CalleeSavedRegClassesWin64;
220 return CalleeSavedRegClasses64Bit;
223 MachineFrameInfo *MFI = MF->getFrameInfo();
224 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225 if (MMI && MMI->callsEHReturn())
226 return CalleeSavedRegClasses32EHRet;
228 return CalleeSavedRegClasses32Bit;
233 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
234 BitVector Reserved(getNumRegs());
235 Reserved.set(X86::RSP);
236 Reserved.set(X86::ESP);
237 Reserved.set(X86::SP);
238 Reserved.set(X86::SPL);
240 Reserved.set(X86::RBP);
241 Reserved.set(X86::EBP);
242 Reserved.set(X86::BP);
243 Reserved.set(X86::BPL);
248 //===----------------------------------------------------------------------===//
249 // Stack Frame Processing methods
250 //===----------------------------------------------------------------------===//
252 // hasFP - Return true if the specified function should have a dedicated frame
253 // pointer register. This is true if the function has variable sized allocas or
254 // if frame pointer elimination is disabled.
256 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
257 MachineFrameInfo *MFI = MF.getFrameInfo();
258 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
260 return (NoFramePointerElim ||
261 needsStackRealignment(MF) ||
262 MFI->hasVarSizedObjects() ||
263 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
264 (MMI && MMI->callsUnwindInit()));
267 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
268 MachineFrameInfo *MFI = MF.getFrameInfo();;
270 // FIXME: Currently we don't support stack realignment for functions with
271 // variable-sized allocas
272 return (RealignStack &&
273 (MFI->getMaxAlignment() > StackAlign &&
274 !MFI->hasVarSizedObjects()));
277 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
278 return !MF.getFrameInfo()->hasVarSizedObjects();
281 void X86RegisterInfo::
282 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
283 MachineBasicBlock::iterator I) const {
284 if (!hasReservedCallFrame(MF)) {
285 // If the stack pointer can be changed after prologue, turn the
286 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
287 // adjcallstackdown instruction into 'add ESP, <amt>'
288 // TODO: consider using push / pop instead of sub + store / add
289 MachineInstr *Old = I;
290 uint64_t Amount = Old->getOperand(0).getImm();
292 // We need to keep the stack aligned properly. To do this, we round the
293 // amount of space needed for the outgoing arguments up to the next
294 // alignment boundary.
295 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
297 MachineInstr *New = 0;
298 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
299 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
300 .addReg(StackPtr).addImm(Amount);
302 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
303 // factor out the amount the callee already popped.
304 uint64_t CalleeAmt = Old->getOperand(1).getImm();
307 unsigned Opc = (Amount < 128) ?
308 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
309 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
310 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
314 // Replace the pseudo instruction with a new instruction...
315 if (New) MBB.insert(I, New);
317 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
318 // If we are performing frame pointer elimination and if the callee pops
319 // something off the stack pointer, add it back. We do this until we have
320 // more advanced stack pointer tracking ability.
321 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
322 unsigned Opc = (CalleeAmt < 128) ?
323 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
324 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
326 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
334 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
335 int SPAdj, RegScavenger *RS) const{
336 assert(SPAdj == 0 && "Unexpected");
339 MachineInstr &MI = *II;
340 MachineFunction &MF = *MI.getParent()->getParent();
341 while (!MI.getOperand(i).isFrameIndex()) {
343 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
346 int FrameIndex = MI.getOperand(i).getIndex();
347 // This must be part of a four operand memory reference. Replace the
348 // FrameIndex with base register with EBP. Add an offset to the offset.
349 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
351 // Now add the frame object offset to the offset from EBP.
352 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
353 MI.getOperand(i+3).getImm()+SlotSize;
356 Offset += MF.getFrameInfo()->getStackSize();
358 Offset += SlotSize; // Skip the saved EBP
359 // Skip the RETADDR move area
360 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
361 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
362 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
365 MI.getOperand(i+3).ChangeToImmediate(Offset);
369 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
370 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
371 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
372 if (TailCallReturnAddrDelta < 0) {
373 // create RETURNADDR area
383 CreateFixedObject(-TailCallReturnAddrDelta,
384 (-1*SlotSize)+TailCallReturnAddrDelta);
387 assert((TailCallReturnAddrDelta <= 0) &&
388 "The Delta should always be zero or negative");
389 // Create a frame entry for the EBP register that must be saved.
390 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
392 TailCallReturnAddrDelta);
393 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
394 "Slot for EBP register must be last in order to be found!");
398 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
399 /// stack pointer by a constant value.
401 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
402 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
403 const TargetInstrInfo &TII) {
404 bool isSub = NumBytes < 0;
405 uint64_t Offset = isSub ? -NumBytes : NumBytes;
408 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
409 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
411 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
412 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
413 uint64_t Chunk = (1LL << 31) - 1;
416 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
417 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
422 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
424 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
425 unsigned StackPtr, uint64_t *NumBytes = NULL) {
426 if (MBBI == MBB.begin()) return;
428 MachineBasicBlock::iterator PI = prior(MBBI);
429 unsigned Opc = PI->getOpcode();
430 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
431 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
432 PI->getOperand(0).getReg() == StackPtr) {
434 *NumBytes += PI->getOperand(2).getImm();
436 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
437 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
438 PI->getOperand(0).getReg() == StackPtr) {
440 *NumBytes -= PI->getOperand(2).getImm();
445 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
447 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
448 MachineBasicBlock::iterator &MBBI,
449 unsigned StackPtr, uint64_t *NumBytes = NULL) {
452 if (MBBI == MBB.end()) return;
454 MachineBasicBlock::iterator NI = next(MBBI);
455 if (NI == MBB.end()) return;
457 unsigned Opc = NI->getOpcode();
458 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
459 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
460 NI->getOperand(0).getReg() == StackPtr) {
462 *NumBytes -= NI->getOperand(2).getImm();
465 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
466 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
467 NI->getOperand(0).getReg() == StackPtr) {
469 *NumBytes += NI->getOperand(2).getImm();
475 /// mergeSPUpdates - Checks the instruction before/after the passed
476 /// instruction. If it is an ADD/SUB instruction it is deleted
477 /// argument and the stack adjustment is returned as a positive value for ADD
478 /// and a negative for SUB.
479 static int mergeSPUpdates(MachineBasicBlock &MBB,
480 MachineBasicBlock::iterator &MBBI,
482 bool doMergeWithPrevious) {
484 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
485 (!doMergeWithPrevious && MBBI == MBB.end()))
490 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
491 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
492 unsigned Opc = PI->getOpcode();
493 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
494 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
495 PI->getOperand(0).getReg() == StackPtr){
496 Offset += PI->getOperand(2).getImm();
498 if (!doMergeWithPrevious) MBBI = NI;
499 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
500 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
501 PI->getOperand(0).getReg() == StackPtr) {
502 Offset -= PI->getOperand(2).getImm();
504 if (!doMergeWithPrevious) MBBI = NI;
510 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
511 unsigned FrameLabelId,
512 unsigned ReadyLabelId) const {
513 MachineFrameInfo *MFI = MF.getFrameInfo();
514 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
518 uint64_t StackSize = MFI->getStackSize();
519 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
520 const TargetData *TD = MF.getTarget().getTargetData();
522 // Calculate amount of bytes used for return address storing
524 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
525 TargetFrameInfo::StackGrowsUp ?
526 TD->getPointerSize() : -TD->getPointerSize());
529 // Show update of SP.
532 MachineLocation SPDst(MachineLocation::VirtualFP);
533 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
534 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
536 MachineLocation SPDst(MachineLocation::VirtualFP);
537 MachineLocation SPSrc(MachineLocation::VirtualFP,
538 -StackSize+stackGrowth);
539 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
542 //FIXME: Verify & implement for FP
543 MachineLocation SPDst(StackPtr);
544 MachineLocation SPSrc(StackPtr, stackGrowth);
545 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
548 // Add callee saved registers to move list.
549 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
551 // FIXME: This is dirty hack. The code itself is pretty mess right now.
552 // It should be rewritten from scratch and generalized sometimes.
554 // Determine maximum offset (minumum due to stack growth)
555 int64_t MaxOffset = 0;
556 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
557 MaxOffset = std::min(MaxOffset,
558 MFI->getObjectOffset(CSI[I].getFrameIdx()));
561 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
562 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
563 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
564 unsigned Reg = CSI[I].getReg();
565 Offset = (MaxOffset-Offset+saveAreaOffset);
566 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
567 MachineLocation CSSrc(Reg);
568 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
573 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
574 MachineLocation FPSrc(FramePtr);
575 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
578 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
579 MachineLocation FPSrc(MachineLocation::VirtualFP);
580 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
584 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
585 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
586 MachineFrameInfo *MFI = MF.getFrameInfo();
587 const Function* Fn = MF.getFunction();
588 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
589 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
590 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
591 MachineBasicBlock::iterator MBBI = MBB.begin();
592 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
593 !Fn->doesNotThrow() ||
594 UnwindTablesMandatory;
595 // Prepare for frame info.
596 unsigned FrameLabelId = 0;
598 // Get the number of bytes to allocate from the FrameInfo.
599 uint64_t StackSize = MFI->getStackSize();
600 // Add RETADDR move area to callee saved frame size.
601 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
602 if (TailCallReturnAddrDelta < 0)
603 X86FI->setCalleeSavedFrameSize(
604 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
605 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
607 // Insert stack pointer adjustment for later moving of return addr. Only
608 // applies to tail call optimized functions where the callee argument stack
609 // size is bigger than the callers.
610 if (TailCallReturnAddrDelta < 0) {
611 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
612 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
616 // Get the offset of the stack slot for the EBP register... which is
617 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
618 // Update the frame offset adjustment.
619 MFI->setOffsetAdjustment(SlotSize-NumBytes);
621 // Save EBP into the appropriate stack slot...
622 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
624 NumBytes -= SlotSize;
626 if (needsFrameMoves) {
627 // Mark effective beginning of when frame pointer becomes valid.
628 FrameLabelId = MMI->NextLabelID();
629 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
632 // Update EBP with the new base value...
633 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
637 unsigned ReadyLabelId = 0;
638 if (needsFrameMoves) {
639 // Mark effective beginning of when frame pointer is ready.
640 ReadyLabelId = MMI->NextLabelID();
641 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
644 // Skip the callee-saved push instructions.
645 while (MBBI != MBB.end() &&
646 (MBBI->getOpcode() == X86::PUSH32r ||
647 MBBI->getOpcode() == X86::PUSH64r))
650 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
651 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
652 // Check, whether EAX is livein for this function
653 bool isEAXAlive = false;
654 for (MachineRegisterInfo::livein_iterator
655 II = MF.getRegInfo().livein_begin(),
656 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
657 unsigned Reg = II->first;
658 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
659 Reg == X86::AH || Reg == X86::AL);
662 // Function prologue calls _alloca to probe the stack when allocating
663 // more than 4k bytes in one go. Touching the stack at 4K increments is
664 // necessary to ensure that the guard pages used by the OS virtual memory
665 // manager are allocated in correct sequence.
667 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
668 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
669 .addExternalSymbol("_alloca");
672 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
673 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
674 // allocated bytes for EAX.
675 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
676 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
677 .addExternalSymbol("_alloca");
679 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
680 StackPtr, NumBytes-4);
681 MBB.insert(MBBI, MI);
684 // If there is an SUB32ri of ESP immediately before this instruction,
685 // merge the two. This can be the case when tail call elimination is
686 // enabled and the callee has more arguments then the caller.
687 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
688 // If there is an ADD32ri or SUB32ri of ESP immediately after this
689 // instruction, merge the two instructions.
690 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
693 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
698 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
700 // If it's main() on Cygwin\Mingw32 we should align stack as well
701 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
702 Subtarget->isTargetCygMing()) {
703 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
704 .addReg(X86::ESP).addImm(-StackAlign);
707 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
708 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
712 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
713 MachineBasicBlock &MBB) const {
714 const MachineFrameInfo *MFI = MF.getFrameInfo();
715 const Function* Fn = MF.getFunction();
716 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
717 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
718 MachineBasicBlock::iterator MBBI = prior(MBB.end());
719 unsigned RetOpcode = MBBI->getOpcode();
724 case X86::TCRETURNdi:
725 case X86::TCRETURNri:
726 case X86::TCRETURNri64:
727 case X86::TCRETURNdi64:
731 case X86::TAILJMPm: break; // These are ok
733 assert(0 && "Can only insert epilog into returning blocks");
736 // Get the number of bytes to allocate from the FrameInfo
737 uint64_t StackSize = MFI->getStackSize();
738 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
739 uint64_t NumBytes = StackSize - CSSize;
743 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
744 NumBytes -= SlotSize;
747 // Skip the callee-saved pop instructions.
748 while (MBBI != MBB.begin()) {
749 MachineBasicBlock::iterator PI = prior(MBBI);
750 unsigned Opc = PI->getOpcode();
751 if (Opc != X86::POP32r && Opc != X86::POP64r &&
752 !PI->getDesc().isTerminator())
757 // If there is an ADD32ri or SUB32ri of ESP immediately before this
758 // instruction, merge the two instructions.
759 if (NumBytes || MFI->hasVarSizedObjects())
760 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
762 // If dynamic alloca is used, then reset esp to point to the last callee-saved
763 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
764 // aligned stack in the prologue, - revert stack changes back. Note: we're
765 // assuming, that frame pointer was forced for main()
766 if (MFI->hasVarSizedObjects() ||
767 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
768 Subtarget->isTargetCygMing())) {
769 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
771 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
773 MBB.insert(MBBI, MI);
775 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
781 // adjust stack pointer back: ESP += numbytes
783 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
785 // We're returning from function via eh_return.
786 if (RetOpcode == X86::EH_RETURN) {
787 MBBI = prior(MBB.end());
788 MachineOperand &DestAddr = MBBI->getOperand(0);
789 assert(DestAddr.isRegister() && "Offset should be in register!");
790 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
791 addReg(DestAddr.getReg());
792 // Tail call return: adjust the stack pointer and jump to callee
793 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
794 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
795 MBBI = prior(MBB.end());
796 MachineOperand &JumpTarget = MBBI->getOperand(0);
797 MachineOperand &StackAdjust = MBBI->getOperand(1);
798 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
800 // Adjust stack pointer.
801 int StackAdj = StackAdjust.getImm();
802 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
804 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
805 // Incoporate the retaddr area.
806 Offset = StackAdj-MaxTCDelta;
807 assert(Offset >= 0 && "Offset should never be negative");
809 // Check for possible merge with preceeding ADD instruction.
810 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
811 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
813 // Jump to label or value in register.
814 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
815 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
816 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
817 else if (RetOpcode== X86::TCRETURNri64) {
818 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
820 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
821 // Delete the pseudo instruction TCRETURN.
823 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
824 (X86FI->getTCReturnAddrDelta() < 0)) {
825 // Add the return addr area delta back since we are not tail calling.
826 int delta = -1*X86FI->getTCReturnAddrDelta();
827 MBBI = prior(MBB.end());
828 // Check for possible merge with preceeding ADD instruction.
829 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
830 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
834 unsigned X86RegisterInfo::getRARegister() const {
836 return X86::RIP; // Should have dwarf #16
838 return X86::EIP; // Should have dwarf #8
841 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
842 return hasFP(MF) ? FramePtr : StackPtr;
846 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
847 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
849 return Offset + MF.getFrameInfo()->getStackSize();
851 Offset += SlotSize; // Skip the saved EBP
852 // Skip the RETADDR move area
853 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
854 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
855 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
859 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
861 // Calculate amount of bytes used for return address storing
862 int stackGrowth = (Is64Bit ? -8 : -4);
864 // Initial state of the frame pointer is esp+4.
865 MachineLocation Dst(MachineLocation::VirtualFP);
866 MachineLocation Src(StackPtr, stackGrowth);
867 Moves.push_back(MachineMove(0, Dst, Src));
869 // Add return address to move list
870 MachineLocation CSDst(StackPtr, stackGrowth);
871 MachineLocation CSSrc(getRARegister());
872 Moves.push_back(MachineMove(0, CSDst, CSSrc));
875 unsigned X86RegisterInfo::getEHExceptionRegister() const {
876 assert(0 && "What is the exception register");
880 unsigned X86RegisterInfo::getEHHandlerRegister() const {
881 assert(0 && "What is the exception handler register");
886 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
893 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
895 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
897 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
899 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
905 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
907 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
909 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
911 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
913 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
915 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
917 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
919 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
921 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
923 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
925 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
927 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
929 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
931 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
933 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
935 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
942 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
944 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
946 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
948 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
950 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
952 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
954 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
956 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
958 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
960 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
962 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
964 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
966 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
968 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
970 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
972 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
978 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
980 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
982 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
984 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
986 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
988 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
990 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
992 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
994 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
996 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
998 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1000 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1002 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1004 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1006 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1008 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1013 default: return Reg;
1014 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1016 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1018 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1020 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1022 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1024 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1026 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1028 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1030 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1032 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1034 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1036 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1038 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1040 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1042 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1044 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1053 #include "X86GenRegisterInfo.inc"