1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/SSARegMap.h"
30 #include "llvm/Target/TargetAsmInfo.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
42 NoFusing("disable-spill-fusing",
43 cl::desc("Disable fusing of spill code into instructions"));
45 PrintFailedFusing("print-failed-fuse-candidates",
46 cl::desc("Print instructions that the allocator wants to"
47 " fuse, but the X86 backend currently can't"),
51 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
52 const TargetInstrInfo &tii)
53 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
55 // Cache some information.
56 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
57 Is64Bit = Subtarget->is64Bit();
58 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 SmallVector<unsigned,16> AmbEntries;
70 static const unsigned OpTbl2Addr[][2] = {
71 { X86::ADC32ri, X86::ADC32mi },
72 { X86::ADC32ri8, X86::ADC32mi8 },
73 { X86::ADC32rr, X86::ADC32mr },
74 { X86::ADC64ri32, X86::ADC64mi32 },
75 { X86::ADC64ri8, X86::ADC64mi8 },
76 { X86::ADC64rr, X86::ADC64mr },
77 { X86::ADD16ri, X86::ADD16mi },
78 { X86::ADD16ri8, X86::ADD16mi8 },
79 { X86::ADD16rr, X86::ADD16mr },
80 { X86::ADD32ri, X86::ADD32mi },
81 { X86::ADD32ri8, X86::ADD32mi8 },
82 { X86::ADD32rr, X86::ADD32mr },
83 { X86::ADD64ri32, X86::ADD64mi32 },
84 { X86::ADD64ri8, X86::ADD64mi8 },
85 { X86::ADD64rr, X86::ADD64mr },
86 { X86::ADD8ri, X86::ADD8mi },
87 { X86::ADD8rr, X86::ADD8mr },
88 { X86::AND16ri, X86::AND16mi },
89 { X86::AND16ri8, X86::AND16mi8 },
90 { X86::AND16rr, X86::AND16mr },
91 { X86::AND32ri, X86::AND32mi },
92 { X86::AND32ri8, X86::AND32mi8 },
93 { X86::AND32rr, X86::AND32mr },
94 { X86::AND64ri32, X86::AND64mi32 },
95 { X86::AND64ri8, X86::AND64mi8 },
96 { X86::AND64rr, X86::AND64mr },
97 { X86::AND8ri, X86::AND8mi },
98 { X86::AND8rr, X86::AND8mr },
99 { X86::DEC16r, X86::DEC16m },
100 { X86::DEC32r, X86::DEC32m },
101 { X86::DEC64_16r, X86::DEC64_16m },
102 { X86::DEC64_32r, X86::DEC64_32m },
103 { X86::DEC64r, X86::DEC64m },
104 { X86::DEC8r, X86::DEC8m },
105 { X86::INC16r, X86::INC16m },
106 { X86::INC32r, X86::INC32m },
107 { X86::INC64_16r, X86::INC64_16m },
108 { X86::INC64_32r, X86::INC64_32m },
109 { X86::INC64r, X86::INC64m },
110 { X86::INC8r, X86::INC8m },
111 { X86::NEG16r, X86::NEG16m },
112 { X86::NEG32r, X86::NEG32m },
113 { X86::NEG64r, X86::NEG64m },
114 { X86::NEG8r, X86::NEG8m },
115 { X86::NOT16r, X86::NOT16m },
116 { X86::NOT32r, X86::NOT32m },
117 { X86::NOT64r, X86::NOT64m },
118 { X86::NOT8r, X86::NOT8m },
119 { X86::OR16ri, X86::OR16mi },
120 { X86::OR16ri8, X86::OR16mi8 },
121 { X86::OR16rr, X86::OR16mr },
122 { X86::OR32ri, X86::OR32mi },
123 { X86::OR32ri8, X86::OR32mi8 },
124 { X86::OR32rr, X86::OR32mr },
125 { X86::OR64ri32, X86::OR64mi32 },
126 { X86::OR64ri8, X86::OR64mi8 },
127 { X86::OR64rr, X86::OR64mr },
128 { X86::OR8ri, X86::OR8mi },
129 { X86::OR8rr, X86::OR8mr },
130 { X86::ROL16r1, X86::ROL16m1 },
131 { X86::ROL16rCL, X86::ROL16mCL },
132 { X86::ROL16ri, X86::ROL16mi },
133 { X86::ROL32r1, X86::ROL32m1 },
134 { X86::ROL32rCL, X86::ROL32mCL },
135 { X86::ROL32ri, X86::ROL32mi },
136 { X86::ROL64r1, X86::ROL64m1 },
137 { X86::ROL64rCL, X86::ROL64mCL },
138 { X86::ROL64ri, X86::ROL64mi },
139 { X86::ROL8r1, X86::ROL8m1 },
140 { X86::ROL8rCL, X86::ROL8mCL },
141 { X86::ROL8ri, X86::ROL8mi },
142 { X86::ROR16r1, X86::ROR16m1 },
143 { X86::ROR16rCL, X86::ROR16mCL },
144 { X86::ROR16ri, X86::ROR16mi },
145 { X86::ROR32r1, X86::ROR32m1 },
146 { X86::ROR32rCL, X86::ROR32mCL },
147 { X86::ROR32ri, X86::ROR32mi },
148 { X86::ROR64r1, X86::ROR64m1 },
149 { X86::ROR64rCL, X86::ROR64mCL },
150 { X86::ROR64ri, X86::ROR64mi },
151 { X86::ROR8r1, X86::ROR8m1 },
152 { X86::ROR8rCL, X86::ROR8mCL },
153 { X86::ROR8ri, X86::ROR8mi },
154 { X86::SAR16r1, X86::SAR16m1 },
155 { X86::SAR16rCL, X86::SAR16mCL },
156 { X86::SAR16ri, X86::SAR16mi },
157 { X86::SAR32r1, X86::SAR32m1 },
158 { X86::SAR32rCL, X86::SAR32mCL },
159 { X86::SAR32ri, X86::SAR32mi },
160 { X86::SAR64r1, X86::SAR64m1 },
161 { X86::SAR64rCL, X86::SAR64mCL },
162 { X86::SAR64ri, X86::SAR64mi },
163 { X86::SAR8r1, X86::SAR8m1 },
164 { X86::SAR8rCL, X86::SAR8mCL },
165 { X86::SAR8ri, X86::SAR8mi },
166 { X86::SBB32ri, X86::SBB32mi },
167 { X86::SBB32ri8, X86::SBB32mi8 },
168 { X86::SBB32rr, X86::SBB32mr },
169 { X86::SBB64ri32, X86::SBB64mi32 },
170 { X86::SBB64ri8, X86::SBB64mi8 },
171 { X86::SBB64rr, X86::SBB64mr },
172 { X86::SHL16r1, X86::SHL16m1 },
173 { X86::SHL16rCL, X86::SHL16mCL },
174 { X86::SHL16ri, X86::SHL16mi },
175 { X86::SHL32r1, X86::SHL32m1 },
176 { X86::SHL32rCL, X86::SHL32mCL },
177 { X86::SHL32ri, X86::SHL32mi },
178 { X86::SHL64r1, X86::SHL64m1 },
179 { X86::SHL64rCL, X86::SHL64mCL },
180 { X86::SHL64ri, X86::SHL64mi },
181 { X86::SHL8r1, X86::SHL8m1 },
182 { X86::SHL8rCL, X86::SHL8mCL },
183 { X86::SHL8ri, X86::SHL8mi },
184 { X86::SHLD16rrCL, X86::SHLD16mrCL },
185 { X86::SHLD16rri8, X86::SHLD16mri8 },
186 { X86::SHLD32rrCL, X86::SHLD32mrCL },
187 { X86::SHLD32rri8, X86::SHLD32mri8 },
188 { X86::SHLD64rrCL, X86::SHLD64mrCL },
189 { X86::SHLD64rri8, X86::SHLD64mri8 },
190 { X86::SHR16r1, X86::SHR16m1 },
191 { X86::SHR16rCL, X86::SHR16mCL },
192 { X86::SHR16ri, X86::SHR16mi },
193 { X86::SHR32r1, X86::SHR32m1 },
194 { X86::SHR32rCL, X86::SHR32mCL },
195 { X86::SHR32ri, X86::SHR32mi },
196 { X86::SHR64r1, X86::SHR64m1 },
197 { X86::SHR64rCL, X86::SHR64mCL },
198 { X86::SHR64ri, X86::SHR64mi },
199 { X86::SHR8r1, X86::SHR8m1 },
200 { X86::SHR8rCL, X86::SHR8mCL },
201 { X86::SHR8ri, X86::SHR8mi },
202 { X86::SHRD16rrCL, X86::SHRD16mrCL },
203 { X86::SHRD16rri8, X86::SHRD16mri8 },
204 { X86::SHRD32rrCL, X86::SHRD32mrCL },
205 { X86::SHRD32rri8, X86::SHRD32mri8 },
206 { X86::SHRD64rrCL, X86::SHRD64mrCL },
207 { X86::SHRD64rri8, X86::SHRD64mri8 },
208 { X86::SUB16ri, X86::SUB16mi },
209 { X86::SUB16ri8, X86::SUB16mi8 },
210 { X86::SUB16rr, X86::SUB16mr },
211 { X86::SUB32ri, X86::SUB32mi },
212 { X86::SUB32ri8, X86::SUB32mi8 },
213 { X86::SUB32rr, X86::SUB32mr },
214 { X86::SUB64ri32, X86::SUB64mi32 },
215 { X86::SUB64ri8, X86::SUB64mi8 },
216 { X86::SUB64rr, X86::SUB64mr },
217 { X86::SUB8ri, X86::SUB8mi },
218 { X86::SUB8rr, X86::SUB8mr },
219 { X86::XOR16ri, X86::XOR16mi },
220 { X86::XOR16ri8, X86::XOR16mi8 },
221 { X86::XOR16rr, X86::XOR16mr },
222 { X86::XOR32ri, X86::XOR32mi },
223 { X86::XOR32ri8, X86::XOR32mi8 },
224 { X86::XOR32rr, X86::XOR32mr },
225 { X86::XOR64ri32, X86::XOR64mi32 },
226 { X86::XOR64ri8, X86::XOR64mi8 },
227 { X86::XOR64rr, X86::XOR64mr },
228 { X86::XOR8ri, X86::XOR8mi },
229 { X86::XOR8rr, X86::XOR8mr }
232 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
233 unsigned RegOp = OpTbl2Addr[i][0];
234 unsigned MemOp = OpTbl2Addr[i][1];
235 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp)))
236 assert(false && "Duplicated entries?");
237 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
238 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
239 std::make_pair(RegOp, AuxInfo))))
240 AmbEntries.push_back(MemOp);
243 // If the third value is 1, then it's folding either a load or a store.
244 static const unsigned OpTbl0[][3] = {
245 { X86::CALL32r, X86::CALL32m, 1 },
246 { X86::CALL64r, X86::CALL64m, 1 },
247 { X86::CMP16ri, X86::CMP16mi, 1 },
248 { X86::CMP16ri8, X86::CMP16mi8, 1 },
249 { X86::CMP32ri, X86::CMP32mi, 1 },
250 { X86::CMP32ri8, X86::CMP32mi8, 1 },
251 { X86::CMP64ri32, X86::CMP64mi32, 1 },
252 { X86::CMP64ri8, X86::CMP64mi8, 1 },
253 { X86::CMP8ri, X86::CMP8mi, 1 },
254 { X86::DIV16r, X86::DIV16m, 1 },
255 { X86::DIV32r, X86::DIV32m, 1 },
256 { X86::DIV64r, X86::DIV64m, 1 },
257 { X86::DIV8r, X86::DIV8m, 1 },
258 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
259 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
260 { X86::IDIV16r, X86::IDIV16m, 1 },
261 { X86::IDIV32r, X86::IDIV32m, 1 },
262 { X86::IDIV64r, X86::IDIV64m, 1 },
263 { X86::IDIV8r, X86::IDIV8m, 1 },
264 { X86::IMUL16r, X86::IMUL16m, 1 },
265 { X86::IMUL32r, X86::IMUL32m, 1 },
266 { X86::IMUL64r, X86::IMUL64m, 1 },
267 { X86::IMUL8r, X86::IMUL8m, 1 },
268 { X86::JMP32r, X86::JMP32m, 1 },
269 { X86::JMP64r, X86::JMP64m, 1 },
270 { X86::MOV16ri, X86::MOV16mi, 0 },
271 { X86::MOV16rr, X86::MOV16mr, 0 },
272 { X86::MOV16to16_, X86::MOV16_mr, 0 },
273 { X86::MOV32ri, X86::MOV32mi, 0 },
274 { X86::MOV32rr, X86::MOV32mr, 0 },
275 { X86::MOV32to32_, X86::MOV32_mr, 0 },
276 { X86::MOV64ri32, X86::MOV64mi32, 0 },
277 { X86::MOV64rr, X86::MOV64mr, 0 },
278 { X86::MOV8ri, X86::MOV8mi, 0 },
279 { X86::MOV8rr, X86::MOV8mr, 0 },
280 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
281 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
282 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
283 { X86::MOVPQIto64rr,X86::MOVPQIto64mr, 0 },
284 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
285 { X86::MOVSDrr, X86::MOVSDmr, 0 },
286 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
287 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
288 { X86::MOVSSrr, X86::MOVSSmr, 0 },
289 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
290 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
291 { X86::MUL16r, X86::MUL16m, 1 },
292 { X86::MUL32r, X86::MUL32m, 1 },
293 { X86::MUL64r, X86::MUL64m, 1 },
294 { X86::MUL8r, X86::MUL8m, 1 },
295 { X86::SETAEr, X86::SETAEm, 0 },
296 { X86::SETAr, X86::SETAm, 0 },
297 { X86::SETBEr, X86::SETBEm, 0 },
298 { X86::SETBr, X86::SETBm, 0 },
299 { X86::SETEr, X86::SETEm, 0 },
300 { X86::SETGEr, X86::SETGEm, 0 },
301 { X86::SETGr, X86::SETGm, 0 },
302 { X86::SETLEr, X86::SETLEm, 0 },
303 { X86::SETLr, X86::SETLm, 0 },
304 { X86::SETNEr, X86::SETNEm, 0 },
305 { X86::SETNPr, X86::SETNPm, 0 },
306 { X86::SETNSr, X86::SETNSm, 0 },
307 { X86::SETPr, X86::SETPm, 0 },
308 { X86::SETSr, X86::SETSm, 0 },
309 { X86::TAILJMPr, X86::TAILJMPm, 1 },
310 { X86::TEST16ri, X86::TEST16mi, 1 },
311 { X86::TEST32ri, X86::TEST32mi, 1 },
312 { X86::TEST64ri32, X86::TEST64mi32, 1 },
313 { X86::TEST8ri, X86::TEST8mi, 1 },
314 { X86::XCHG16rr, X86::XCHG16mr, 0 },
315 { X86::XCHG32rr, X86::XCHG32mr, 0 },
316 { X86::XCHG64rr, X86::XCHG64mr, 0 },
317 { X86::XCHG8rr, X86::XCHG8mr, 0 }
320 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
321 unsigned RegOp = OpTbl0[i][0];
322 unsigned MemOp = OpTbl0[i][1];
323 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp)))
324 assert(false && "Duplicated entries?");
325 unsigned FoldedLoad = OpTbl0[i][2];
326 // Index 0, folded load or store.
327 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
328 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
329 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
330 std::make_pair(RegOp, AuxInfo))))
331 AmbEntries.push_back(MemOp);
334 static const unsigned OpTbl1[][2] = {
335 { X86::CMP16rr, X86::CMP16rm },
336 { X86::CMP32rr, X86::CMP32rm },
337 { X86::CMP64rr, X86::CMP64rm },
338 { X86::CMP8rr, X86::CMP8rm },
339 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
340 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
341 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
342 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
343 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
344 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
345 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
346 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
347 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
348 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
349 { X86::FsMOVAPDrr, X86::MOVSDrm },
350 { X86::FsMOVAPSrr, X86::MOVSSrm },
351 { X86::IMUL16rri, X86::IMUL16rmi },
352 { X86::IMUL16rri8, X86::IMUL16rmi8 },
353 { X86::IMUL32rri, X86::IMUL32rmi },
354 { X86::IMUL32rri8, X86::IMUL32rmi8 },
355 { X86::IMUL64rri32, X86::IMUL64rmi32 },
356 { X86::IMUL64rri8, X86::IMUL64rmi8 },
357 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
358 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
359 { X86::Int_COMISDrr, X86::Int_COMISDrm },
360 { X86::Int_COMISSrr, X86::Int_COMISSrm },
361 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
362 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
363 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
364 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
365 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
366 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
367 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
368 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
369 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
370 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
371 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
372 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
373 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
374 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
375 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
376 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
377 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
378 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
379 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
380 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
381 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
382 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
383 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
384 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
385 { X86::MOV16rr, X86::MOV16rm },
386 { X86::MOV16to16_, X86::MOV16_rm },
387 { X86::MOV32rr, X86::MOV32rm },
388 { X86::MOV32to32_, X86::MOV32_rm },
389 { X86::MOV64rr, X86::MOV64rm },
390 { X86::MOV64toPQIrr, X86::MOV64toPQIrm },
391 { X86::MOV64toSDrr, X86::MOV64toSDrm },
392 { X86::MOV8rr, X86::MOV8rm },
393 { X86::MOVAPDrr, X86::MOVAPDrm },
394 { X86::MOVAPSrr, X86::MOVAPSrm },
395 { X86::MOVDDUPrr, X86::MOVDDUPrm },
396 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
397 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
398 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
399 { X86::MOVSDrr, X86::MOVSDrm },
400 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
401 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
402 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
403 { X86::MOVSSrr, X86::MOVSSrm },
404 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
405 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
406 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
407 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
408 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
409 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
410 { X86::MOVUPDrr, X86::MOVUPDrm },
411 { X86::MOVUPSrr, X86::MOVUPSrm },
412 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
413 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
414 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
415 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
416 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
417 { X86::PSHUFDri, X86::PSHUFDmi },
418 { X86::PSHUFHWri, X86::PSHUFHWmi },
419 { X86::PSHUFLWri, X86::PSHUFLWmi },
420 { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
421 { X86::RCPPSr, X86::RCPPSm },
422 { X86::RCPPSr_Int, X86::RCPPSm_Int },
423 { X86::RSQRTPSr, X86::RSQRTPSm },
424 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
425 { X86::RSQRTSSr, X86::RSQRTSSm },
426 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
427 { X86::SQRTPDr, X86::SQRTPDm },
428 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
429 { X86::SQRTPSr, X86::SQRTPSm },
430 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
431 { X86::SQRTSDr, X86::SQRTSDm },
432 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
433 { X86::SQRTSSr, X86::SQRTSSm },
434 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
435 { X86::TEST16rr, X86::TEST16rm },
436 { X86::TEST32rr, X86::TEST32rm },
437 { X86::TEST64rr, X86::TEST64rm },
438 { X86::TEST8rr, X86::TEST8rm },
439 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
440 { X86::UCOMISDrr, X86::UCOMISDrm },
441 { X86::UCOMISSrr, X86::UCOMISSrm },
442 { X86::XCHG16rr, X86::XCHG16rm },
443 { X86::XCHG32rr, X86::XCHG32rm },
444 { X86::XCHG64rr, X86::XCHG64rm },
445 { X86::XCHG8rr, X86::XCHG8rm }
448 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
449 unsigned RegOp = OpTbl1[i][0];
450 unsigned MemOp = OpTbl1[i][1];
451 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp)))
452 assert(false && "Duplicated entries?");
453 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
454 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
455 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
456 std::make_pair(RegOp, AuxInfo))))
457 AmbEntries.push_back(MemOp);
460 static const unsigned OpTbl2[][2] = {
461 { X86::ADC32rr, X86::ADC32rm },
462 { X86::ADC64rr, X86::ADC64rm },
463 { X86::ADD16rr, X86::ADD16rm },
464 { X86::ADD32rr, X86::ADD32rm },
465 { X86::ADD64rr, X86::ADD64rm },
466 { X86::ADD8rr, X86::ADD8rm },
467 { X86::ADDPDrr, X86::ADDPDrm },
468 { X86::ADDPSrr, X86::ADDPSrm },
469 { X86::ADDSDrr, X86::ADDSDrm },
470 { X86::ADDSSrr, X86::ADDSSrm },
471 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
472 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
473 { X86::AND16rr, X86::AND16rm },
474 { X86::AND32rr, X86::AND32rm },
475 { X86::AND64rr, X86::AND64rm },
476 { X86::AND8rr, X86::AND8rm },
477 { X86::ANDNPDrr, X86::ANDNPDrm },
478 { X86::ANDNPSrr, X86::ANDNPSrm },
479 { X86::ANDPDrr, X86::ANDPDrm },
480 { X86::ANDPSrr, X86::ANDPSrm },
481 { X86::CMOVA16rr, X86::CMOVA16rm },
482 { X86::CMOVA32rr, X86::CMOVA32rm },
483 { X86::CMOVA64rr, X86::CMOVA64rm },
484 { X86::CMOVAE16rr, X86::CMOVAE16rm },
485 { X86::CMOVAE32rr, X86::CMOVAE32rm },
486 { X86::CMOVAE64rr, X86::CMOVAE64rm },
487 { X86::CMOVB16rr, X86::CMOVB16rm },
488 { X86::CMOVB32rr, X86::CMOVB32rm },
489 { X86::CMOVB64rr, X86::CMOVB64rm },
490 { X86::CMOVBE16rr, X86::CMOVBE16rm },
491 { X86::CMOVBE32rr, X86::CMOVBE32rm },
492 { X86::CMOVBE64rr, X86::CMOVBE64rm },
493 { X86::CMOVE16rr, X86::CMOVE16rm },
494 { X86::CMOVE32rr, X86::CMOVE32rm },
495 { X86::CMOVE64rr, X86::CMOVE64rm },
496 { X86::CMOVG16rr, X86::CMOVG16rm },
497 { X86::CMOVG32rr, X86::CMOVG32rm },
498 { X86::CMOVG64rr, X86::CMOVG64rm },
499 { X86::CMOVGE16rr, X86::CMOVGE16rm },
500 { X86::CMOVGE32rr, X86::CMOVGE32rm },
501 { X86::CMOVGE64rr, X86::CMOVGE64rm },
502 { X86::CMOVL16rr, X86::CMOVL16rm },
503 { X86::CMOVL32rr, X86::CMOVL32rm },
504 { X86::CMOVL64rr, X86::CMOVL64rm },
505 { X86::CMOVLE16rr, X86::CMOVLE16rm },
506 { X86::CMOVLE32rr, X86::CMOVLE32rm },
507 { X86::CMOVLE64rr, X86::CMOVLE64rm },
508 { X86::CMOVNE16rr, X86::CMOVNE16rm },
509 { X86::CMOVNE32rr, X86::CMOVNE32rm },
510 { X86::CMOVNE64rr, X86::CMOVNE64rm },
511 { X86::CMOVNP16rr, X86::CMOVNP16rm },
512 { X86::CMOVNP32rr, X86::CMOVNP32rm },
513 { X86::CMOVNP64rr, X86::CMOVNP64rm },
514 { X86::CMOVNS16rr, X86::CMOVNS16rm },
515 { X86::CMOVNS32rr, X86::CMOVNS32rm },
516 { X86::CMOVNS64rr, X86::CMOVNS64rm },
517 { X86::CMOVP16rr, X86::CMOVP16rm },
518 { X86::CMOVP32rr, X86::CMOVP32rm },
519 { X86::CMOVP64rr, X86::CMOVP64rm },
520 { X86::CMOVS16rr, X86::CMOVS16rm },
521 { X86::CMOVS32rr, X86::CMOVS32rm },
522 { X86::CMOVS64rr, X86::CMOVS64rm },
523 { X86::CMPPDrri, X86::CMPPDrmi },
524 { X86::CMPPSrri, X86::CMPPSrmi },
525 { X86::CMPSDrr, X86::CMPSDrm },
526 { X86::CMPSSrr, X86::CMPSSrm },
527 { X86::DIVPDrr, X86::DIVPDrm },
528 { X86::DIVPSrr, X86::DIVPSrm },
529 { X86::DIVSDrr, X86::DIVSDrm },
530 { X86::DIVSSrr, X86::DIVSSrm },
531 { X86::HADDPDrr, X86::HADDPDrm },
532 { X86::HADDPSrr, X86::HADDPSrm },
533 { X86::HSUBPDrr, X86::HSUBPDrm },
534 { X86::HSUBPSrr, X86::HSUBPSrm },
535 { X86::IMUL16rr, X86::IMUL16rm },
536 { X86::IMUL32rr, X86::IMUL32rm },
537 { X86::IMUL64rr, X86::IMUL64rm },
538 { X86::MAXPDrr, X86::MAXPDrm },
539 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
540 { X86::MAXPSrr, X86::MAXPSrm },
541 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
542 { X86::MAXSDrr, X86::MAXSDrm },
543 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
544 { X86::MAXSSrr, X86::MAXSSrm },
545 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
546 { X86::MINPDrr, X86::MINPDrm },
547 { X86::MINPDrr_Int, X86::MINPDrm_Int },
548 { X86::MINPSrr, X86::MINPSrm },
549 { X86::MINPSrr_Int, X86::MINPSrm_Int },
550 { X86::MINSDrr, X86::MINSDrm },
551 { X86::MINSDrr_Int, X86::MINSDrm_Int },
552 { X86::MINSSrr, X86::MINSSrm },
553 { X86::MINSSrr_Int, X86::MINSSrm_Int },
554 { X86::MULPDrr, X86::MULPDrm },
555 { X86::MULPSrr, X86::MULPSrm },
556 { X86::MULSDrr, X86::MULSDrm },
557 { X86::MULSSrr, X86::MULSSrm },
558 { X86::OR16rr, X86::OR16rm },
559 { X86::OR32rr, X86::OR32rm },
560 { X86::OR64rr, X86::OR64rm },
561 { X86::OR8rr, X86::OR8rm },
562 { X86::ORPDrr, X86::ORPDrm },
563 { X86::ORPSrr, X86::ORPSrm },
564 { X86::PACKSSDWrr, X86::PACKSSDWrm },
565 { X86::PACKSSWBrr, X86::PACKSSWBrm },
566 { X86::PACKUSWBrr, X86::PACKUSWBrm },
567 { X86::PADDBrr, X86::PADDBrm },
568 { X86::PADDDrr, X86::PADDDrm },
569 { X86::PADDQrr, X86::PADDQrm },
570 { X86::PADDSBrr, X86::PADDSBrm },
571 { X86::PADDSWrr, X86::PADDSWrm },
572 { X86::PADDWrr, X86::PADDWrm },
573 { X86::PANDNrr, X86::PANDNrm },
574 { X86::PANDrr, X86::PANDrm },
575 { X86::PAVGBrr, X86::PAVGBrm },
576 { X86::PAVGWrr, X86::PAVGWrm },
577 { X86::PCMPEQBrr, X86::PCMPEQBrm },
578 { X86::PCMPEQDrr, X86::PCMPEQDrm },
579 { X86::PCMPEQWrr, X86::PCMPEQWrm },
580 { X86::PCMPGTBrr, X86::PCMPGTBrm },
581 { X86::PCMPGTDrr, X86::PCMPGTDrm },
582 { X86::PCMPGTWrr, X86::PCMPGTWrm },
583 { X86::PINSRWrri, X86::PINSRWrmi },
584 { X86::PMADDWDrr, X86::PMADDWDrm },
585 { X86::PMAXSWrr, X86::PMAXSWrm },
586 { X86::PMAXUBrr, X86::PMAXUBrm },
587 { X86::PMINSWrr, X86::PMINSWrm },
588 { X86::PMINUBrr, X86::PMINUBrm },
589 { X86::PMULHUWrr, X86::PMULHUWrm },
590 { X86::PMULHWrr, X86::PMULHWrm },
591 { X86::PMULLWrr, X86::PMULLWrm },
592 { X86::PMULUDQrr, X86::PMULUDQrm },
593 { X86::PORrr, X86::PORrm },
594 { X86::PSADBWrr, X86::PSADBWrm },
595 { X86::PSLLDrr, X86::PSLLDrm },
596 { X86::PSLLQrr, X86::PSLLQrm },
597 { X86::PSLLWrr, X86::PSLLWrm },
598 { X86::PSRADrr, X86::PSRADrm },
599 { X86::PSRAWrr, X86::PSRAWrm },
600 { X86::PSRLDrr, X86::PSRLDrm },
601 { X86::PSRLQrr, X86::PSRLQrm },
602 { X86::PSRLWrr, X86::PSRLWrm },
603 { X86::PSUBBrr, X86::PSUBBrm },
604 { X86::PSUBDrr, X86::PSUBDrm },
605 { X86::PSUBSBrr, X86::PSUBSBrm },
606 { X86::PSUBSWrr, X86::PSUBSWrm },
607 { X86::PSUBWrr, X86::PSUBWrm },
608 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
609 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
610 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
611 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
612 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
613 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
614 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
615 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
616 { X86::PXORrr, X86::PXORrm },
617 { X86::SBB32rr, X86::SBB32rm },
618 { X86::SBB64rr, X86::SBB64rm },
619 { X86::SHUFPDrri, X86::SHUFPDrmi },
620 { X86::SHUFPSrri, X86::SHUFPSrmi },
621 { X86::SUB16rr, X86::SUB16rm },
622 { X86::SUB32rr, X86::SUB32rm },
623 { X86::SUB64rr, X86::SUB64rm },
624 { X86::SUB8rr, X86::SUB8rm },
625 { X86::SUBPDrr, X86::SUBPDrm },
626 { X86::SUBPSrr, X86::SUBPSrm },
627 { X86::SUBSDrr, X86::SUBSDrm },
628 { X86::SUBSSrr, X86::SUBSSrm },
629 // FIXME: TEST*rr -> swapped operand of TEST*mr.
630 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
631 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
632 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
633 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
634 { X86::XOR16rr, X86::XOR16rm },
635 { X86::XOR32rr, X86::XOR32rm },
636 { X86::XOR64rr, X86::XOR64rm },
637 { X86::XOR8rr, X86::XOR8rm },
638 { X86::XORPDrr, X86::XORPDrm },
639 { X86::XORPSrr, X86::XORPSrm }
642 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
643 unsigned RegOp = OpTbl2[i][0];
644 unsigned MemOp = OpTbl2[i][1];
645 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp)))
646 assert(false && "Duplicated entries?");
647 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
648 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
649 std::make_pair(RegOp, AuxInfo))))
650 AmbEntries.push_back(MemOp);
653 // Remove ambiguous entries.
654 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
657 // getDwarfRegNum - This function maps LLVM register identifiers to the
658 // Dwarf specific numbering, used in debug info and exception tables.
659 // The registers are given "basic" dwarf numbers in the .td files,
660 // which are collected by TableGen into X86GenRegisterInfo::getDwarfRegNum.
661 // This wrapper allows for target-specific overrides.
662 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo) const {
663 int n = X86GenRegisterInfo::getDwarfRegNum(RegNo);
664 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
665 if (Subtarget->isDarwin) {
666 // ESP and EBP are switched.
673 // getX86RegNum - This function maps LLVM register identifiers to their X86
674 // specific numbering, which is used in various places encoding instructions.
676 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
678 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
679 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
680 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
681 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
682 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
684 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
686 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
688 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
691 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
693 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
695 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
697 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
699 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
701 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
703 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
705 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
708 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
709 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
710 return RegNo-X86::ST0;
712 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
713 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
714 return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM0);
715 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
716 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
717 return getDwarfRegNum(RegNo) - getDwarfRegNum(X86::XMM8);
720 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
721 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
726 bool X86RegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
727 MachineBasicBlock::iterator MI,
728 const std::vector<CalleeSavedInfo> &CSI) const {
732 MachineFunction &MF = *MBB.getParent();
733 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
734 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
735 unsigned Opc = Is64Bit ? X86::PUSH64r : X86::PUSH32r;
736 for (unsigned i = CSI.size(); i != 0; --i) {
737 unsigned Reg = CSI[i-1].getReg();
738 // Add the callee-saved register as live-in. It's killed at the spill.
740 BuildMI(MBB, MI, TII.get(Opc)).addReg(Reg);
745 bool X86RegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
746 MachineBasicBlock::iterator MI,
747 const std::vector<CalleeSavedInfo> &CSI) const {
751 unsigned Opc = Is64Bit ? X86::POP64r : X86::POP32r;
752 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
753 unsigned Reg = CSI[i].getReg();
754 BuildMI(MBB, MI, TII.get(Opc), Reg);
759 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
760 MachineOperand &MO) {
762 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
763 else if (MO.isImmediate())
764 MIB = MIB.addImm(MO.getImm());
765 else if (MO.isFrameIndex())
766 MIB = MIB.addFrameIndex(MO.getFrameIndex());
767 else if (MO.isGlobalAddress())
768 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
769 else if (MO.isConstantPoolIndex())
770 MIB = MIB.addConstantPoolIndex(MO.getConstantPoolIndex(), MO.getOffset());
771 else if (MO.isJumpTableIndex())
772 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
773 else if (MO.isExternalSymbol())
774 MIB = MIB.addExternalSymbol(MO.getSymbolName());
776 assert(0 && "Unknown operand for X86InstrAddOperand!");
781 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
782 unsigned StackAlign) {
784 if (RC == &X86::GR64RegClass) {
786 } else if (RC == &X86::GR32RegClass) {
788 } else if (RC == &X86::GR16RegClass) {
790 } else if (RC == &X86::GR8RegClass) {
792 } else if (RC == &X86::GR32_RegClass) {
794 } else if (RC == &X86::GR16_RegClass) {
796 } else if (RC == &X86::RFP80RegClass) {
797 Opc = X86::ST_FpP80m; // pops
798 } else if (RC == &X86::RFP64RegClass) {
800 } else if (RC == &X86::RFP32RegClass) {
802 } else if (RC == &X86::FR32RegClass) {
804 } else if (RC == &X86::FR64RegClass) {
806 } else if (RC == &X86::VR128RegClass) {
807 // FIXME: Use movaps once we are capable of selectively
808 // aligning functions that spill SSE registers on 16-byte boundaries.
809 Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
810 } else if (RC == &X86::VR64RegClass) {
811 Opc = X86::MMX_MOVQ64mr;
813 assert(0 && "Unknown regclass");
820 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
821 MachineBasicBlock::iterator MI,
822 unsigned SrcReg, int FrameIdx,
823 const TargetRegisterClass *RC) const {
824 unsigned Opc = getStoreRegOpcode(RC, StackAlign);
825 addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
826 .addReg(SrcReg, false, false, true);
829 void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
830 SmallVectorImpl<MachineOperand> &Addr,
831 const TargetRegisterClass *RC,
832 SmallVectorImpl<MachineInstr*> &NewMIs) const {
833 unsigned Opc = getStoreRegOpcode(RC, StackAlign);
834 MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
835 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
836 MIB = X86InstrAddOperand(MIB, Addr[i]);
837 MIB.addReg(SrcReg, false, false, true);
838 NewMIs.push_back(MIB);
841 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
842 unsigned StackAlign) {
844 if (RC == &X86::GR64RegClass) {
846 } else if (RC == &X86::GR32RegClass) {
848 } else if (RC == &X86::GR16RegClass) {
850 } else if (RC == &X86::GR8RegClass) {
852 } else if (RC == &X86::GR32_RegClass) {
854 } else if (RC == &X86::GR16_RegClass) {
856 } else if (RC == &X86::RFP80RegClass) {
858 } else if (RC == &X86::RFP64RegClass) {
860 } else if (RC == &X86::RFP32RegClass) {
862 } else if (RC == &X86::FR32RegClass) {
864 } else if (RC == &X86::FR64RegClass) {
866 } else if (RC == &X86::VR128RegClass) {
867 // FIXME: Use movaps once we are capable of selectively
868 // aligning functions that spill SSE registers on 16-byte boundaries.
869 Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
870 } else if (RC == &X86::VR64RegClass) {
871 Opc = X86::MMX_MOVQ64rm;
873 assert(0 && "Unknown regclass");
880 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
881 MachineBasicBlock::iterator MI,
882 unsigned DestReg, int FrameIdx,
883 const TargetRegisterClass *RC) const{
884 unsigned Opc = getLoadRegOpcode(RC, StackAlign);
885 addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
888 void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
889 SmallVectorImpl<MachineOperand> &Addr,
890 const TargetRegisterClass *RC,
891 SmallVectorImpl<MachineInstr*> &NewMIs) const {
892 unsigned Opc = getLoadRegOpcode(RC, StackAlign);
893 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
894 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
895 MIB = X86InstrAddOperand(MIB, Addr[i]);
896 NewMIs.push_back(MIB);
899 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
900 MachineBasicBlock::iterator MI,
901 unsigned DestReg, unsigned SrcReg,
902 const TargetRegisterClass *DestRC,
903 const TargetRegisterClass *SrcRC) const {
904 if (DestRC != SrcRC) {
905 // Moving EFLAGS to / from another register requires a push and a pop.
906 if (SrcRC == &X86::CCRRegClass) {
907 assert(SrcReg == X86::EFLAGS);
908 if (DestRC == &X86::GR64RegClass) {
909 BuildMI(MBB, MI, TII.get(X86::PUSHFQ));
910 BuildMI(MBB, MI, TII.get(X86::POP64r), DestReg);
912 } else if (DestRC == &X86::GR32RegClass) {
913 BuildMI(MBB, MI, TII.get(X86::PUSHFD));
914 BuildMI(MBB, MI, TII.get(X86::POP32r), DestReg);
917 } else if (DestRC == &X86::CCRRegClass) {
918 assert(DestReg == X86::EFLAGS);
919 if (SrcRC == &X86::GR64RegClass) {
920 BuildMI(MBB, MI, TII.get(X86::PUSH64r)).addReg(SrcReg);
921 BuildMI(MBB, MI, TII.get(X86::POPFQ));
923 } else if (SrcRC == &X86::GR32RegClass) {
924 BuildMI(MBB, MI, TII.get(X86::PUSH32r)).addReg(SrcReg);
925 BuildMI(MBB, MI, TII.get(X86::POPFD));
929 cerr << "Not yet supported!";
934 if (DestRC == &X86::GR64RegClass) {
936 } else if (DestRC == &X86::GR32RegClass) {
938 } else if (DestRC == &X86::GR16RegClass) {
940 } else if (DestRC == &X86::GR8RegClass) {
942 } else if (DestRC == &X86::GR32_RegClass) {
944 } else if (DestRC == &X86::GR16_RegClass) {
946 } else if (DestRC == &X86::RFP32RegClass) {
947 Opc = X86::MOV_Fp3232;
948 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
949 Opc = X86::MOV_Fp6464;
950 } else if (DestRC == &X86::RFP80RegClass) {
951 Opc = X86::MOV_Fp8080;
952 } else if (DestRC == &X86::FR32RegClass) {
953 Opc = X86::FsMOVAPSrr;
954 } else if (DestRC == &X86::FR64RegClass) {
955 Opc = X86::FsMOVAPDrr;
956 } else if (DestRC == &X86::VR128RegClass) {
958 } else if (DestRC == &X86::VR64RegClass) {
959 Opc = X86::MMX_MOVQ64rr;
961 assert(0 && "Unknown regclass");
964 BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
967 const TargetRegisterClass *
968 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
969 if (RC == &X86::CCRRegClass)
971 return &X86::GR64RegClass;
973 return &X86::GR32RegClass;
977 void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
978 MachineBasicBlock::iterator I,
980 const MachineInstr *Orig) const {
981 // MOV32r0 etc. are implemented with xor which clobbers condition code.
982 // Re-materialize them as movri instructions to avoid side effects.
983 switch (Orig->getOpcode()) {
985 BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
988 BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
991 BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
994 BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
997 MachineInstr *MI = Orig->clone();
998 MI->getOperand(0).setReg(DestReg);
1005 static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
1006 SmallVector<MachineOperand,4> &MOs,
1007 MachineInstr *MI, const TargetInstrInfo &TII) {
1008 // Create the base instruction with the memory operand as the first part.
1009 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1010 MachineInstrBuilder MIB(NewMI);
1011 unsigned NumAddrOps = MOs.size();
1012 for (unsigned i = 0; i != NumAddrOps; ++i)
1013 MIB = X86InstrAddOperand(MIB, MOs[i]);
1014 if (NumAddrOps < 4) // FrameIndex only
1015 MIB.addImm(1).addReg(0).addImm(0);
1017 // Loop over the rest of the ri operands, converting them over.
1018 unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
1019 for (unsigned i = 0; i != NumOps; ++i) {
1020 MachineOperand &MO = MI->getOperand(i+2);
1021 MIB = X86InstrAddOperand(MIB, MO);
1023 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
1024 MachineOperand &MO = MI->getOperand(i);
1025 MIB = X86InstrAddOperand(MIB, MO);
1030 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
1031 SmallVector<MachineOperand,4> &MOs,
1032 MachineInstr *MI, const TargetInstrInfo &TII) {
1033 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1034 MachineInstrBuilder MIB(NewMI);
1036 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1037 MachineOperand &MO = MI->getOperand(i);
1039 assert(MO.isRegister() && "Expected to fold into reg operand!");
1040 unsigned NumAddrOps = MOs.size();
1041 for (unsigned i = 0; i != NumAddrOps; ++i)
1042 MIB = X86InstrAddOperand(MIB, MOs[i]);
1043 if (NumAddrOps < 4) // FrameIndex only
1044 MIB.addImm(1).addReg(0).addImm(0);
1046 MIB = X86InstrAddOperand(MIB, MO);
1052 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
1053 SmallVector<MachineOperand,4> &MOs,
1055 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
1057 unsigned NumAddrOps = MOs.size();
1058 for (unsigned i = 0; i != NumAddrOps; ++i)
1059 MIB = X86InstrAddOperand(MIB, MOs[i]);
1060 if (NumAddrOps < 4) // FrameIndex only
1061 MIB.addImm(1).addReg(0).addImm(0);
1062 return MIB.addImm(0);
1066 X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
1067 SmallVector<MachineOperand,4> &MOs) const {
1068 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1069 bool isTwoAddrFold = false;
1070 unsigned NumOps = TII.getNumOperands(MI->getOpcode());
1071 bool isTwoAddr = NumOps > 1 &&
1072 MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
1074 MachineInstr *NewMI = NULL;
1075 // Folding a memory location into the two-address part of a two-address
1076 // instruction is different than folding it other places. It requires
1077 // replacing the *two* registers with the memory location.
1078 if (isTwoAddr && NumOps >= 2 && i < 2 &&
1079 MI->getOperand(0).isRegister() &&
1080 MI->getOperand(1).isRegister() &&
1081 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
1082 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1083 isTwoAddrFold = true;
1084 } else if (i == 0) { // If operand 0
1085 if (MI->getOpcode() == X86::MOV16r0)
1086 NewMI = MakeM0Inst(TII, X86::MOV16mi, MOs, MI);
1087 else if (MI->getOpcode() == X86::MOV32r0)
1088 NewMI = MakeM0Inst(TII, X86::MOV32mi, MOs, MI);
1089 else if (MI->getOpcode() == X86::MOV64r0)
1090 NewMI = MakeM0Inst(TII, X86::MOV64mi32, MOs, MI);
1091 else if (MI->getOpcode() == X86::MOV8r0)
1092 NewMI = MakeM0Inst(TII, X86::MOV8mi, MOs, MI);
1094 NewMI->copyKillDeadInfo(MI);
1098 OpcodeTablePtr = &RegOp2MemOpTable0;
1099 } else if (i == 1) {
1100 OpcodeTablePtr = &RegOp2MemOpTable1;
1101 } else if (i == 2) {
1102 OpcodeTablePtr = &RegOp2MemOpTable2;
1105 // If table selected...
1106 if (OpcodeTablePtr) {
1107 // Find the Opcode to fuse
1108 DenseMap<unsigned*, unsigned>::iterator I =
1109 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
1110 if (I != OpcodeTablePtr->end()) {
1112 NewMI = FuseTwoAddrInst(I->second, MOs, MI, TII);
1114 NewMI = FuseInst(I->second, i, MOs, MI, TII);
1115 NewMI->copyKillDeadInfo(MI);
1121 if (PrintFailedFusing)
1122 cerr << "We failed to fuse ("
1123 << ((i == 1) ? "r" : "s") << "): " << *MI;
1128 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
1129 int FrameIndex) const {
1130 // Check switch flag
1131 if (NoFusing) return NULL;
1132 SmallVector<MachineOperand,4> MOs;
1133 MOs.push_back(MachineOperand::CreateFrameIndex(FrameIndex));
1134 return foldMemoryOperand(MI, OpNum, MOs);
1137 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
1138 MachineInstr *LoadMI) const {
1139 // Check switch flag
1140 if (NoFusing) return NULL;
1141 SmallVector<MachineOperand,4> MOs;
1142 unsigned NumOps = TII.getNumOperands(LoadMI->getOpcode());
1143 for (unsigned i = NumOps - 4; i != NumOps; ++i)
1144 MOs.push_back(LoadMI->getOperand(i));
1145 return foldMemoryOperand(MI, OpNum, MOs);
1148 unsigned X86RegisterInfo::getOpcodeAfterMemoryFold(unsigned Opc,
1149 unsigned OpNum) const {
1150 // Check switch flag
1151 if (NoFusing) return 0;
1152 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1153 unsigned NumOps = TII.getNumOperands(Opc);
1154 bool isTwoAddr = NumOps > 1 &&
1155 TII.getOperandConstraint(Opc, 1, TOI::TIED_TO) != -1;
1157 // Folding a memory location into the two-address part of a two-address
1158 // instruction is different than folding it other places. It requires
1159 // replacing the *two* registers with the memory location.
1160 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
1161 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1162 } else if (OpNum == 0) { // If operand 0
1165 return X86::MOV16mi;
1167 return X86::MOV32mi;
1169 return X86::MOV64mi32;
1174 OpcodeTablePtr = &RegOp2MemOpTable0;
1175 } else if (OpNum == 1) {
1176 OpcodeTablePtr = &RegOp2MemOpTable1;
1177 } else if (OpNum == 2) {
1178 OpcodeTablePtr = &RegOp2MemOpTable2;
1181 if (OpcodeTablePtr) {
1182 // Find the Opcode to fuse
1183 DenseMap<unsigned*, unsigned>::iterator I =
1184 OpcodeTablePtr->find((unsigned*)Opc);
1185 if (I != OpcodeTablePtr->end())
1191 bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
1192 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
1193 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1194 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
1195 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
1196 if (I == MemOp2RegOpTable.end())
1198 unsigned Opc = I->second.first;
1199 unsigned Index = I->second.second & 0xf;
1200 bool FoldedLoad = I->second.second & (1 << 4);
1201 bool FoldedStore = I->second.second & (1 << 5);
1202 if (UnfoldLoad && !FoldedLoad)
1204 UnfoldLoad &= FoldedLoad;
1205 if (UnfoldStore && !FoldedStore)
1207 UnfoldStore &= FoldedStore;
1209 const TargetInstrDescriptor &TID = TII.get(Opc);
1210 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1211 const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1212 ? TII.getPointerRegClass() : getRegClass(TOI.RegClass);
1213 SmallVector<MachineOperand,4> AddrOps;
1214 SmallVector<MachineOperand,2> BeforeOps;
1215 SmallVector<MachineOperand,2> AfterOps;
1216 SmallVector<MachineOperand,4> ImpOps;
1217 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1218 MachineOperand &Op = MI->getOperand(i);
1219 if (i >= Index && i < Index+4)
1220 AddrOps.push_back(Op);
1221 else if (Op.isRegister() && Op.isImplicit())
1222 ImpOps.push_back(Op);
1224 BeforeOps.push_back(Op);
1226 AfterOps.push_back(Op);
1229 // Emit the load instruction.
1231 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
1233 // Address operands cannot be marked isKill.
1234 for (unsigned i = 1; i != 5; ++i) {
1235 MachineOperand &MO = NewMIs[0]->getOperand(i);
1236 if (MO.isRegister())
1242 // Emit the data processing instruction.
1243 MachineInstr *DataMI = new MachineInstr(TID, true);
1244 MachineInstrBuilder MIB(DataMI);
1247 MIB.addReg(Reg, true);
1248 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
1249 MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
1252 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
1253 MIB = X86InstrAddOperand(MIB, AfterOps[i]);
1254 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
1255 MachineOperand &MO = ImpOps[i];
1256 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
1258 NewMIs.push_back(MIB);
1260 // Emit the store instruction.
1262 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
1263 const TargetRegisterClass *DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1264 ? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass);
1265 storeRegToAddr(MF, Reg, AddrOps, DstRC, NewMIs);
1273 X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1274 SmallVectorImpl<SDNode*> &NewNodes) const {
1275 if (!N->isTargetOpcode())
1278 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
1279 MemOp2RegOpTable.find((unsigned*)N->getTargetOpcode());
1280 if (I == MemOp2RegOpTable.end())
1282 unsigned Opc = I->second.first;
1283 unsigned Index = I->second.second & 0xf;
1284 bool FoldedLoad = I->second.second & (1 << 4);
1285 bool FoldedStore = I->second.second & (1 << 5);
1286 const TargetInstrDescriptor &TID = TII.get(Opc);
1287 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1288 const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1289 ? TII.getPointerRegClass() : getRegClass(TOI.RegClass);
1290 std::vector<SDOperand> AddrOps;
1291 std::vector<SDOperand> BeforeOps;
1292 std::vector<SDOperand> AfterOps;
1293 unsigned NumOps = N->getNumOperands();
1294 for (unsigned i = 0; i != NumOps-1; ++i) {
1295 SDOperand Op = N->getOperand(i);
1296 if (i >= Index && i < Index+4)
1297 AddrOps.push_back(Op);
1299 BeforeOps.push_back(Op);
1301 AfterOps.push_back(Op);
1303 SDOperand Chain = N->getOperand(NumOps-1);
1304 AddrOps.push_back(Chain);
1306 // Emit the load instruction.
1309 MVT::ValueType VT = *RC->vt_begin();
1310 Load = DAG.getTargetNode(getLoadRegOpcode(RC, StackAlign), VT, MVT::Other,
1311 &AddrOps[0], AddrOps.size());
1312 NewNodes.push_back(Load);
1315 // Emit the data processing instruction.
1316 std::vector<MVT::ValueType> VTs;
1317 const TargetRegisterClass *DstRC = 0;
1318 if (TID.numDefs > 0) {
1319 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
1320 DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
1321 ? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass);
1322 VTs.push_back(*DstRC->vt_begin());
1324 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
1325 MVT::ValueType VT = N->getValueType(i);
1326 if (VT != MVT::Other && i >= TID.numDefs)
1330 BeforeOps.push_back(SDOperand(Load, 0));
1331 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
1332 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
1333 NewNodes.push_back(NewNode);
1335 // Emit the store instruction.
1338 AddrOps.push_back(SDOperand(NewNode, 0));
1339 AddrOps.push_back(Chain);
1340 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, StackAlign),
1341 MVT::Other, &AddrOps[0], AddrOps.size());
1342 NewNodes.push_back(Store);
1348 unsigned X86RegisterInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
1349 bool UnfoldLoad, bool UnfoldStore) const {
1350 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
1351 MemOp2RegOpTable.find((unsigned*)Opc);
1352 if (I == MemOp2RegOpTable.end())
1354 bool FoldedLoad = I->second.second & (1 << 4);
1355 bool FoldedStore = I->second.second & (1 << 5);
1356 if (UnfoldLoad && !FoldedLoad)
1358 if (UnfoldStore && !FoldedStore)
1360 return I->second.first;
1364 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
1365 static const unsigned CalleeSavedRegs32Bit[] = {
1366 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
1369 static const unsigned CalleeSavedRegs32EHRet[] = {
1370 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
1373 static const unsigned CalleeSavedRegs64Bit[] = {
1374 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1378 return CalleeSavedRegs64Bit;
1381 MachineFrameInfo *MFI = MF->getFrameInfo();
1382 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1383 if (MMI && MMI->callsEHReturn())
1384 return CalleeSavedRegs32EHRet;
1386 return CalleeSavedRegs32Bit;
1390 const TargetRegisterClass* const*
1391 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
1392 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
1393 &X86::GR32RegClass, &X86::GR32RegClass,
1394 &X86::GR32RegClass, &X86::GR32RegClass, 0
1396 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
1397 &X86::GR32RegClass, &X86::GR32RegClass,
1398 &X86::GR32RegClass, &X86::GR32RegClass,
1399 &X86::GR32RegClass, &X86::GR32RegClass, 0
1401 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
1402 &X86::GR64RegClass, &X86::GR64RegClass,
1403 &X86::GR64RegClass, &X86::GR64RegClass,
1404 &X86::GR64RegClass, &X86::GR64RegClass, 0
1408 return CalleeSavedRegClasses64Bit;
1411 MachineFrameInfo *MFI = MF->getFrameInfo();
1412 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1413 if (MMI && MMI->callsEHReturn())
1414 return CalleeSavedRegClasses32EHRet;
1416 return CalleeSavedRegClasses32Bit;
1421 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
1422 BitVector Reserved(getNumRegs());
1423 Reserved.set(X86::RSP);
1424 Reserved.set(X86::ESP);
1425 Reserved.set(X86::SP);
1426 Reserved.set(X86::SPL);
1428 Reserved.set(X86::RBP);
1429 Reserved.set(X86::EBP);
1430 Reserved.set(X86::BP);
1431 Reserved.set(X86::BPL);
1436 //===----------------------------------------------------------------------===//
1437 // Stack Frame Processing methods
1438 //===----------------------------------------------------------------------===//
1440 // hasFP - Return true if the specified function should have a dedicated frame
1441 // pointer register. This is true if the function has variable sized allocas or
1442 // if frame pointer elimination is disabled.
1444 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
1445 MachineFrameInfo *MFI = MF.getFrameInfo();
1446 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1448 return (NoFramePointerElim ||
1449 MFI->hasVarSizedObjects() ||
1450 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
1451 (MMI && MMI->callsUnwindInit()));
1454 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
1455 return !MF.getFrameInfo()->hasVarSizedObjects();
1458 void X86RegisterInfo::
1459 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1460 MachineBasicBlock::iterator I) const {
1461 if (!hasReservedCallFrame(MF)) {
1462 // If the stack pointer can be changed after prologue, turn the
1463 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1464 // adjcallstackdown instruction into 'add ESP, <amt>'
1465 // TODO: consider using push / pop instead of sub + store / add
1466 MachineInstr *Old = I;
1467 uint64_t Amount = Old->getOperand(0).getImm();
1469 // We need to keep the stack aligned properly. To do this, we round the
1470 // amount of space needed for the outgoing arguments up to the next
1471 // alignment boundary.
1472 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
1474 MachineInstr *New = 0;
1475 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
1476 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
1477 .addReg(StackPtr).addImm(Amount);
1479 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
1480 // factor out the amount the callee already popped.
1481 uint64_t CalleeAmt = Old->getOperand(1).getImm();
1482 Amount -= CalleeAmt;
1484 unsigned Opc = (Amount < 128) ?
1485 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1486 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1487 New = BuildMI(TII.get(Opc), StackPtr)
1488 .addReg(StackPtr).addImm(Amount);
1492 // Replace the pseudo instruction with a new instruction...
1493 if (New) MBB.insert(I, New);
1495 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
1496 // If we are performing frame pointer elimination and if the callee pops
1497 // something off the stack pointer, add it back. We do this until we have
1498 // more advanced stack pointer tracking ability.
1499 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
1500 unsigned Opc = (CalleeAmt < 128) ?
1501 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1502 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1504 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
1512 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1513 int SPAdj, RegScavenger *RS) const{
1514 assert(SPAdj == 0 && "Unexpected");
1517 MachineInstr &MI = *II;
1518 MachineFunction &MF = *MI.getParent()->getParent();
1519 while (!MI.getOperand(i).isFrameIndex()) {
1521 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1524 int FrameIndex = MI.getOperand(i).getFrameIndex();
1525 // This must be part of a four operand memory reference. Replace the
1526 // FrameIndex with base register with EBP. Add an offset to the offset.
1527 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
1529 // Now add the frame object offset to the offset from EBP.
1530 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
1531 MI.getOperand(i+3).getImm()+SlotSize;
1534 Offset += MF.getFrameInfo()->getStackSize();
1536 Offset += SlotSize; // Skip the saved EBP
1537 // Skip the RETADDR move area
1538 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1539 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1540 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
1543 MI.getOperand(i+3).ChangeToImmediate(Offset);
1547 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
1548 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1549 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1550 if (TailCallReturnAddrDelta < 0) {
1551 // create RETURNADDR area
1561 CreateFixedObject(-TailCallReturnAddrDelta,
1562 (-1*SlotSize)+TailCallReturnAddrDelta);
1565 assert((TailCallReturnAddrDelta <= 0) &&
1566 "The Delta should always be zero or negative");
1567 // Create a frame entry for the EBP register that must be saved.
1568 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
1570 TailCallReturnAddrDelta);
1571 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
1572 "Slot for EBP register must be last in order to be found!");
1576 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
1577 /// stack pointer by a constant value.
1579 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1580 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
1581 const TargetInstrInfo &TII) {
1582 bool isSub = NumBytes < 0;
1583 uint64_t Offset = isSub ? -NumBytes : NumBytes;
1584 unsigned Opc = isSub
1586 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1587 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
1589 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1590 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
1591 uint64_t Chunk = (1LL << 31) - 1;
1594 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
1595 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
1600 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
1602 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1603 unsigned StackPtr, uint64_t *NumBytes = NULL) {
1604 if (MBBI == MBB.begin()) return;
1606 MachineBasicBlock::iterator PI = prior(MBBI);
1607 unsigned Opc = PI->getOpcode();
1608 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1609 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1610 PI->getOperand(0).getReg() == StackPtr) {
1612 *NumBytes += PI->getOperand(2).getImm();
1614 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1615 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1616 PI->getOperand(0).getReg() == StackPtr) {
1618 *NumBytes -= PI->getOperand(2).getImm();
1623 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
1625 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
1626 MachineBasicBlock::iterator &MBBI,
1627 unsigned StackPtr, uint64_t *NumBytes = NULL) {
1630 if (MBBI == MBB.end()) return;
1632 MachineBasicBlock::iterator NI = next(MBBI);
1633 if (NI == MBB.end()) return;
1635 unsigned Opc = NI->getOpcode();
1636 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1637 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1638 NI->getOperand(0).getReg() == StackPtr) {
1640 *NumBytes -= NI->getOperand(2).getImm();
1643 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1644 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1645 NI->getOperand(0).getReg() == StackPtr) {
1647 *NumBytes += NI->getOperand(2).getImm();
1653 /// mergeSPUpdates - Checks the instruction before/after the passed
1654 /// instruction. If it is an ADD/SUB instruction it is deleted
1655 /// argument and the stack adjustment is returned as a positive value for ADD
1656 /// and a negative for SUB.
1657 static int mergeSPUpdates(MachineBasicBlock &MBB,
1658 MachineBasicBlock::iterator &MBBI,
1660 bool doMergeWithPrevious) {
1662 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
1663 (!doMergeWithPrevious && MBBI == MBB.end()))
1668 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
1669 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
1670 unsigned Opc = PI->getOpcode();
1671 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1672 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1673 PI->getOperand(0).getReg() == StackPtr){
1674 Offset += PI->getOperand(2).getImm();
1676 if (!doMergeWithPrevious) MBBI = NI;
1677 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1678 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1679 PI->getOperand(0).getReg() == StackPtr) {
1680 Offset -= PI->getOperand(2).getImm();
1682 if (!doMergeWithPrevious) MBBI = NI;
1688 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
1689 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1690 MachineFrameInfo *MFI = MF.getFrameInfo();
1691 const Function* Fn = MF.getFunction();
1692 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
1693 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1694 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1695 MachineBasicBlock::iterator MBBI = MBB.begin();
1697 // Prepare for frame info.
1698 unsigned FrameLabelId = 0;
1700 // Get the number of bytes to allocate from the FrameInfo.
1701 uint64_t StackSize = MFI->getStackSize();
1702 // Add RETADDR move area to callee saved frame size.
1703 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1704 if (TailCallReturnAddrDelta < 0)
1705 X86FI->setCalleeSavedFrameSize(
1706 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
1707 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1709 // Insert stack pointer adjustment for later moving of return addr. Only
1710 // applies to tail call optimized functions where the callee argument stack
1711 // size is bigger than the callers.
1712 if (TailCallReturnAddrDelta < 0) {
1713 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
1714 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
1718 // Get the offset of the stack slot for the EBP register... which is
1719 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1720 // Update the frame offset adjustment.
1721 MFI->setOffsetAdjustment(SlotSize-NumBytes);
1723 // Save EBP into the appropriate stack slot...
1724 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1726 NumBytes -= SlotSize;
1728 if (MMI && MMI->needsFrameInfo()) {
1729 // Mark effective beginning of when frame pointer becomes valid.
1730 FrameLabelId = MMI->NextLabelID();
1731 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
1734 // Update EBP with the new base value...
1735 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1739 unsigned ReadyLabelId = 0;
1740 if (MMI && MMI->needsFrameInfo()) {
1741 // Mark effective beginning of when frame pointer is ready.
1742 ReadyLabelId = MMI->NextLabelID();
1743 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
1746 // Skip the callee-saved push instructions.
1747 while (MBBI != MBB.end() &&
1748 (MBBI->getOpcode() == X86::PUSH32r ||
1749 MBBI->getOpcode() == X86::PUSH64r))
1752 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
1753 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1754 // Check, whether EAX is livein for this function
1755 bool isEAXAlive = false;
1756 for (MachineFunction::livein_iterator II = MF.livein_begin(),
1757 EE = MF.livein_end(); (II != EE) && !isEAXAlive; ++II) {
1758 unsigned Reg = II->first;
1759 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1760 Reg == X86::AH || Reg == X86::AL);
1763 // Function prologue calls _alloca to probe the stack when allocating
1764 // more than 4k bytes in one go. Touching the stack at 4K increments is
1765 // necessary to ensure that the guard pages used by the OS virtual memory
1766 // manager are allocated in correct sequence.
1768 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
1769 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
1770 .addExternalSymbol("_alloca");
1773 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
1774 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1775 // allocated bytes for EAX.
1776 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
1777 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
1778 .addExternalSymbol("_alloca");
1780 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
1781 StackPtr, NumBytes-4);
1782 MBB.insert(MBBI, MI);
1785 // If there is an SUB32ri of ESP immediately before this instruction,
1786 // merge the two. This can be the case when tail call elimination is
1787 // enabled and the callee has more arguments then the caller.
1788 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1789 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1790 // instruction, merge the two instructions.
1791 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1794 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1798 if (MMI && MMI->needsFrameInfo()) {
1799 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1800 const TargetData *TD = MF.getTarget().getTargetData();
1802 // Calculate amount of bytes used for return address storing
1804 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
1805 TargetFrameInfo::StackGrowsUp ?
1806 TD->getPointerSize() : -TD->getPointerSize());
1809 // Show update of SP.
1812 MachineLocation SPDst(MachineLocation::VirtualFP);
1813 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
1814 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1816 MachineLocation SPDst(MachineLocation::VirtualFP);
1817 MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize+stackGrowth);
1818 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1821 //FIXME: Verify & implement for FP
1822 MachineLocation SPDst(StackPtr);
1823 MachineLocation SPSrc(StackPtr, stackGrowth);
1824 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1827 // Add callee saved registers to move list.
1828 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1830 // FIXME: This is dirty hack. The code itself is pretty mess right now.
1831 // It should be rewritten from scratch and generalized sometimes.
1833 // Determine maximum offset (minumum due to stack growth)
1834 int64_t MaxOffset = 0;
1835 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
1836 MaxOffset = std::min(MaxOffset,
1837 MFI->getObjectOffset(CSI[I].getFrameIdx()));
1839 // Calculate offsets
1840 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
1841 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
1842 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1843 unsigned Reg = CSI[I].getReg();
1844 Offset = (MaxOffset-Offset+saveAreaOffset);
1845 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1846 MachineLocation CSSrc(Reg);
1847 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1852 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
1853 MachineLocation FPSrc(FramePtr);
1854 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1857 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
1858 MachineLocation FPSrc(MachineLocation::VirtualFP);
1859 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1862 // If it's main() on Cygwin\Mingw32 we should align stack as well
1863 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1864 Subtarget->isTargetCygMing()) {
1865 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
1866 .addReg(X86::ESP).addImm(-StackAlign);
1869 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
1870 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1874 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1875 MachineBasicBlock &MBB) const {
1876 const MachineFrameInfo *MFI = MF.getFrameInfo();
1877 const Function* Fn = MF.getFunction();
1878 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1879 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
1880 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1881 unsigned RetOpcode = MBBI->getOpcode();
1883 switch (RetOpcode) {
1886 case X86::TCRETURNdi:
1887 case X86::TCRETURNri:
1888 case X86::TCRETURNri64:
1889 case X86::TCRETURNdi64:
1890 case X86::EH_RETURN:
1893 case X86::TAILJMPm: break; // These are ok
1895 assert(0 && "Can only insert epilog into returning blocks");
1898 // Get the number of bytes to allocate from the FrameInfo
1899 uint64_t StackSize = MFI->getStackSize();
1900 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1901 uint64_t NumBytes = StackSize - CSSize;
1905 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1906 NumBytes -= SlotSize;
1909 // Skip the callee-saved pop instructions.
1910 while (MBBI != MBB.begin()) {
1911 MachineBasicBlock::iterator PI = prior(MBBI);
1912 unsigned Opc = PI->getOpcode();
1913 if (Opc != X86::POP32r && Opc != X86::POP64r && !TII.isTerminatorInstr(Opc))
1918 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1919 // instruction, merge the two instructions.
1920 if (NumBytes || MFI->hasVarSizedObjects())
1921 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1923 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1924 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
1925 // aligned stack in the prologue, - revert stack changes back. Note: we're
1926 // assuming, that frame pointer was forced for main()
1927 if (MFI->hasVarSizedObjects() ||
1928 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1929 Subtarget->isTargetCygMing())) {
1930 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1932 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
1934 MBB.insert(MBBI, MI);
1936 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1942 // adjust stack pointer back: ESP += numbytes
1944 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1946 // We're returning from function via eh_return.
1947 if (RetOpcode == X86::EH_RETURN) {
1948 MBBI = prior(MBB.end());
1949 MachineOperand &DestAddr = MBBI->getOperand(0);
1950 assert(DestAddr.isRegister() && "Offset should be in register!");
1951 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1952 addReg(DestAddr.getReg());
1953 // Tail call return: adjust the stack pointer and jump to callee
1954 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1955 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1956 MBBI = prior(MBB.end());
1957 MachineOperand &JumpTarget = MBBI->getOperand(0);
1958 MachineOperand &StackAdjust = MBBI->getOperand(1);
1959 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
1961 // Adjust stack pointer.
1962 int StackAdj = StackAdjust.getImm();
1963 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1965 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1966 // Incoporate the retaddr area.
1967 Offset = StackAdj-MaxTCDelta;
1968 assert(Offset >= 0 && "Offset should never be negative");
1970 // Check for possible merge with preceeding ADD instruction.
1971 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1972 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1974 // Jump to label or value in register.
1975 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1976 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
1977 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1978 else if (RetOpcode== X86::TCRETURNri64) {
1979 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1981 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1982 // Delete the pseudo instruction TCRETURN.
1984 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1985 (X86FI->getTCReturnAddrDelta() < 0)) {
1986 // Add the return addr area delta back since we are not tail calling.
1987 int delta = -1*X86FI->getTCReturnAddrDelta();
1988 MBBI = prior(MBB.end());
1989 // Check for possible merge with preceeding ADD instruction.
1990 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1991 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1995 unsigned X86RegisterInfo::getRARegister() const {
1997 return X86::RIP; // Should have dwarf #16
1999 return X86::EIP; // Should have dwarf #8
2002 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
2003 return hasFP(MF) ? FramePtr : StackPtr;
2006 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
2008 // Calculate amount of bytes used for return address storing
2009 int stackGrowth = (Is64Bit ? -8 : -4);
2011 // Initial state of the frame pointer is esp+4.
2012 MachineLocation Dst(MachineLocation::VirtualFP);
2013 MachineLocation Src(StackPtr, stackGrowth);
2014 Moves.push_back(MachineMove(0, Dst, Src));
2016 // Add return address to move list
2017 MachineLocation CSDst(StackPtr, stackGrowth);
2018 MachineLocation CSSrc(getRARegister());
2019 Moves.push_back(MachineMove(0, CSDst, CSSrc));
2022 unsigned X86RegisterInfo::getEHExceptionRegister() const {
2023 assert(0 && "What is the exception register");
2027 unsigned X86RegisterInfo::getEHHandlerRegister() const {
2028 assert(0 && "What is the exception handler register");
2033 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
2035 default: return Reg;
2040 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
2042 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
2044 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
2046 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
2052 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
2054 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
2056 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
2058 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
2060 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
2062 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
2064 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
2066 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
2068 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
2070 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
2072 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
2074 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
2076 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
2078 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
2080 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
2082 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
2088 default: return Reg;
2089 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
2091 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
2093 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
2095 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
2097 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
2099 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
2101 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
2103 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
2105 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
2107 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
2109 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
2111 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
2113 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
2115 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
2117 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
2119 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
2124 default: return Reg;
2125 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
2127 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
2129 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
2131 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
2133 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
2135 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
2137 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
2139 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
2141 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
2143 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
2145 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
2147 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
2149 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
2151 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
2153 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
2155 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
2160 default: return Reg;
2161 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
2163 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
2165 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
2167 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
2169 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
2171 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
2173 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
2175 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
2177 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
2179 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
2181 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
2183 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
2185 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
2187 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
2189 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
2191 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
2200 #include "X86GenRegisterInfo.inc"