1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/MachineValueType.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
47 ForceStackAlign("force-align-stack",
48 cl::desc("Force align the stack to the minimum alignment"
49 " needed for the function."),
50 cl::init(false), cl::Hidden);
53 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
56 X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI)
58 (STI.is64Bit() ? X86::RIP : X86::EIP),
59 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false),
60 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true),
61 (STI.is64Bit() ? X86::RIP : X86::EIP)),
63 X86_MC::InitLLVM2SEHRegisterMapping(this);
65 // Cache some information.
66 Is64Bit = Subtarget.is64Bit();
67 IsWin64 = Subtarget.isTargetWin64();
78 // Use a callee-saved register as the base pointer. These registers must
79 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
80 // requires GOT in the EBX register before function calls via PLT GOT pointer.
81 BasePtr = Is64Bit ? X86::RBX : X86::ESI;
85 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
86 // ExeDepsFixer and PostRAScheduler require liveness.
91 X86RegisterInfo::getSEHRegNum(unsigned i) const {
92 return getEncodingValue(i);
95 const TargetRegisterClass *
96 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
98 // The sub_8bit sub-register index is more constrained in 32-bit mode.
99 // It behaves just like the sub_8bit_hi index.
100 if (!Is64Bit && Idx == X86::sub_8bit)
101 Idx = X86::sub_8bit_hi;
103 // Forward to TableGen's default version.
104 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
107 const TargetRegisterClass *
108 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
109 const TargetRegisterClass *B,
110 unsigned SubIdx) const {
111 // The sub_8bit sub-register index is more constrained in 32-bit mode.
112 if (!Is64Bit && SubIdx == X86::sub_8bit) {
113 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
117 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
120 const TargetRegisterClass*
121 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
122 // Don't allow super-classes of GR8_NOREX. This class is only used after
123 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
124 // to the full GR8 register class in 64-bit mode, so we cannot allow the
125 // reigster class inflation.
127 // The GR8_NOREX class is always used in a way that won't be constrained to a
128 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
130 if (RC == &X86::GR8_NOREXRegClass)
133 const TargetRegisterClass *Super = RC;
134 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
136 switch (Super->getID()) {
137 case X86::GR8RegClassID:
138 case X86::GR16RegClassID:
139 case X86::GR32RegClassID:
140 case X86::GR64RegClassID:
141 case X86::FR32RegClassID:
142 case X86::FR64RegClassID:
143 case X86::RFP32RegClassID:
144 case X86::RFP64RegClassID:
145 case X86::RFP80RegClassID:
146 case X86::VR128RegClassID:
147 case X86::VR256RegClassID:
148 // Don't return a super-class that would shrink the spill size.
149 // That can happen with the vector and float classes.
150 if (Super->getSize() == RC->getSize())
158 const TargetRegisterClass *
159 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
160 unsigned Kind) const {
162 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
163 case 0: // Normal GPRs.
164 if (Subtarget.isTarget64BitLP64())
165 return &X86::GR64RegClass;
166 return &X86::GR32RegClass;
167 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
168 if (Subtarget.isTarget64BitLP64())
169 return &X86::GR64_NOSPRegClass;
170 return &X86::GR32_NOSPRegClass;
171 case 2: // Available for tailcall (not callee-saved GPRs).
172 if (Subtarget.isTargetWin64())
173 return &X86::GR64_TCW64RegClass;
174 else if (Subtarget.is64Bit())
175 return &X86::GR64_TCRegClass;
177 const Function *F = MF.getFunction();
178 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
180 return &X86::GR32RegClass;
181 return &X86::GR32_TCRegClass;
185 const TargetRegisterClass *
186 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
187 if (RC == &X86::CCRRegClass) {
189 return &X86::GR64RegClass;
191 return &X86::GR32RegClass;
197 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
198 MachineFunction &MF) const {
199 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
201 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
202 switch (RC->getID()) {
205 case X86::GR32RegClassID:
207 case X86::GR64RegClassID:
209 case X86::VR128RegClassID:
210 return Subtarget.is64Bit() ? 10 : 4;
211 case X86::VR64RegClassID:
217 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
218 bool HasAVX = Subtarget.hasAVX();
219 bool HasAVX512 = Subtarget.hasAVX512();
221 assert(MF && "MachineFunction required");
222 switch (MF->getFunction()->getCallingConv()) {
223 case CallingConv::GHC:
224 case CallingConv::HiPE:
225 return CSR_NoRegs_SaveList;
226 case CallingConv::AnyReg:
228 return CSR_64_AllRegs_AVX_SaveList;
229 return CSR_64_AllRegs_SaveList;
230 case CallingConv::PreserveMost:
231 return CSR_64_RT_MostRegs_SaveList;
232 case CallingConv::PreserveAll:
234 return CSR_64_RT_AllRegs_AVX_SaveList;
235 return CSR_64_RT_AllRegs_SaveList;
236 case CallingConv::Intel_OCL_BI: {
237 if (HasAVX512 && IsWin64)
238 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
239 if (HasAVX512 && Is64Bit)
240 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
241 if (HasAVX && IsWin64)
242 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
243 if (HasAVX && Is64Bit)
244 return CSR_64_Intel_OCL_BI_AVX_SaveList;
245 if (!HasAVX && !IsWin64 && Is64Bit)
246 return CSR_64_Intel_OCL_BI_SaveList;
249 case CallingConv::Cold:
251 return CSR_64_MostRegs_SaveList;
257 bool CallsEHReturn = MF->getMMI().callsEHReturn();
260 return CSR_Win64_SaveList;
262 return CSR_64EHRet_SaveList;
263 return CSR_64_SaveList;
266 return CSR_32EHRet_SaveList;
267 return CSR_32_SaveList;
271 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
272 bool HasAVX = Subtarget.hasAVX();
273 bool HasAVX512 = Subtarget.hasAVX512();
276 case CallingConv::GHC:
277 case CallingConv::HiPE:
278 return CSR_NoRegs_RegMask;
279 case CallingConv::AnyReg:
281 return CSR_64_AllRegs_AVX_RegMask;
282 return CSR_64_AllRegs_RegMask;
283 case CallingConv::PreserveMost:
284 return CSR_64_RT_MostRegs_RegMask;
285 case CallingConv::PreserveAll:
287 return CSR_64_RT_AllRegs_AVX_RegMask;
288 return CSR_64_RT_AllRegs_RegMask;
289 case CallingConv::Intel_OCL_BI: {
290 if (HasAVX512 && IsWin64)
291 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
292 if (HasAVX512 && Is64Bit)
293 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
294 if (HasAVX && IsWin64)
295 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
296 if (HasAVX && Is64Bit)
297 return CSR_64_Intel_OCL_BI_AVX_RegMask;
298 if (!HasAVX && !IsWin64 && Is64Bit)
299 return CSR_64_Intel_OCL_BI_RegMask;
302 case CallingConv::Cold:
304 return CSR_64_MostRegs_RegMask;
310 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
314 return CSR_Win64_RegMask;
315 return CSR_64_RegMask;
317 return CSR_32_RegMask;
321 X86RegisterInfo::getNoPreservedMask() const {
322 return CSR_NoRegs_RegMask;
325 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
326 BitVector Reserved(getNumRegs());
327 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
329 // Set the stack-pointer register and its aliases as reserved.
330 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
334 // Set the instruction pointer register and its aliases as reserved.
335 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
339 // Set the frame-pointer register and its aliases as reserved if needed.
340 if (TFI->hasFP(MF)) {
341 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
346 // Set the base-pointer register and its aliases as reserved if needed.
347 if (hasBasePointer(MF)) {
348 CallingConv::ID CC = MF.getFunction()->getCallingConv();
349 const uint32_t* RegMask = getCallPreservedMask(CC);
350 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
352 "Stack realignment in presence of dynamic allocas is not supported with"
353 "this calling convention.");
355 for (MCSubRegIterator I(getBaseRegister(), this, /*IncludeSelf=*/true);
360 // Mark the segment registers as reserved.
361 Reserved.set(X86::CS);
362 Reserved.set(X86::SS);
363 Reserved.set(X86::DS);
364 Reserved.set(X86::ES);
365 Reserved.set(X86::FS);
366 Reserved.set(X86::GS);
368 // Mark the floating point stack registers as reserved.
369 for (unsigned n = 0; n != 8; ++n)
370 Reserved.set(X86::ST0 + n);
372 // Reserve the registers that only exist in 64-bit mode.
374 // These 8-bit registers are part of the x86-64 extension even though their
375 // super-registers are old 32-bits.
376 Reserved.set(X86::SIL);
377 Reserved.set(X86::DIL);
378 Reserved.set(X86::BPL);
379 Reserved.set(X86::SPL);
381 for (unsigned n = 0; n != 8; ++n) {
383 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
387 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
391 if (!Is64Bit || !Subtarget.hasAVX512()) {
392 for (unsigned n = 16; n != 32; ++n) {
393 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
401 //===----------------------------------------------------------------------===//
402 // Stack Frame Processing methods
403 //===----------------------------------------------------------------------===//
405 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
406 const MachineFrameInfo *MFI = MF.getFrameInfo();
408 if (!EnableBasePointer)
411 // When we need stack realignment, we can't address the stack from the frame
412 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
413 // can't address variables from the stack pointer. MS inline asm can
414 // reference locals while also adjusting the stack pointer. When we can't
415 // use both the SP and the FP, we need a separate base pointer register.
416 bool CantUseFP = needsStackRealignment(MF);
418 MFI->hasVarSizedObjects() || MFI->hasInlineAsmWithSPAdjust();
419 return CantUseFP && CantUseSP;
422 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
423 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
426 const MachineFrameInfo *MFI = MF.getFrameInfo();
427 const MachineRegisterInfo *MRI = &MF.getRegInfo();
429 // Stack realignment requires a frame pointer. If we already started
430 // register allocation with frame pointer elimination, it is too late now.
431 if (!MRI->canReserveReg(FramePtr))
434 // If a base pointer is necessary. Check that it isn't too late to reserve
436 if (MFI->hasVarSizedObjects())
437 return MRI->canReserveReg(BasePtr);
441 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
442 const MachineFrameInfo *MFI = MF.getFrameInfo();
443 const Function *F = MF.getFunction();
444 unsigned StackAlign = MF.getTarget()
447 ->getStackAlignment();
448 bool requiresRealignment =
449 ((MFI->getMaxAlignment() > StackAlign) ||
450 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
451 Attribute::StackAlignment));
453 // If we've requested that we force align the stack do so now.
455 return canRealignStack(MF);
457 return requiresRealignment && canRealignStack(MF);
460 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
461 unsigned Reg, int &FrameIdx) const {
462 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
464 if (Reg == FramePtr && TFI->hasFP(MF)) {
465 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
472 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
473 int SPAdj, unsigned FIOperandNum,
474 RegScavenger *RS) const {
475 assert(SPAdj == 0 && "Unexpected");
477 MachineInstr &MI = *II;
478 MachineFunction &MF = *MI.getParent()->getParent();
479 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
480 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
483 unsigned Opc = MI.getOpcode();
484 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
485 if (hasBasePointer(MF))
486 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
487 else if (needsStackRealignment(MF))
488 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
492 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
494 // This must be part of a four operand memory reference. Replace the
495 // FrameIndex with base register with EBP. Add an offset to the offset.
496 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
498 // Now add the frame object offset to the offset from EBP.
501 // Tail call jmp happens after FP is popped.
502 const MachineFrameInfo *MFI = MF.getFrameInfo();
503 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
505 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
507 // The frame index format for stackmaps and patchpoints is different from the
508 // X86 format. It only has a FI and an offset.
509 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
510 assert(BasePtr == FramePtr && "Expected the FP as base register");
511 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
512 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
516 if (MI.getOperand(FIOperandNum+3).isImm()) {
517 // Offset is a 32-bit integer.
518 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
519 int Offset = FIOffset + Imm;
520 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
521 "Requesting 64-bit offset in 32-bit immediate!");
522 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
524 // Offset is symbolic. This is extremely rare.
525 uint64_t Offset = FIOffset +
526 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
527 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
531 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
532 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
533 return TFI->hasFP(MF) ? FramePtr : StackPtr;
537 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
540 default: llvm_unreachable("Unexpected VT");
544 default: return getX86SubSuperRegister(Reg, MVT::i64);
545 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
547 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
549 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
551 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
553 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
555 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
557 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
559 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
564 default: llvm_unreachable("Unexpected register");
565 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
567 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
569 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
571 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
573 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
575 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
577 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
579 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
581 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
583 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
585 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
587 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
589 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
591 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
593 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
595 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
601 default: llvm_unreachable("Unexpected register");
602 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
604 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
606 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
608 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
610 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
612 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
614 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
616 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
618 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
620 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
622 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
624 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
626 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
628 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
630 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
632 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
637 default: llvm_unreachable("Unexpected register");
638 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
640 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
642 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
644 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
646 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
648 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
650 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
652 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
654 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
656 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
658 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
660 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
662 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
664 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
666 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
668 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
673 default: llvm_unreachable("Unexpected register");
674 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
676 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
678 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
680 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
682 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
684 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
686 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
688 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
690 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
692 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
694 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
696 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
698 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
700 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
702 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
704 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
710 unsigned get512BitSuperRegister(unsigned Reg) {
711 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
712 return X86::ZMM0 + (Reg - X86::XMM0);
713 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
714 return X86::ZMM0 + (Reg - X86::YMM0);
715 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
717 llvm_unreachable("Unexpected SIMD register");