1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Target/TargetAsmInfo.h"
32 #include "llvm/Target/TargetFrameInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
40 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
41 const TargetInstrInfo &tii)
42 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
44 // Cache some information.
45 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
46 Is64Bit = Subtarget->is64Bit();
47 StackAlign = TM.getFrameInfo()->getStackAlignment();
59 // getDwarfRegNum - This function maps LLVM register identifiers to the
60 // Dwarf specific numbering, used in debug info and exception tables.
62 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
63 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
64 unsigned Flavour = DWARFFlavour::X86_64;
65 if (!Subtarget->is64Bit()) {
66 if (Subtarget->isTargetDarwin()) {
68 Flavour = DWARFFlavour::X86_32_DarwinEH;
70 Flavour = DWARFFlavour::X86_32_Generic;
71 } else if (Subtarget->isTargetCygMing()) {
72 // Unsupported by now, just quick fallback
73 Flavour = DWARFFlavour::X86_32_Generic;
75 Flavour = DWARFFlavour::X86_32_Generic;
79 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
82 // getX86RegNum - This function maps LLVM register identifiers to their X86
83 // specific numbering, which is used in various places encoding instructions.
85 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const {
87 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
88 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
89 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
90 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
91 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
93 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
95 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
97 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
100 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
102 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
104 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
106 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
108 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
110 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
112 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
114 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
117 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
118 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
119 return RegNo-X86::ST0;
121 case X86::XMM0: case X86::XMM8: case X86::MM0:
123 case X86::XMM1: case X86::XMM9: case X86::MM1:
125 case X86::XMM2: case X86::XMM10: case X86::MM2:
127 case X86::XMM3: case X86::XMM11: case X86::MM3:
129 case X86::XMM4: case X86::XMM12: case X86::MM4:
131 case X86::XMM5: case X86::XMM13: case X86::MM5:
133 case X86::XMM6: case X86::XMM14: case X86::MM6:
135 case X86::XMM7: case X86::XMM15: case X86::MM7:
139 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
140 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
145 const TargetRegisterClass *
146 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
147 if (RC == &X86::CCRRegClass)
149 return &X86::GR64RegClass;
151 return &X86::GR32RegClass;
155 void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
156 MachineBasicBlock::iterator I,
158 const MachineInstr *Orig) const {
159 // MOV32r0 etc. are implemented with xor which clobbers condition code.
160 // Re-materialize them as movri instructions to avoid side effects.
161 switch (Orig->getOpcode()) {
163 BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
166 BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
169 BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
172 BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
175 MachineInstr *MI = Orig->clone();
176 MI->getOperand(0).setReg(DestReg);
184 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
185 static const unsigned CalleeSavedRegs32Bit[] = {
186 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
189 static const unsigned CalleeSavedRegs32EHRet[] = {
190 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
193 static const unsigned CalleeSavedRegs64Bit[] = {
194 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
198 return CalleeSavedRegs64Bit;
201 MachineFrameInfo *MFI = MF->getFrameInfo();
202 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
203 if (MMI && MMI->callsEHReturn())
204 return CalleeSavedRegs32EHRet;
206 return CalleeSavedRegs32Bit;
210 const TargetRegisterClass* const*
211 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
212 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
213 &X86::GR32RegClass, &X86::GR32RegClass,
214 &X86::GR32RegClass, &X86::GR32RegClass, 0
216 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
217 &X86::GR32RegClass, &X86::GR32RegClass,
218 &X86::GR32RegClass, &X86::GR32RegClass,
219 &X86::GR32RegClass, &X86::GR32RegClass, 0
221 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
222 &X86::GR64RegClass, &X86::GR64RegClass,
223 &X86::GR64RegClass, &X86::GR64RegClass,
224 &X86::GR64RegClass, &X86::GR64RegClass, 0
228 return CalleeSavedRegClasses64Bit;
231 MachineFrameInfo *MFI = MF->getFrameInfo();
232 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
233 if (MMI && MMI->callsEHReturn())
234 return CalleeSavedRegClasses32EHRet;
236 return CalleeSavedRegClasses32Bit;
241 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
242 BitVector Reserved(getNumRegs());
243 Reserved.set(X86::RSP);
244 Reserved.set(X86::ESP);
245 Reserved.set(X86::SP);
246 Reserved.set(X86::SPL);
248 Reserved.set(X86::RBP);
249 Reserved.set(X86::EBP);
250 Reserved.set(X86::BP);
251 Reserved.set(X86::BPL);
256 //===----------------------------------------------------------------------===//
257 // Stack Frame Processing methods
258 //===----------------------------------------------------------------------===//
260 // hasFP - Return true if the specified function should have a dedicated frame
261 // pointer register. This is true if the function has variable sized allocas or
262 // if frame pointer elimination is disabled.
264 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
265 MachineFrameInfo *MFI = MF.getFrameInfo();
266 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
268 return (NoFramePointerElim ||
269 MFI->hasVarSizedObjects() ||
270 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
271 (MMI && MMI->callsUnwindInit()));
274 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
275 return !MF.getFrameInfo()->hasVarSizedObjects();
278 void X86RegisterInfo::
279 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
280 MachineBasicBlock::iterator I) const {
281 if (!hasReservedCallFrame(MF)) {
282 // If the stack pointer can be changed after prologue, turn the
283 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
284 // adjcallstackdown instruction into 'add ESP, <amt>'
285 // TODO: consider using push / pop instead of sub + store / add
286 MachineInstr *Old = I;
287 uint64_t Amount = Old->getOperand(0).getImm();
289 // We need to keep the stack aligned properly. To do this, we round the
290 // amount of space needed for the outgoing arguments up to the next
291 // alignment boundary.
292 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
294 MachineInstr *New = 0;
295 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
296 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
297 .addReg(StackPtr).addImm(Amount);
299 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
300 // factor out the amount the callee already popped.
301 uint64_t CalleeAmt = Old->getOperand(1).getImm();
304 unsigned Opc = (Amount < 128) ?
305 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
306 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
307 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
311 // Replace the pseudo instruction with a new instruction...
312 if (New) MBB.insert(I, New);
314 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
315 // If we are performing frame pointer elimination and if the callee pops
316 // something off the stack pointer, add it back. We do this until we have
317 // more advanced stack pointer tracking ability.
318 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
319 unsigned Opc = (CalleeAmt < 128) ?
320 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
321 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
323 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
331 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
332 int SPAdj, RegScavenger *RS) const{
333 assert(SPAdj == 0 && "Unexpected");
336 MachineInstr &MI = *II;
337 MachineFunction &MF = *MI.getParent()->getParent();
338 while (!MI.getOperand(i).isFrameIndex()) {
340 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
343 int FrameIndex = MI.getOperand(i).getIndex();
344 // This must be part of a four operand memory reference. Replace the
345 // FrameIndex with base register with EBP. Add an offset to the offset.
346 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
348 // Now add the frame object offset to the offset from EBP.
349 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
350 MI.getOperand(i+3).getImm()+SlotSize;
353 Offset += MF.getFrameInfo()->getStackSize();
355 Offset += SlotSize; // Skip the saved EBP
356 // Skip the RETADDR move area
357 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
358 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
359 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
362 MI.getOperand(i+3).ChangeToImmediate(Offset);
366 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
367 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
368 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
369 if (TailCallReturnAddrDelta < 0) {
370 // create RETURNADDR area
380 CreateFixedObject(-TailCallReturnAddrDelta,
381 (-1*SlotSize)+TailCallReturnAddrDelta);
384 assert((TailCallReturnAddrDelta <= 0) &&
385 "The Delta should always be zero or negative");
386 // Create a frame entry for the EBP register that must be saved.
387 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
389 TailCallReturnAddrDelta);
390 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
391 "Slot for EBP register must be last in order to be found!");
395 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
396 /// stack pointer by a constant value.
398 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
399 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
400 const TargetInstrInfo &TII) {
401 bool isSub = NumBytes < 0;
402 uint64_t Offset = isSub ? -NumBytes : NumBytes;
405 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
406 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
408 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
409 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
410 uint64_t Chunk = (1LL << 31) - 1;
413 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
414 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
419 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
421 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
422 unsigned StackPtr, uint64_t *NumBytes = NULL) {
423 if (MBBI == MBB.begin()) return;
425 MachineBasicBlock::iterator PI = prior(MBBI);
426 unsigned Opc = PI->getOpcode();
427 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
428 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
429 PI->getOperand(0).getReg() == StackPtr) {
431 *NumBytes += PI->getOperand(2).getImm();
433 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
434 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
435 PI->getOperand(0).getReg() == StackPtr) {
437 *NumBytes -= PI->getOperand(2).getImm();
442 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
444 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
445 MachineBasicBlock::iterator &MBBI,
446 unsigned StackPtr, uint64_t *NumBytes = NULL) {
449 if (MBBI == MBB.end()) return;
451 MachineBasicBlock::iterator NI = next(MBBI);
452 if (NI == MBB.end()) return;
454 unsigned Opc = NI->getOpcode();
455 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
456 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
457 NI->getOperand(0).getReg() == StackPtr) {
459 *NumBytes -= NI->getOperand(2).getImm();
462 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
463 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
464 NI->getOperand(0).getReg() == StackPtr) {
466 *NumBytes += NI->getOperand(2).getImm();
472 /// mergeSPUpdates - Checks the instruction before/after the passed
473 /// instruction. If it is an ADD/SUB instruction it is deleted
474 /// argument and the stack adjustment is returned as a positive value for ADD
475 /// and a negative for SUB.
476 static int mergeSPUpdates(MachineBasicBlock &MBB,
477 MachineBasicBlock::iterator &MBBI,
479 bool doMergeWithPrevious) {
481 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
482 (!doMergeWithPrevious && MBBI == MBB.end()))
487 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
488 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
489 unsigned Opc = PI->getOpcode();
490 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
491 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
492 PI->getOperand(0).getReg() == StackPtr){
493 Offset += PI->getOperand(2).getImm();
495 if (!doMergeWithPrevious) MBBI = NI;
496 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
497 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
498 PI->getOperand(0).getReg() == StackPtr) {
499 Offset -= PI->getOperand(2).getImm();
501 if (!doMergeWithPrevious) MBBI = NI;
507 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
508 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
509 MachineFrameInfo *MFI = MF.getFrameInfo();
510 const Function* Fn = MF.getFunction();
511 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
512 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
513 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
514 MachineBasicBlock::iterator MBBI = MBB.begin();
516 // Prepare for frame info.
517 unsigned FrameLabelId = 0;
519 // Get the number of bytes to allocate from the FrameInfo.
520 uint64_t StackSize = MFI->getStackSize();
521 // Add RETADDR move area to callee saved frame size.
522 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
523 if (TailCallReturnAddrDelta < 0)
524 X86FI->setCalleeSavedFrameSize(
525 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
526 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
528 // Insert stack pointer adjustment for later moving of return addr. Only
529 // applies to tail call optimized functions where the callee argument stack
530 // size is bigger than the callers.
531 if (TailCallReturnAddrDelta < 0) {
532 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
533 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
537 // Get the offset of the stack slot for the EBP register... which is
538 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
539 // Update the frame offset adjustment.
540 MFI->setOffsetAdjustment(SlotSize-NumBytes);
542 // Save EBP into the appropriate stack slot...
543 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
545 NumBytes -= SlotSize;
547 if (MMI && MMI->needsFrameInfo()) {
548 // Mark effective beginning of when frame pointer becomes valid.
549 FrameLabelId = MMI->NextLabelID();
550 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
553 // Update EBP with the new base value...
554 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
558 unsigned ReadyLabelId = 0;
559 if (MMI && MMI->needsFrameInfo()) {
560 // Mark effective beginning of when frame pointer is ready.
561 ReadyLabelId = MMI->NextLabelID();
562 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
565 // Skip the callee-saved push instructions.
566 while (MBBI != MBB.end() &&
567 (MBBI->getOpcode() == X86::PUSH32r ||
568 MBBI->getOpcode() == X86::PUSH64r))
571 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
572 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
573 // Check, whether EAX is livein for this function
574 bool isEAXAlive = false;
575 for (MachineRegisterInfo::livein_iterator
576 II = MF.getRegInfo().livein_begin(),
577 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
578 unsigned Reg = II->first;
579 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
580 Reg == X86::AH || Reg == X86::AL);
583 // Function prologue calls _alloca to probe the stack when allocating
584 // more than 4k bytes in one go. Touching the stack at 4K increments is
585 // necessary to ensure that the guard pages used by the OS virtual memory
586 // manager are allocated in correct sequence.
588 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
589 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
590 .addExternalSymbol("_alloca");
593 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
594 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
595 // allocated bytes for EAX.
596 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
597 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
598 .addExternalSymbol("_alloca");
600 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
601 StackPtr, NumBytes-4);
602 MBB.insert(MBBI, MI);
605 // If there is an SUB32ri of ESP immediately before this instruction,
606 // merge the two. This can be the case when tail call elimination is
607 // enabled and the callee has more arguments then the caller.
608 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
609 // If there is an ADD32ri or SUB32ri of ESP immediately after this
610 // instruction, merge the two instructions.
611 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
614 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
618 if (MMI && MMI->needsFrameInfo()) {
619 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
620 const TargetData *TD = MF.getTarget().getTargetData();
622 // Calculate amount of bytes used for return address storing
624 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
625 TargetFrameInfo::StackGrowsUp ?
626 TD->getPointerSize() : -TD->getPointerSize());
629 // Show update of SP.
632 MachineLocation SPDst(MachineLocation::VirtualFP);
633 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
634 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
636 MachineLocation SPDst(MachineLocation::VirtualFP);
637 MachineLocation SPSrc(MachineLocation::VirtualFP,
638 -StackSize+stackGrowth);
639 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
642 //FIXME: Verify & implement for FP
643 MachineLocation SPDst(StackPtr);
644 MachineLocation SPSrc(StackPtr, stackGrowth);
645 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
648 // Add callee saved registers to move list.
649 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
651 // FIXME: This is dirty hack. The code itself is pretty mess right now.
652 // It should be rewritten from scratch and generalized sometimes.
654 // Determine maximum offset (minumum due to stack growth)
655 int64_t MaxOffset = 0;
656 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
657 MaxOffset = std::min(MaxOffset,
658 MFI->getObjectOffset(CSI[I].getFrameIdx()));
661 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
662 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
663 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
664 unsigned Reg = CSI[I].getReg();
665 Offset = (MaxOffset-Offset+saveAreaOffset);
666 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
667 MachineLocation CSSrc(Reg);
668 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
673 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
674 MachineLocation FPSrc(FramePtr);
675 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
678 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
679 MachineLocation FPSrc(MachineLocation::VirtualFP);
680 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
683 // If it's main() on Cygwin\Mingw32 we should align stack as well
684 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
685 Subtarget->isTargetCygMing()) {
686 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
687 .addReg(X86::ESP).addImm(-StackAlign);
690 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
691 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
695 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
696 MachineBasicBlock &MBB) const {
697 const MachineFrameInfo *MFI = MF.getFrameInfo();
698 const Function* Fn = MF.getFunction();
699 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
700 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
701 MachineBasicBlock::iterator MBBI = prior(MBB.end());
702 unsigned RetOpcode = MBBI->getOpcode();
707 case X86::TCRETURNdi:
708 case X86::TCRETURNri:
709 case X86::TCRETURNri64:
710 case X86::TCRETURNdi64:
714 case X86::TAILJMPm: break; // These are ok
716 assert(0 && "Can only insert epilog into returning blocks");
719 // Get the number of bytes to allocate from the FrameInfo
720 uint64_t StackSize = MFI->getStackSize();
721 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
722 uint64_t NumBytes = StackSize - CSSize;
726 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
727 NumBytes -= SlotSize;
730 // Skip the callee-saved pop instructions.
731 while (MBBI != MBB.begin()) {
732 MachineBasicBlock::iterator PI = prior(MBBI);
733 unsigned Opc = PI->getOpcode();
734 if (Opc != X86::POP32r && Opc != X86::POP64r &&
735 !PI->getDesc().isTerminator())
740 // If there is an ADD32ri or SUB32ri of ESP immediately before this
741 // instruction, merge the two instructions.
742 if (NumBytes || MFI->hasVarSizedObjects())
743 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
745 // If dynamic alloca is used, then reset esp to point to the last callee-saved
746 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
747 // aligned stack in the prologue, - revert stack changes back. Note: we're
748 // assuming, that frame pointer was forced for main()
749 if (MFI->hasVarSizedObjects() ||
750 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
751 Subtarget->isTargetCygMing())) {
752 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
754 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
756 MBB.insert(MBBI, MI);
758 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
764 // adjust stack pointer back: ESP += numbytes
766 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
768 // We're returning from function via eh_return.
769 if (RetOpcode == X86::EH_RETURN) {
770 MBBI = prior(MBB.end());
771 MachineOperand &DestAddr = MBBI->getOperand(0);
772 assert(DestAddr.isRegister() && "Offset should be in register!");
773 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
774 addReg(DestAddr.getReg());
775 // Tail call return: adjust the stack pointer and jump to callee
776 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
777 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
778 MBBI = prior(MBB.end());
779 MachineOperand &JumpTarget = MBBI->getOperand(0);
780 MachineOperand &StackAdjust = MBBI->getOperand(1);
781 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
783 // Adjust stack pointer.
784 int StackAdj = StackAdjust.getImm();
785 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
787 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
788 // Incoporate the retaddr area.
789 Offset = StackAdj-MaxTCDelta;
790 assert(Offset >= 0 && "Offset should never be negative");
792 // Check for possible merge with preceeding ADD instruction.
793 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
794 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
796 // Jump to label or value in register.
797 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
798 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
799 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
800 else if (RetOpcode== X86::TCRETURNri64) {
801 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
803 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
804 // Delete the pseudo instruction TCRETURN.
806 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
807 (X86FI->getTCReturnAddrDelta() < 0)) {
808 // Add the return addr area delta back since we are not tail calling.
809 int delta = -1*X86FI->getTCReturnAddrDelta();
810 MBBI = prior(MBB.end());
811 // Check for possible merge with preceeding ADD instruction.
812 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
813 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
817 unsigned X86RegisterInfo::getRARegister() const {
819 return X86::RIP; // Should have dwarf #16
821 return X86::EIP; // Should have dwarf #8
824 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
825 return hasFP(MF) ? FramePtr : StackPtr;
829 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
830 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
832 return Offset + MF.getFrameInfo()->getStackSize();
834 Offset += SlotSize; // Skip the saved EBP
835 // Skip the RETADDR move area
836 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
837 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
838 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
842 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
844 // Calculate amount of bytes used for return address storing
845 int stackGrowth = (Is64Bit ? -8 : -4);
847 // Initial state of the frame pointer is esp+4.
848 MachineLocation Dst(MachineLocation::VirtualFP);
849 MachineLocation Src(StackPtr, stackGrowth);
850 Moves.push_back(MachineMove(0, Dst, Src));
852 // Add return address to move list
853 MachineLocation CSDst(StackPtr, stackGrowth);
854 MachineLocation CSSrc(getRARegister());
855 Moves.push_back(MachineMove(0, CSDst, CSSrc));
858 unsigned X86RegisterInfo::getEHExceptionRegister() const {
859 assert(0 && "What is the exception register");
863 unsigned X86RegisterInfo::getEHHandlerRegister() const {
864 assert(0 && "What is the exception handler register");
869 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
876 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
878 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
880 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
882 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
888 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
890 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
892 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
894 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
896 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
898 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
900 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
902 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
904 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
906 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
908 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
910 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
912 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
914 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
916 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
918 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
925 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
927 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
929 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
931 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
933 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
935 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
937 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
939 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
941 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
943 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
945 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
947 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
949 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
951 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
953 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
955 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
961 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
963 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
965 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
967 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
969 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
971 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
973 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
975 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
977 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
979 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
981 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
983 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
985 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
987 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
989 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
991 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
997 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
999 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1001 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1003 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1005 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1007 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1009 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1011 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1013 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1015 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1017 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1019 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1021 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1023 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1025 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1027 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1036 #include "X86GenRegisterInfo.inc"