1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "Support/CommandLine.h"
27 #include "Support/STLExtras.h"
32 NoFPElim("disable-fp-elim",
33 cl::desc("Disable frame pointer elimination optimization"));
35 NoFusing("disable-spill-fusing",
36 cl::desc("Disable fusing of spill code into instructions"));
38 PrintFailedFusing("print-failed-fuse-candidates",
39 cl::desc("Print instructions that the allocator wants to"
40 " fuse, but the X86 backend currently can't"),
44 X86RegisterInfo::X86RegisterInfo()
45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
47 static unsigned getIdx(const TargetRegisterClass *RC) {
48 switch (RC->getSize()) {
49 default: assert(0 && "Invalid data size!");
57 int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MI,
59 unsigned SrcReg, int FrameIdx,
60 const TargetRegisterClass *RC) const {
61 static const unsigned Opcode[] =
62 { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTPr80 };
63 MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
64 FrameIdx).addReg(SrcReg);
69 int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator MI,
71 unsigned DestReg, int FrameIdx,
72 const TargetRegisterClass *RC) const{
73 static const unsigned Opcode[] =
74 { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDr80 };
75 unsigned OC = Opcode[getIdx(RC)];
76 MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
80 int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MI,
82 unsigned DestReg, unsigned SrcReg,
83 const TargetRegisterClass *RC) const {
84 static const unsigned Opcode[] =
85 { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
86 MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
90 static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
92 return addFrameReference(BuildMI(Opcode, 1, MI->getOperand(0).getReg()),
96 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
98 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
99 .addReg(MI->getOperand(1).getReg());
102 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
104 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
105 .addZImm(MI->getOperand(1).getImmedValue());
108 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
110 return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
114 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
116 return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
117 FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
121 bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI,
122 unsigned i, int FrameIndex) const {
123 if (NoFusing) return false;
125 /// FIXME: This should obviously be autogenerated by tablegen when patterns
127 MachineBasicBlock& MBB = *MI->getParent();
128 MachineInstr* NI = 0;
130 switch(MI->getOpcode()) {
131 case X86::MOVrr8: NI = MakeMRInst(X86::MOVmr8 , FrameIndex, MI); break;
132 case X86::MOVrr16: NI = MakeMRInst(X86::MOVmr16, FrameIndex, MI); break;
133 case X86::MOVrr32: NI = MakeMRInst(X86::MOVmr32, FrameIndex, MI); break;
134 case X86::MOVri8: NI = MakeMIInst(X86::MOVmi8 , FrameIndex, MI); break;
135 case X86::MOVri16: NI = MakeMIInst(X86::MOVmi16, FrameIndex, MI); break;
136 case X86::MOVri32: NI = MakeMIInst(X86::MOVmi32, FrameIndex, MI); break;
137 case X86::MULr8: NI = MakeMInst(X86::MULm8 , FrameIndex, MI); break;
138 case X86::MULr16: NI = MakeMInst(X86::MULm16, FrameIndex, MI); break;
139 case X86::MULr32: NI = MakeMInst(X86::MULm32, FrameIndex, MI); break;
140 case X86::DIVr8: NI = MakeMInst(X86::DIVm8 , FrameIndex, MI); break;
141 case X86::DIVr16: NI = MakeMInst(X86::DIVm16, FrameIndex, MI); break;
142 case X86::DIVr32: NI = MakeMInst(X86::DIVm32, FrameIndex, MI); break;
143 case X86::IDIVr8: NI = MakeMInst(X86::IDIVm8 , FrameIndex, MI); break;
144 case X86::IDIVr16: NI = MakeMInst(X86::IDIVm16, FrameIndex, MI); break;
145 case X86::IDIVr32: NI = MakeMInst(X86::IDIVm32, FrameIndex, MI); break;
146 case X86::NEGr8: NI = MakeMInst(X86::NEGm8 , FrameIndex, MI); break;
147 case X86::NEGr16: NI = MakeMInst(X86::NEGm16, FrameIndex, MI); break;
148 case X86::NEGr32: NI = MakeMInst(X86::NEGm32, FrameIndex, MI); break;
149 case X86::NOTr8: NI = MakeMInst(X86::NOTm8 , FrameIndex, MI); break;
150 case X86::NOTr16: NI = MakeMInst(X86::NOTm16, FrameIndex, MI); break;
151 case X86::NOTr32: NI = MakeMInst(X86::NOTm32, FrameIndex, MI); break;
152 case X86::INCr8: NI = MakeMInst(X86::INCm8 , FrameIndex, MI); break;
153 case X86::INCr16: NI = MakeMInst(X86::INCm16, FrameIndex, MI); break;
154 case X86::INCr32: NI = MakeMInst(X86::INCm32, FrameIndex, MI); break;
155 case X86::DECr8: NI = MakeMInst(X86::DECm8 , FrameIndex, MI); break;
156 case X86::DECr16: NI = MakeMInst(X86::DECm16, FrameIndex, MI); break;
157 case X86::DECr32: NI = MakeMInst(X86::DECm32, FrameIndex, MI); break;
158 case X86::ADDrr8: NI = MakeMRInst(X86::ADDmr8 , FrameIndex, MI); break;
159 case X86::ADDrr16: NI = MakeMRInst(X86::ADDmr16, FrameIndex, MI); break;
160 case X86::ADDrr32: NI = MakeMRInst(X86::ADDmr32, FrameIndex, MI); break;
161 case X86::ADCrr32: NI = MakeMRInst(X86::ADCmr32, FrameIndex, MI); break;
162 case X86::ADDri8: NI = MakeMIInst(X86::ADDmi8 , FrameIndex, MI); break;
163 case X86::ADDri16: NI = MakeMIInst(X86::ADDmi16, FrameIndex, MI); break;
164 case X86::ADDri32: NI = MakeMIInst(X86::ADDmi32, FrameIndex, MI); break;
165 case X86::SUBrr8: NI = MakeMRInst(X86::SUBmr8 , FrameIndex, MI); break;
166 case X86::SUBrr16: NI = MakeMRInst(X86::SUBmr16, FrameIndex, MI); break;
167 case X86::SUBrr32: NI = MakeMRInst(X86::SUBmr32, FrameIndex, MI); break;
168 case X86::SBBrr32: NI = MakeMRInst(X86::SBBmr32, FrameIndex, MI); break;
169 case X86::SUBri8: NI = MakeMIInst(X86::SUBmi8 , FrameIndex, MI); break;
170 case X86::SUBri16: NI = MakeMIInst(X86::SUBmi16, FrameIndex, MI); break;
171 case X86::SUBri32: NI = MakeMIInst(X86::SUBmi32, FrameIndex, MI); break;
172 case X86::ANDrr8: NI = MakeMRInst(X86::ANDmr8 , FrameIndex, MI); break;
173 case X86::ANDrr16: NI = MakeMRInst(X86::ANDmr16, FrameIndex, MI); break;
174 case X86::ANDrr32: NI = MakeMRInst(X86::ANDmr32, FrameIndex, MI); break;
175 case X86::ANDri8: NI = MakeMIInst(X86::ANDmi8 , FrameIndex, MI); break;
176 case X86::ANDri16: NI = MakeMIInst(X86::ANDmi16, FrameIndex, MI); break;
177 case X86::ANDri32: NI = MakeMIInst(X86::ANDmi32, FrameIndex, MI); break;
178 case X86::ORrr8: NI = MakeMRInst(X86::ORmr8 , FrameIndex, MI); break;
179 case X86::ORrr16: NI = MakeMRInst(X86::ORmr16, FrameIndex, MI); break;
180 case X86::ORrr32: NI = MakeMRInst(X86::ORmr32, FrameIndex, MI); break;
181 case X86::ORri8: NI = MakeMIInst(X86::ORmi8 , FrameIndex, MI); break;
182 case X86::ORri16: NI = MakeMIInst(X86::ORmi16, FrameIndex, MI); break;
183 case X86::ORri32: NI = MakeMIInst(X86::ORmi32, FrameIndex, MI); break;
184 case X86::XORrr8: NI = MakeMRInst(X86::XORmr8 , FrameIndex, MI); break;
185 case X86::XORrr16: NI = MakeMRInst(X86::XORmr16, FrameIndex, MI); break;
186 case X86::XORrr32: NI = MakeMRInst(X86::XORmr32, FrameIndex, MI); break;
187 case X86::XORri8: NI = MakeMIInst(X86::XORmi8 , FrameIndex, MI); break;
188 case X86::XORri16: NI = MakeMIInst(X86::XORmi16, FrameIndex, MI); break;
189 case X86::XORri32: NI = MakeMIInst(X86::XORmi32, FrameIndex, MI); break;
190 case X86::CMPrr8: NI = MakeMRInst(X86::CMPmr8 , FrameIndex, MI); break;
191 case X86::CMPrr16: NI = MakeMRInst(X86::CMPmr16, FrameIndex, MI); break;
192 case X86::CMPrr32: NI = MakeMRInst(X86::CMPmr32, FrameIndex, MI); break;
193 case X86::CMPri8: NI = MakeMIInst(X86::CMPmi8 , FrameIndex, MI); break;
194 case X86::CMPri16: NI = MakeMIInst(X86::CMPmi16, FrameIndex, MI); break;
195 case X86::CMPri32: NI = MakeMIInst(X86::CMPmi32, FrameIndex, MI); break;
196 default: break; // Cannot fold
199 switch(MI->getOpcode()) {
200 case X86::MOVrr8: NI = MakeRMInst(X86::MOVrm8 , FrameIndex, MI); break;
201 case X86::MOVrr16: NI = MakeRMInst(X86::MOVrm16, FrameIndex, MI); break;
202 case X86::MOVrr32: NI = MakeRMInst(X86::MOVrm32, FrameIndex, MI); break;
203 case X86::ADDrr8: NI = MakeRMInst(X86::ADDrm8 , FrameIndex, MI); break;
204 case X86::ADDrr16: NI = MakeRMInst(X86::ADDrm16, FrameIndex, MI); break;
205 case X86::ADDrr32: NI = MakeRMInst(X86::ADDrm32, FrameIndex, MI); break;
206 case X86::ADCrr32: NI = MakeRMInst(X86::ADCrm32, FrameIndex, MI); break;
207 case X86::SUBrr8: NI = MakeRMInst(X86::SUBrm8 , FrameIndex, MI); break;
208 case X86::SUBrr16: NI = MakeRMInst(X86::SUBrm16, FrameIndex, MI); break;
209 case X86::SUBrr32: NI = MakeRMInst(X86::SUBrm32, FrameIndex, MI); break;
210 case X86::SBBrr32: NI = MakeRMInst(X86::SBBrm32, FrameIndex, MI); break;
211 case X86::ANDrr8: NI = MakeRMInst(X86::ANDrm8 , FrameIndex, MI); break;
212 case X86::ANDrr16: NI = MakeRMInst(X86::ANDrm16, FrameIndex, MI); break;
213 case X86::ANDrr32: NI = MakeRMInst(X86::ANDrm32, FrameIndex, MI); break;
214 case X86::ORrr8: NI = MakeRMInst(X86::ORrm8 , FrameIndex, MI); break;
215 case X86::ORrr16: NI = MakeRMInst(X86::ORrm16, FrameIndex, MI); break;
216 case X86::ORrr32: NI = MakeRMInst(X86::ORrm32, FrameIndex, MI); break;
217 case X86::XORrr8: NI = MakeRMInst(X86::XORrm8 , FrameIndex, MI); break;
218 case X86::XORrr16: NI = MakeRMInst(X86::XORrm16, FrameIndex, MI); break;
219 case X86::XORrr32: NI = MakeRMInst(X86::XORrm32, FrameIndex, MI); break;
220 case X86::IMULrr16:NI = MakeRMInst(X86::IMULrm16, FrameIndex, MI); break;
221 case X86::IMULrr32:NI = MakeRMInst(X86::IMULrm32, FrameIndex, MI); break;
222 case X86::IMULrri16: NI = MakeRMIInst(X86::IMULrmi16, FrameIndex, MI);break;
223 case X86::IMULrri32: NI = MakeRMIInst(X86::IMULrmi32, FrameIndex, MI);break;
224 case X86::CMPrr8: NI = MakeRMInst(X86::CMPrm8 , FrameIndex, MI); break;
225 case X86::CMPrr16: NI = MakeRMInst(X86::CMPrm16, FrameIndex, MI); break;
226 case X86::CMPrr32: NI = MakeRMInst(X86::CMPrm32, FrameIndex, MI); break;
228 case X86::MOVSXr16r8: NI = MakeRMInst(X86::MOVSXr16m8 , FrameIndex, MI); break;
229 case X86::MOVSXr32r8: NI = MakeRMInst(X86::MOVSXr32m8, FrameIndex, MI); break;
230 case X86::MOVSXr32r16:NI = MakeRMInst(X86::MOVSXr32m16, FrameIndex, MI); break;
231 case X86::MOVZXr16r8: NI = MakeRMInst(X86::MOVZXr16m8 , FrameIndex, MI); break;
232 case X86::MOVZXr32r8: NI = MakeRMInst(X86::MOVZXr32m8, FrameIndex, MI); break;
233 case X86::MOVZXr32r16:NI = MakeRMInst(X86::MOVZXr32m16, FrameIndex, MI); break;
238 MI = MBB.insert(MBB.erase(MI), NI);
241 if (PrintFailedFusing)
242 std::cerr << "We failed to fuse: " << *MI;
247 //===----------------------------------------------------------------------===//
248 // Stack Frame Processing methods
249 //===----------------------------------------------------------------------===//
251 // hasFP - Return true if the specified function should have a dedicated frame
252 // pointer register. This is true if the function has variable sized allocas or
253 // if frame pointer elimination is disabled.
255 static bool hasFP(MachineFunction &MF) {
256 return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
259 void X86RegisterInfo::
260 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
261 MachineBasicBlock::iterator I) const {
263 // If we have a frame pointer, turn the adjcallstackup instruction into a
264 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
266 MachineInstr *Old = I;
267 unsigned Amount = Old->getOperand(0).getImmedValue();
269 // We need to keep the stack aligned properly. To do this, we round the
270 // amount of space needed for the outgoing arguments up to the next
271 // alignment boundary.
272 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
273 Amount = (Amount+Align-1)/Align*Align;
276 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
277 New=BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
279 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
280 New=BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
283 // Replace the pseudo instruction with a new instruction...
291 void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
292 MachineBasicBlock::iterator II) const {
294 MachineInstr &MI = *II;
295 while (!MI.getOperand(i).isFrameIndex()) {
297 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
300 int FrameIndex = MI.getOperand(i).getFrameIndex();
302 // This must be part of a four operand memory reference. Replace the
303 // FrameIndex with base register with EBP. Add add an offset to the offset.
304 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
306 // Now add the frame object offset to the offset from EBP.
307 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
308 MI.getOperand(i+3).getImmedValue()+4;
311 Offset += MF.getFrameInfo()->getStackSize();
313 Offset += 4; // Skip the saved EBP
315 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
319 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
321 // Create a frame entry for the EBP register that must be saved.
322 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
323 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
324 "Slot for EBP register must be last in order to be found!");
328 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
329 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
330 MachineBasicBlock::iterator MBBI = MBB.begin();
331 MachineFrameInfo *MFI = MF.getFrameInfo();
334 // Get the number of bytes to allocate from the FrameInfo
335 unsigned NumBytes = MFI->getStackSize();
337 // Get the offset of the stack slot for the EBP register... which is
338 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
339 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
341 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
342 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
343 MBB.insert(MBBI, MI);
346 // Save EBP into the appropriate stack slot...
347 MI = addRegOffset(BuildMI(X86::MOVmr32, 5), // mov [ESP-<offset>], EBP
348 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
349 MBB.insert(MBBI, MI);
351 // Update EBP with the new base value...
352 if (NumBytes == 4) // mov EBP, ESP
353 MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
354 else // lea EBP, [ESP+StackSize]
355 MI = addRegOffset(BuildMI(X86::LEAr32, 5, X86::EBP), X86::ESP,NumBytes-4);
357 MBB.insert(MBBI, MI);
360 if (MFI->hasCalls()) {
361 // When we have no frame pointer, we reserve argument space for call sites
362 // in the function immediately on entry to the current function. This
363 // eliminates the need for add/sub ESP brackets around call sites.
365 NumBytes += MFI->getMaxCallFrameSize();
367 // Round the size to a multiple of the alignment (don't forget the 4 byte
369 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
370 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
373 // Update frame info to pretend that this is part of the stack...
374 MFI->setStackSize(NumBytes);
377 // adjust stack pointer: ESP -= numbytes
378 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
379 MBB.insert(MBBI, MI);
384 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
385 MachineBasicBlock &MBB) const {
386 const MachineFrameInfo *MFI = MF.getFrameInfo();
387 MachineBasicBlock::iterator MBBI = prior(MBB.end());
389 assert(MBBI->getOpcode() == X86::RET &&
390 "Can only insert epilog into returning blocks");
393 // Get the offset of the stack slot for the EBP register... which is
394 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
395 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
398 MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
399 MBB.insert(MBBI, MI);
402 MI = BuildMI(X86::POPr32, 0, X86::EBP);
403 MBB.insert(MBBI, MI);
405 // Get the number of bytes allocated from the FrameInfo...
406 unsigned NumBytes = MFI->getStackSize();
408 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
409 MI =BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
410 MBB.insert(MBBI, MI);
415 #include "X86GenRegisterInfo.inc"
417 const TargetRegisterClass*
418 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
419 switch (Ty->getPrimitiveID()) {
421 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
422 default: assert(0 && "Invalid type to getClass!");
424 case Type::SByteTyID:
425 case Type::UByteTyID: return &R8Instance;
426 case Type::ShortTyID:
427 case Type::UShortTyID: return &R16Instance;
430 case Type::PointerTyID: return &R32Instance;
432 case Type::FloatTyID:
433 case Type::DoubleTyID: return &RFPInstance;