1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
41 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
42 const TargetInstrInfo &tii)
43 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
45 // Cache some information.
46 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
47 Is64Bit = Subtarget->is64Bit();
48 IsWin64 = Subtarget->isTargetWin64();
49 StackAlign = TM.getFrameInfo()->getStackAlignment();
61 // getDwarfRegNum - This function maps LLVM register identifiers to the
62 // Dwarf specific numbering, used in debug info and exception tables.
64 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
65 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
66 unsigned Flavour = DWARFFlavour::X86_64;
67 if (!Subtarget->is64Bit()) {
68 if (Subtarget->isTargetDarwin()) {
70 Flavour = DWARFFlavour::X86_32_DarwinEH;
72 Flavour = DWARFFlavour::X86_32_Generic;
73 } else if (Subtarget->isTargetCygMing()) {
74 // Unsupported by now, just quick fallback
75 Flavour = DWARFFlavour::X86_32_Generic;
77 Flavour = DWARFFlavour::X86_32_Generic;
81 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
84 // getX86RegNum - This function maps LLVM register identifiers to their X86
85 // specific numbering, which is used in various places encoding instructions.
87 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
89 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
90 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
91 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
92 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
93 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
95 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
97 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
99 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
102 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
106 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
108 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
110 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
112 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
114 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
116 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
119 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
120 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
121 return RegNo-X86::ST0;
123 case X86::XMM0: case X86::XMM8: case X86::MM0:
125 case X86::XMM1: case X86::XMM9: case X86::MM1:
127 case X86::XMM2: case X86::XMM10: case X86::MM2:
129 case X86::XMM3: case X86::XMM11: case X86::MM3:
131 case X86::XMM4: case X86::XMM12: case X86::MM4:
133 case X86::XMM5: case X86::XMM13: case X86::MM5:
135 case X86::XMM6: case X86::XMM14: case X86::MM6:
137 case X86::XMM7: case X86::XMM15: case X86::MM7:
141 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
142 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
147 const TargetRegisterClass *
148 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
149 if (RC == &X86::CCRRegClass) {
151 return &X86::GR64RegClass;
153 return &X86::GR32RegClass;
159 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
160 static const unsigned CalleeSavedRegs32Bit[] = {
161 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
164 static const unsigned CalleeSavedRegs32EHRet[] = {
165 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
168 static const unsigned CalleeSavedRegs64Bit[] = {
169 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
172 static const unsigned CalleeSavedRegsWin64[] = {
173 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
174 X86::R12, X86::R13, X86::R14, X86::R15, 0
179 return CalleeSavedRegsWin64;
181 return CalleeSavedRegs64Bit;
184 MachineFrameInfo *MFI = MF->getFrameInfo();
185 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
186 if (MMI && MMI->callsEHReturn())
187 return CalleeSavedRegs32EHRet;
189 return CalleeSavedRegs32Bit;
193 const TargetRegisterClass* const*
194 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
195 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
196 &X86::GR32RegClass, &X86::GR32RegClass,
197 &X86::GR32RegClass, &X86::GR32RegClass, 0
199 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
200 &X86::GR32RegClass, &X86::GR32RegClass,
201 &X86::GR32RegClass, &X86::GR32RegClass,
202 &X86::GR32RegClass, &X86::GR32RegClass, 0
204 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
205 &X86::GR64RegClass, &X86::GR64RegClass,
206 &X86::GR64RegClass, &X86::GR64RegClass,
207 &X86::GR64RegClass, &X86::GR64RegClass, 0
209 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
210 &X86::GR64RegClass, &X86::GR64RegClass,
211 &X86::GR64RegClass, &X86::GR64RegClass,
212 &X86::GR64RegClass, &X86::GR64RegClass,
213 &X86::GR64RegClass, &X86::GR64RegClass, 0
218 return CalleeSavedRegClassesWin64;
220 return CalleeSavedRegClasses64Bit;
223 MachineFrameInfo *MFI = MF->getFrameInfo();
224 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225 if (MMI && MMI->callsEHReturn())
226 return CalleeSavedRegClasses32EHRet;
228 return CalleeSavedRegClasses32Bit;
233 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
234 BitVector Reserved(getNumRegs());
235 Reserved.set(X86::RSP);
236 Reserved.set(X86::ESP);
237 Reserved.set(X86::SP);
238 Reserved.set(X86::SPL);
240 Reserved.set(X86::RBP);
241 Reserved.set(X86::EBP);
242 Reserved.set(X86::BP);
243 Reserved.set(X86::BPL);
248 //===----------------------------------------------------------------------===//
249 // Stack Frame Processing methods
250 //===----------------------------------------------------------------------===//
252 // hasFP - Return true if the specified function should have a dedicated frame
253 // pointer register. This is true if the function has variable sized allocas or
254 // if frame pointer elimination is disabled.
256 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
257 MachineFrameInfo *MFI = MF.getFrameInfo();
258 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
260 return (NoFramePointerElim ||
261 needsStackRealignment(MF) ||
262 MFI->hasVarSizedObjects() ||
263 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
264 (MMI && MMI->callsUnwindInit()));
267 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
268 MachineFrameInfo *MFI = MF.getFrameInfo();;
270 // FIXME: Currently we don't support stack realignment for functions with
271 // variable-sized allocas
272 return (RealignStack &&
273 (MFI->getMaxAlignment() > StackAlign &&
274 !MFI->hasVarSizedObjects()));
277 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
278 return !MF.getFrameInfo()->hasVarSizedObjects();
282 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
283 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
285 return Offset + MF.getFrameInfo()->getStackSize();
287 Offset += SlotSize; // Skip the saved EBP
288 // Skip the RETADDR move area
289 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
290 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
291 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
295 void X86RegisterInfo::
296 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
297 MachineBasicBlock::iterator I) const {
298 if (!hasReservedCallFrame(MF)) {
299 // If the stack pointer can be changed after prologue, turn the
300 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
301 // adjcallstackdown instruction into 'add ESP, <amt>'
302 // TODO: consider using push / pop instead of sub + store / add
303 MachineInstr *Old = I;
304 uint64_t Amount = Old->getOperand(0).getImm();
306 // We need to keep the stack aligned properly. To do this, we round the
307 // amount of space needed for the outgoing arguments up to the next
308 // alignment boundary.
309 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
311 MachineInstr *New = 0;
312 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
313 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
314 .addReg(StackPtr).addImm(Amount);
316 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
317 // factor out the amount the callee already popped.
318 uint64_t CalleeAmt = Old->getOperand(1).getImm();
321 unsigned Opc = (Amount < 128) ?
322 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
323 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
324 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
328 // Replace the pseudo instruction with a new instruction...
329 if (New) MBB.insert(I, New);
331 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
332 // If we are performing frame pointer elimination and if the callee pops
333 // something off the stack pointer, add it back. We do this until we have
334 // more advanced stack pointer tracking ability.
335 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
336 unsigned Opc = (CalleeAmt < 128) ?
337 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
338 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
340 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
348 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
349 int SPAdj, RegScavenger *RS) const{
350 assert(SPAdj == 0 && "Unexpected");
353 MachineInstr &MI = *II;
354 MachineFunction &MF = *MI.getParent()->getParent();
355 while (!MI.getOperand(i).isFrameIndex()) {
357 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
360 int FrameIndex = MI.getOperand(i).getIndex();
361 // This must be part of a four operand memory reference. Replace the
362 // FrameIndex with base register with EBP. Add an offset to the offset.
363 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
365 // Now add the frame object offset to the offset from EBP.
366 int64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
367 MI.getOperand(i+3).getImm();
369 MI.getOperand(i+3).ChangeToImmediate(Offset);
373 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
374 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
375 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
376 if (TailCallReturnAddrDelta < 0) {
377 // create RETURNADDR area
387 CreateFixedObject(-TailCallReturnAddrDelta,
388 (-1*SlotSize)+TailCallReturnAddrDelta);
391 assert((TailCallReturnAddrDelta <= 0) &&
392 "The Delta should always be zero or negative");
393 // Create a frame entry for the EBP register that must be saved.
394 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
396 TailCallReturnAddrDelta);
397 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
398 "Slot for EBP register must be last in order to be found!");
402 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
403 /// stack pointer by a constant value.
405 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
406 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
407 const TargetInstrInfo &TII) {
408 bool isSub = NumBytes < 0;
409 uint64_t Offset = isSub ? -NumBytes : NumBytes;
412 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
413 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
415 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
416 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
417 uint64_t Chunk = (1LL << 31) - 1;
420 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
421 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
426 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
428 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
429 unsigned StackPtr, uint64_t *NumBytes = NULL) {
430 if (MBBI == MBB.begin()) return;
432 MachineBasicBlock::iterator PI = prior(MBBI);
433 unsigned Opc = PI->getOpcode();
434 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
435 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
436 PI->getOperand(0).getReg() == StackPtr) {
438 *NumBytes += PI->getOperand(2).getImm();
440 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
441 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
442 PI->getOperand(0).getReg() == StackPtr) {
444 *NumBytes -= PI->getOperand(2).getImm();
449 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
451 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
452 MachineBasicBlock::iterator &MBBI,
453 unsigned StackPtr, uint64_t *NumBytes = NULL) {
456 if (MBBI == MBB.end()) return;
458 MachineBasicBlock::iterator NI = next(MBBI);
459 if (NI == MBB.end()) return;
461 unsigned Opc = NI->getOpcode();
462 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
463 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
464 NI->getOperand(0).getReg() == StackPtr) {
466 *NumBytes -= NI->getOperand(2).getImm();
469 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
470 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
471 NI->getOperand(0).getReg() == StackPtr) {
473 *NumBytes += NI->getOperand(2).getImm();
479 /// mergeSPUpdates - Checks the instruction before/after the passed
480 /// instruction. If it is an ADD/SUB instruction it is deleted
481 /// argument and the stack adjustment is returned as a positive value for ADD
482 /// and a negative for SUB.
483 static int mergeSPUpdates(MachineBasicBlock &MBB,
484 MachineBasicBlock::iterator &MBBI,
486 bool doMergeWithPrevious) {
488 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
489 (!doMergeWithPrevious && MBBI == MBB.end()))
494 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
495 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
496 unsigned Opc = PI->getOpcode();
497 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
498 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
499 PI->getOperand(0).getReg() == StackPtr){
500 Offset += PI->getOperand(2).getImm();
502 if (!doMergeWithPrevious) MBBI = NI;
503 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
504 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
505 PI->getOperand(0).getReg() == StackPtr) {
506 Offset -= PI->getOperand(2).getImm();
508 if (!doMergeWithPrevious) MBBI = NI;
514 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
515 unsigned FrameLabelId,
516 unsigned ReadyLabelId) const {
517 MachineFrameInfo *MFI = MF.getFrameInfo();
518 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
522 uint64_t StackSize = MFI->getStackSize();
523 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
524 const TargetData *TD = MF.getTarget().getTargetData();
526 // Calculate amount of bytes used for return address storing
528 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
529 TargetFrameInfo::StackGrowsUp ?
530 TD->getPointerSize() : -TD->getPointerSize());
533 // Show update of SP.
536 MachineLocation SPDst(MachineLocation::VirtualFP);
537 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
538 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
540 MachineLocation SPDst(MachineLocation::VirtualFP);
541 MachineLocation SPSrc(MachineLocation::VirtualFP,
542 -StackSize+stackGrowth);
543 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
546 //FIXME: Verify & implement for FP
547 MachineLocation SPDst(StackPtr);
548 MachineLocation SPSrc(StackPtr, stackGrowth);
549 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
552 // Add callee saved registers to move list.
553 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
555 // FIXME: This is dirty hack. The code itself is pretty mess right now.
556 // It should be rewritten from scratch and generalized sometimes.
558 // Determine maximum offset (minumum due to stack growth)
559 int64_t MaxOffset = 0;
560 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
561 MaxOffset = std::min(MaxOffset,
562 MFI->getObjectOffset(CSI[I].getFrameIdx()));
565 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
566 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
567 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
568 unsigned Reg = CSI[I].getReg();
569 Offset = (MaxOffset-Offset+saveAreaOffset);
570 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
571 MachineLocation CSSrc(Reg);
572 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
577 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
578 MachineLocation FPSrc(FramePtr);
579 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
582 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
583 MachineLocation FPSrc(MachineLocation::VirtualFP);
584 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
588 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
589 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
590 MachineFrameInfo *MFI = MF.getFrameInfo();
591 const Function* Fn = MF.getFunction();
592 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
593 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
594 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
595 MachineBasicBlock::iterator MBBI = MBB.begin();
596 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
597 !Fn->doesNotThrow() ||
598 UnwindTablesMandatory;
599 // Prepare for frame info.
600 unsigned FrameLabelId = 0;
602 // Get the number of bytes to allocate from the FrameInfo.
603 uint64_t StackSize = MFI->getStackSize();
604 // Add RETADDR move area to callee saved frame size.
605 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
606 if (TailCallReturnAddrDelta < 0)
607 X86FI->setCalleeSavedFrameSize(
608 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
609 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
611 // Insert stack pointer adjustment for later moving of return addr. Only
612 // applies to tail call optimized functions where the callee argument stack
613 // size is bigger than the callers.
614 if (TailCallReturnAddrDelta < 0) {
615 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
616 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
620 // Get the offset of the stack slot for the EBP register... which is
621 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
622 // Update the frame offset adjustment.
623 MFI->setOffsetAdjustment(SlotSize-NumBytes);
625 // Save EBP into the appropriate stack slot...
626 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
628 NumBytes -= SlotSize;
630 if (needsFrameMoves) {
631 // Mark effective beginning of when frame pointer becomes valid.
632 FrameLabelId = MMI->NextLabelID();
633 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
636 // Update EBP with the new base value...
637 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
641 unsigned ReadyLabelId = 0;
642 if (needsFrameMoves) {
643 // Mark effective beginning of when frame pointer is ready.
644 ReadyLabelId = MMI->NextLabelID();
645 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
648 // Skip the callee-saved push instructions.
649 while (MBBI != MBB.end() &&
650 (MBBI->getOpcode() == X86::PUSH32r ||
651 MBBI->getOpcode() == X86::PUSH64r))
654 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
655 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
656 // Check, whether EAX is livein for this function
657 bool isEAXAlive = false;
658 for (MachineRegisterInfo::livein_iterator
659 II = MF.getRegInfo().livein_begin(),
660 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
661 unsigned Reg = II->first;
662 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
663 Reg == X86::AH || Reg == X86::AL);
666 // Function prologue calls _alloca to probe the stack when allocating
667 // more than 4k bytes in one go. Touching the stack at 4K increments is
668 // necessary to ensure that the guard pages used by the OS virtual memory
669 // manager are allocated in correct sequence.
671 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
672 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
673 .addExternalSymbol("_alloca");
676 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
677 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
678 // allocated bytes for EAX.
679 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
680 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
681 .addExternalSymbol("_alloca");
683 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
684 StackPtr, NumBytes-4);
685 MBB.insert(MBBI, MI);
688 // If there is an SUB32ri of ESP immediately before this instruction,
689 // merge the two. This can be the case when tail call elimination is
690 // enabled and the callee has more arguments then the caller.
691 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
692 // If there is an ADD32ri or SUB32ri of ESP immediately after this
693 // instruction, merge the two instructions.
694 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
697 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
702 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
704 // If it's main() on Cygwin\Mingw32 we should align stack as well
705 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
706 Subtarget->isTargetCygMing()) {
707 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
708 .addReg(X86::ESP).addImm(-StackAlign);
711 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
712 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
716 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
717 MachineBasicBlock &MBB) const {
718 const MachineFrameInfo *MFI = MF.getFrameInfo();
719 const Function* Fn = MF.getFunction();
720 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
721 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
722 MachineBasicBlock::iterator MBBI = prior(MBB.end());
723 unsigned RetOpcode = MBBI->getOpcode();
728 case X86::TCRETURNdi:
729 case X86::TCRETURNri:
730 case X86::TCRETURNri64:
731 case X86::TCRETURNdi64:
735 case X86::TAILJMPm: break; // These are ok
737 assert(0 && "Can only insert epilog into returning blocks");
740 // Get the number of bytes to allocate from the FrameInfo
741 uint64_t StackSize = MFI->getStackSize();
742 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
743 uint64_t NumBytes = StackSize - CSSize;
747 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
748 NumBytes -= SlotSize;
751 // Skip the callee-saved pop instructions.
752 while (MBBI != MBB.begin()) {
753 MachineBasicBlock::iterator PI = prior(MBBI);
754 unsigned Opc = PI->getOpcode();
755 if (Opc != X86::POP32r && Opc != X86::POP64r &&
756 !PI->getDesc().isTerminator())
761 // If there is an ADD32ri or SUB32ri of ESP immediately before this
762 // instruction, merge the two instructions.
763 if (NumBytes || MFI->hasVarSizedObjects())
764 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
766 // If dynamic alloca is used, then reset esp to point to the last callee-saved
767 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
768 // aligned stack in the prologue, - revert stack changes back. Note: we're
769 // assuming, that frame pointer was forced for main()
770 if (MFI->hasVarSizedObjects() ||
771 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
772 Subtarget->isTargetCygMing())) {
773 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
775 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
777 MBB.insert(MBBI, MI);
779 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
785 // adjust stack pointer back: ESP += numbytes
787 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
789 // We're returning from function via eh_return.
790 if (RetOpcode == X86::EH_RETURN) {
791 MBBI = prior(MBB.end());
792 MachineOperand &DestAddr = MBBI->getOperand(0);
793 assert(DestAddr.isRegister() && "Offset should be in register!");
794 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
795 addReg(DestAddr.getReg());
796 // Tail call return: adjust the stack pointer and jump to callee
797 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
798 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
799 MBBI = prior(MBB.end());
800 MachineOperand &JumpTarget = MBBI->getOperand(0);
801 MachineOperand &StackAdjust = MBBI->getOperand(1);
802 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
804 // Adjust stack pointer.
805 int StackAdj = StackAdjust.getImm();
806 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
808 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
809 // Incoporate the retaddr area.
810 Offset = StackAdj-MaxTCDelta;
811 assert(Offset >= 0 && "Offset should never be negative");
813 // Check for possible merge with preceeding ADD instruction.
814 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
815 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
817 // Jump to label or value in register.
818 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
819 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
820 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
821 else if (RetOpcode== X86::TCRETURNri64) {
822 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
824 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
825 // Delete the pseudo instruction TCRETURN.
827 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
828 (X86FI->getTCReturnAddrDelta() < 0)) {
829 // Add the return addr area delta back since we are not tail calling.
830 int delta = -1*X86FI->getTCReturnAddrDelta();
831 MBBI = prior(MBB.end());
832 // Check for possible merge with preceeding ADD instruction.
833 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
834 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
838 unsigned X86RegisterInfo::getRARegister() const {
840 return X86::RIP; // Should have dwarf #16
842 return X86::EIP; // Should have dwarf #8
845 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
846 return hasFP(MF) ? FramePtr : StackPtr;
849 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
851 // Calculate amount of bytes used for return address storing
852 int stackGrowth = (Is64Bit ? -8 : -4);
854 // Initial state of the frame pointer is esp+4.
855 MachineLocation Dst(MachineLocation::VirtualFP);
856 MachineLocation Src(StackPtr, stackGrowth);
857 Moves.push_back(MachineMove(0, Dst, Src));
859 // Add return address to move list
860 MachineLocation CSDst(StackPtr, stackGrowth);
861 MachineLocation CSSrc(getRARegister());
862 Moves.push_back(MachineMove(0, CSDst, CSSrc));
865 unsigned X86RegisterInfo::getEHExceptionRegister() const {
866 assert(0 && "What is the exception register");
870 unsigned X86RegisterInfo::getEHHandlerRegister() const {
871 assert(0 && "What is the exception handler register");
876 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
883 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
885 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
887 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
889 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
895 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
897 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
899 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
901 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
903 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
905 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
907 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
909 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
911 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
913 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
915 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
917 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
919 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
921 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
923 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
925 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
932 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
934 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
936 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
938 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
940 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
942 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
944 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
946 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
948 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
950 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
952 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
954 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
956 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
958 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
960 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
962 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
968 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
970 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
972 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
974 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
976 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
978 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
980 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
982 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
984 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
986 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
988 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
990 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
992 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
994 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
996 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
998 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1003 default: return Reg;
1004 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1006 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1008 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1010 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1012 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1014 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1016 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1018 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1020 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1022 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1024 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1026 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1028 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1030 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1032 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1034 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1043 #include "X86GenRegisterInfo.inc"