1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
47 // Cache some information.
48 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
49 Is64Bit = Subtarget->is64Bit();
50 IsWin64 = Subtarget->isTargetWin64();
51 StackAlign = TM.getFrameInfo()->getStackAlignment();
63 // getDwarfRegNum - This function maps LLVM register identifiers to the
64 // Dwarf specific numbering, used in debug info and exception tables.
66 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
67 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
68 unsigned Flavour = DWARFFlavour::X86_64;
69 if (!Subtarget->is64Bit()) {
70 if (Subtarget->isTargetDarwin()) {
72 Flavour = DWARFFlavour::X86_32_DarwinEH;
74 Flavour = DWARFFlavour::X86_32_Generic;
75 } else if (Subtarget->isTargetCygMing()) {
76 // Unsupported by now, just quick fallback
77 Flavour = DWARFFlavour::X86_32_Generic;
79 Flavour = DWARFFlavour::X86_32_Generic;
83 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
86 // getX86RegNum - This function maps LLVM register identifiers to their X86
87 // specific numbering, which is used in various places encoding instructions.
89 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
91 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
92 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
93 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
94 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
95 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
97 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
99 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
101 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
104 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
106 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
108 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
110 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
112 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
114 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
116 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
118 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
121 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
122 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
123 return RegNo-X86::ST0;
125 case X86::XMM0: case X86::XMM8: case X86::MM0:
127 case X86::XMM1: case X86::XMM9: case X86::MM1:
129 case X86::XMM2: case X86::XMM10: case X86::MM2:
131 case X86::XMM3: case X86::XMM11: case X86::MM3:
133 case X86::XMM4: case X86::XMM12: case X86::MM4:
135 case X86::XMM5: case X86::XMM13: case X86::MM5:
137 case X86::XMM6: case X86::XMM14: case X86::MM6:
139 case X86::XMM7: case X86::XMM15: case X86::MM7:
143 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
144 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
149 const TargetRegisterClass *
150 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
151 if (RC == &X86::CCRRegClass) {
153 return &X86::GR64RegClass;
155 return &X86::GR32RegClass;
161 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
162 static const unsigned CalleeSavedRegs32Bit[] = {
163 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
166 static const unsigned CalleeSavedRegs32EHRet[] = {
167 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
170 static const unsigned CalleeSavedRegs64Bit[] = {
171 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
174 static const unsigned CalleeSavedRegsWin64[] = {
175 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
176 X86::R12, X86::R13, X86::R14, X86::R15, 0
181 return CalleeSavedRegsWin64;
183 return CalleeSavedRegs64Bit;
186 const MachineFrameInfo *MFI = MF->getFrameInfo();
187 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
188 if (MMI && MMI->callsEHReturn())
189 return CalleeSavedRegs32EHRet;
191 return CalleeSavedRegs32Bit;
195 const TargetRegisterClass* const*
196 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
197 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
198 &X86::GR32RegClass, &X86::GR32RegClass,
199 &X86::GR32RegClass, &X86::GR32RegClass, 0
201 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
202 &X86::GR32RegClass, &X86::GR32RegClass,
203 &X86::GR32RegClass, &X86::GR32RegClass,
204 &X86::GR32RegClass, &X86::GR32RegClass, 0
206 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
207 &X86::GR64RegClass, &X86::GR64RegClass,
208 &X86::GR64RegClass, &X86::GR64RegClass,
209 &X86::GR64RegClass, &X86::GR64RegClass, 0
211 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
212 &X86::GR64RegClass, &X86::GR64RegClass,
213 &X86::GR64RegClass, &X86::GR64RegClass,
214 &X86::GR64RegClass, &X86::GR64RegClass,
215 &X86::GR64RegClass, &X86::GR64RegClass, 0
220 return CalleeSavedRegClassesWin64;
222 return CalleeSavedRegClasses64Bit;
225 const MachineFrameInfo *MFI = MF->getFrameInfo();
226 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
227 if (MMI && MMI->callsEHReturn())
228 return CalleeSavedRegClasses32EHRet;
230 return CalleeSavedRegClasses32Bit;
235 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
236 BitVector Reserved(getNumRegs());
237 Reserved.set(X86::RSP);
238 Reserved.set(X86::ESP);
239 Reserved.set(X86::SP);
240 Reserved.set(X86::SPL);
242 Reserved.set(X86::RBP);
243 Reserved.set(X86::EBP);
244 Reserved.set(X86::BP);
245 Reserved.set(X86::BPL);
250 //===----------------------------------------------------------------------===//
251 // Stack Frame Processing methods
252 //===----------------------------------------------------------------------===//
254 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
255 unsigned MaxAlign = 0;
256 for (int i = FFI->getObjectIndexBegin(),
257 e = FFI->getObjectIndexEnd(); i != e; ++i) {
258 if (FFI->isDeadObjectIndex(i))
260 unsigned Align = FFI->getObjectAlignment(i);
261 MaxAlign = std::max(MaxAlign, Align);
267 // hasFP - Return true if the specified function should have a dedicated frame
268 // pointer register. This is true if the function has variable sized allocas or
269 // if frame pointer elimination is disabled.
271 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
272 const MachineFrameInfo *MFI = MF.getFrameInfo();
273 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
275 return (NoFramePointerElim ||
276 needsStackRealignment(MF) ||
277 MFI->hasVarSizedObjects() ||
278 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
279 (MMI && MMI->callsUnwindInit()));
282 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
283 const MachineFrameInfo *MFI = MF.getFrameInfo();;
285 // FIXME: Currently we don't support stack realignment for functions with
286 // variable-sized allocas
287 return (RealignStack &&
288 (MFI->getMaxAlignment() > StackAlign &&
289 !MFI->hasVarSizedObjects()));
292 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
293 return !MF.getFrameInfo()->hasVarSizedObjects();
297 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
298 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
299 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
301 if (needsStackRealignment(MF)) {
303 // Skip the saved EBP
306 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
307 assert( (-(Offset + StackSize)) % Align == 0);
308 return Offset + StackSize;
311 // FIXME: Support tail calls
314 return Offset + StackSize;
316 // Skip the saved EBP
319 // Skip the RETADDR move area
320 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
321 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
322 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
328 void X86RegisterInfo::
329 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
330 MachineBasicBlock::iterator I) const {
331 if (!hasReservedCallFrame(MF)) {
332 // If the stack pointer can be changed after prologue, turn the
333 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
334 // adjcallstackdown instruction into 'add ESP, <amt>'
335 // TODO: consider using push / pop instead of sub + store / add
336 MachineInstr *Old = I;
337 uint64_t Amount = Old->getOperand(0).getImm();
339 // We need to keep the stack aligned properly. To do this, we round the
340 // amount of space needed for the outgoing arguments up to the next
341 // alignment boundary.
342 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
344 MachineInstr *New = 0;
345 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
346 New=BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
347 .addReg(StackPtr).addImm(Amount);
349 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
350 // factor out the amount the callee already popped.
351 uint64_t CalleeAmt = Old->getOperand(1).getImm();
354 unsigned Opc = (Amount < 128) ?
355 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
356 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
357 New = BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
361 // Replace the pseudo instruction with a new instruction...
362 if (New) MBB.insert(I, New);
364 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
365 // If we are performing frame pointer elimination and if the callee pops
366 // something off the stack pointer, add it back. We do this until we have
367 // more advanced stack pointer tracking ability.
368 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
369 unsigned Opc = (CalleeAmt < 128) ?
370 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
371 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
373 BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
381 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
382 int SPAdj, RegScavenger *RS) const{
383 assert(SPAdj == 0 && "Unexpected");
386 MachineInstr &MI = *II;
387 MachineFunction &MF = *MI.getParent()->getParent();
388 while (!MI.getOperand(i).isFrameIndex()) {
390 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
393 int FrameIndex = MI.getOperand(i).getIndex();
396 if (needsStackRealignment(MF))
397 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
399 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
401 // This must be part of a four operand memory reference. Replace the
402 // FrameIndex with base register with EBP. Add an offset to the offset.
403 MI.getOperand(i).ChangeToRegister(BasePtr, false);
405 // Now add the frame object offset to the offset from EBP.
406 int64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
407 MI.getOperand(i+3).getImm();
409 MI.getOperand(i+3).ChangeToImmediate(Offset);
413 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
414 RegScavenger *RS) const {
415 MachineFrameInfo *FFI = MF.getFrameInfo();
417 // Calculate and set max stack object alignment early, so we can decide
418 // whether we will need stack realignment (and thus FP).
419 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
420 calculateMaxStackAlignment(FFI));
422 FFI->setMaxAlignment(MaxAlign);
426 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
427 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
428 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
429 if (TailCallReturnAddrDelta < 0) {
430 // create RETURNADDR area
440 CreateFixedObject(-TailCallReturnAddrDelta,
441 (-1*SlotSize)+TailCallReturnAddrDelta);
444 assert((TailCallReturnAddrDelta <= 0) &&
445 "The Delta should always be zero or negative");
446 // Create a frame entry for the EBP register that must be saved.
447 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
449 TailCallReturnAddrDelta);
450 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
451 "Slot for EBP register must be last in order to be found!");
455 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
456 /// stack pointer by a constant value.
458 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
459 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
460 const TargetInstrInfo &TII) {
461 bool isSub = NumBytes < 0;
462 uint64_t Offset = isSub ? -NumBytes : NumBytes;
465 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
466 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
468 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
469 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
470 uint64_t Chunk = (1LL << 31) - 1;
473 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
474 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
479 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
481 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
482 unsigned StackPtr, uint64_t *NumBytes = NULL) {
483 if (MBBI == MBB.begin()) return;
485 MachineBasicBlock::iterator PI = prior(MBBI);
486 unsigned Opc = PI->getOpcode();
487 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
488 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
489 PI->getOperand(0).getReg() == StackPtr) {
491 *NumBytes += PI->getOperand(2).getImm();
493 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
494 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
495 PI->getOperand(0).getReg() == StackPtr) {
497 *NumBytes -= PI->getOperand(2).getImm();
502 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
504 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
505 MachineBasicBlock::iterator &MBBI,
506 unsigned StackPtr, uint64_t *NumBytes = NULL) {
509 if (MBBI == MBB.end()) return;
511 MachineBasicBlock::iterator NI = next(MBBI);
512 if (NI == MBB.end()) return;
514 unsigned Opc = NI->getOpcode();
515 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
516 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
517 NI->getOperand(0).getReg() == StackPtr) {
519 *NumBytes -= NI->getOperand(2).getImm();
522 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
523 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
524 NI->getOperand(0).getReg() == StackPtr) {
526 *NumBytes += NI->getOperand(2).getImm();
532 /// mergeSPUpdates - Checks the instruction before/after the passed
533 /// instruction. If it is an ADD/SUB instruction it is deleted
534 /// argument and the stack adjustment is returned as a positive value for ADD
535 /// and a negative for SUB.
536 static int mergeSPUpdates(MachineBasicBlock &MBB,
537 MachineBasicBlock::iterator &MBBI,
539 bool doMergeWithPrevious) {
541 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
542 (!doMergeWithPrevious && MBBI == MBB.end()))
547 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
548 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
549 unsigned Opc = PI->getOpcode();
550 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
551 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
552 PI->getOperand(0).getReg() == StackPtr){
553 Offset += PI->getOperand(2).getImm();
555 if (!doMergeWithPrevious) MBBI = NI;
556 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
557 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
558 PI->getOperand(0).getReg() == StackPtr) {
559 Offset -= PI->getOperand(2).getImm();
561 if (!doMergeWithPrevious) MBBI = NI;
567 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
568 unsigned FrameLabelId,
569 unsigned ReadyLabelId) const {
570 MachineFrameInfo *MFI = MF.getFrameInfo();
571 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
575 uint64_t StackSize = MFI->getStackSize();
576 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
577 const TargetData *TD = MF.getTarget().getTargetData();
579 // Calculate amount of bytes used for return address storing
581 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
582 TargetFrameInfo::StackGrowsUp ?
583 TD->getPointerSize() : -TD->getPointerSize());
586 // Show update of SP.
589 MachineLocation SPDst(MachineLocation::VirtualFP);
590 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
591 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
593 MachineLocation SPDst(MachineLocation::VirtualFP);
594 MachineLocation SPSrc(MachineLocation::VirtualFP,
595 -StackSize+stackGrowth);
596 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
599 //FIXME: Verify & implement for FP
600 MachineLocation SPDst(StackPtr);
601 MachineLocation SPSrc(StackPtr, stackGrowth);
602 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
605 // Add callee saved registers to move list.
606 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
608 // FIXME: This is dirty hack. The code itself is pretty mess right now.
609 // It should be rewritten from scratch and generalized sometimes.
611 // Determine maximum offset (minumum due to stack growth)
612 int64_t MaxOffset = 0;
613 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
614 MaxOffset = std::min(MaxOffset,
615 MFI->getObjectOffset(CSI[I].getFrameIdx()));
618 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
619 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
620 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
621 unsigned Reg = CSI[I].getReg();
622 Offset = (MaxOffset-Offset+saveAreaOffset);
623 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
624 MachineLocation CSSrc(Reg);
625 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
630 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
631 MachineLocation FPSrc(FramePtr);
632 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
635 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
636 MachineLocation FPSrc(MachineLocation::VirtualFP);
637 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
641 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
642 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
643 MachineFrameInfo *MFI = MF.getFrameInfo();
644 const Function* Fn = MF.getFunction();
645 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
646 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
647 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
648 MachineBasicBlock::iterator MBBI = MBB.begin();
649 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
650 !Fn->doesNotThrow() ||
651 UnwindTablesMandatory;
652 // Prepare for frame info.
653 unsigned FrameLabelId = 0;
655 // Get the number of bytes to allocate from the FrameInfo.
656 uint64_t StackSize = MFI->getStackSize();
657 // Get desired stack alignment
658 uint64_t MaxAlign = MFI->getMaxAlignment();
660 // Add RETADDR move area to callee saved frame size.
661 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
662 if (TailCallReturnAddrDelta < 0)
663 X86FI->setCalleeSavedFrameSize(
664 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
666 // Insert stack pointer adjustment for later moving of return addr. Only
667 // applies to tail call optimized functions where the callee argument stack
668 // size is bigger than the callers.
669 if (TailCallReturnAddrDelta < 0) {
670 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
671 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
674 uint64_t NumBytes = 0;
676 // Calculate required stack adjustment
677 uint64_t FrameSize = StackSize - SlotSize;
678 if (needsStackRealignment(MF))
679 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
681 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
683 // Get the offset of the stack slot for the EBP register... which is
684 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
685 // Update the frame offset adjustment.
686 MFI->setOffsetAdjustment(-NumBytes);
688 // Save EBP into the appropriate stack slot...
689 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
692 if (needsFrameMoves) {
693 // Mark effective beginning of when frame pointer becomes valid.
694 FrameLabelId = MMI->NextLabelID();
695 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
698 // Update EBP with the new base value...
699 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
703 if (needsStackRealignment(MF))
705 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
706 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
708 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
710 unsigned ReadyLabelId = 0;
711 if (needsFrameMoves) {
712 // Mark effective beginning of when frame pointer is ready.
713 ReadyLabelId = MMI->NextLabelID();
714 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
717 // Skip the callee-saved push instructions.
718 while (MBBI != MBB.end() &&
719 (MBBI->getOpcode() == X86::PUSH32r ||
720 MBBI->getOpcode() == X86::PUSH64r))
723 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
724 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
725 // Check, whether EAX is livein for this function
726 bool isEAXAlive = false;
727 for (MachineRegisterInfo::livein_iterator
728 II = MF.getRegInfo().livein_begin(),
729 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
730 unsigned Reg = II->first;
731 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
732 Reg == X86::AH || Reg == X86::AL);
735 // Function prologue calls _alloca to probe the stack when allocating
736 // more than 4k bytes in one go. Touching the stack at 4K increments is
737 // necessary to ensure that the guard pages used by the OS virtual memory
738 // manager are allocated in correct sequence.
740 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
741 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
742 .addExternalSymbol("_alloca");
745 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
746 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
747 // allocated bytes for EAX.
748 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
749 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
750 .addExternalSymbol("_alloca");
752 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
753 StackPtr, false, NumBytes-4);
754 MBB.insert(MBBI, MI);
757 // If there is an SUB32ri of ESP immediately before this instruction,
758 // merge the two. This can be the case when tail call elimination is
759 // enabled and the callee has more arguments then the caller.
760 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
761 // If there is an ADD32ri or SUB32ri of ESP immediately after this
762 // instruction, merge the two instructions.
763 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
766 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
771 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
774 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
775 MachineBasicBlock &MBB) const {
776 const MachineFrameInfo *MFI = MF.getFrameInfo();
777 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
778 MachineBasicBlock::iterator MBBI = prior(MBB.end());
779 unsigned RetOpcode = MBBI->getOpcode();
784 case X86::TCRETURNdi:
785 case X86::TCRETURNri:
786 case X86::TCRETURNri64:
787 case X86::TCRETURNdi64:
791 case X86::TAILJMPm: break; // These are ok
793 assert(0 && "Can only insert epilog into returning blocks");
796 // Get the number of bytes to allocate from the FrameInfo
797 uint64_t StackSize = MFI->getStackSize();
798 uint64_t MaxAlign = MFI->getMaxAlignment();
799 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
800 uint64_t NumBytes = 0;
803 // Calculate required stack adjustment
804 uint64_t FrameSize = StackSize - SlotSize;
805 if (needsStackRealignment(MF))
806 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
808 NumBytes = FrameSize - CSSize;
811 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
813 NumBytes = StackSize - CSSize;
815 // Skip the callee-saved pop instructions.
816 MachineBasicBlock::iterator LastCSPop = MBBI;
817 while (MBBI != MBB.begin()) {
818 MachineBasicBlock::iterator PI = prior(MBBI);
819 unsigned Opc = PI->getOpcode();
820 if (Opc != X86::POP32r && Opc != X86::POP64r &&
821 !PI->getDesc().isTerminator())
826 // If there is an ADD32ri or SUB32ri of ESP immediately before this
827 // instruction, merge the two instructions.
828 if (NumBytes || MFI->hasVarSizedObjects())
829 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
831 // If dynamic alloca is used, then reset esp to point to the last callee-saved
832 // slot before popping them off! Same applies for the case, when stack was
834 if (needsStackRealignment(MF)) {
835 // We cannot use LEA here, because stack pointer was realigned. We need to
836 // deallocate local frame back
838 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
839 MBBI = prior(LastCSPop);
843 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
844 StackPtr).addReg(FramePtr);
845 } else if (MFI->hasVarSizedObjects()) {
847 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
848 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
849 FramePtr, false, -CSSize);
850 MBB.insert(MBBI, MI);
852 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
856 // adjust stack pointer back: ESP += numbytes
858 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
861 // We're returning from function via eh_return.
862 if (RetOpcode == X86::EH_RETURN) {
863 MBBI = prior(MBB.end());
864 MachineOperand &DestAddr = MBBI->getOperand(0);
865 assert(DestAddr.isRegister() && "Offset should be in register!");
866 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
867 addReg(DestAddr.getReg());
868 // Tail call return: adjust the stack pointer and jump to callee
869 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
870 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
871 MBBI = prior(MBB.end());
872 MachineOperand &JumpTarget = MBBI->getOperand(0);
873 MachineOperand &StackAdjust = MBBI->getOperand(1);
874 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
876 // Adjust stack pointer.
877 int StackAdj = StackAdjust.getImm();
878 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
880 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
881 // Incoporate the retaddr area.
882 Offset = StackAdj-MaxTCDelta;
883 assert(Offset >= 0 && "Offset should never be negative");
885 // Check for possible merge with preceeding ADD instruction.
886 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
887 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
889 // Jump to label or value in register.
890 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
891 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
892 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
893 else if (RetOpcode== X86::TCRETURNri64) {
894 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
896 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
897 // Delete the pseudo instruction TCRETURN.
899 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
900 (X86FI->getTCReturnAddrDelta() < 0)) {
901 // Add the return addr area delta back since we are not tail calling.
902 int delta = -1*X86FI->getTCReturnAddrDelta();
903 MBBI = prior(MBB.end());
904 // Check for possible merge with preceeding ADD instruction.
905 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
906 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
910 unsigned X86RegisterInfo::getRARegister() const {
912 return X86::RIP; // Should have dwarf #16
914 return X86::EIP; // Should have dwarf #8
917 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
918 return hasFP(MF) ? FramePtr : StackPtr;
921 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
923 // Calculate amount of bytes used for return address storing
924 int stackGrowth = (Is64Bit ? -8 : -4);
926 // Initial state of the frame pointer is esp+4.
927 MachineLocation Dst(MachineLocation::VirtualFP);
928 MachineLocation Src(StackPtr, stackGrowth);
929 Moves.push_back(MachineMove(0, Dst, Src));
931 // Add return address to move list
932 MachineLocation CSDst(StackPtr, stackGrowth);
933 MachineLocation CSSrc(getRARegister());
934 Moves.push_back(MachineMove(0, CSDst, CSSrc));
937 unsigned X86RegisterInfo::getEHExceptionRegister() const {
938 assert(0 && "What is the exception register");
942 unsigned X86RegisterInfo::getEHHandlerRegister() const {
943 assert(0 && "What is the exception handler register");
948 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
949 switch (VT.getSimpleVT()) {
955 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
957 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
959 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
961 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
967 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
969 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
971 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
973 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
975 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
977 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
979 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
981 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
983 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
985 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
987 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
989 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
991 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
993 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
995 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
997 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1003 default: return Reg;
1004 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1006 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1008 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1010 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1012 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1014 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1016 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1018 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1020 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1022 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1024 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1026 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1028 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1030 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1032 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1034 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1039 default: return Reg;
1040 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1042 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1044 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1046 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1048 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1050 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1052 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1054 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1056 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1058 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1060 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1062 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1064 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1066 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1068 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1070 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1075 default: return Reg;
1076 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1078 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1080 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1082 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1084 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1086 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1088 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1090 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1092 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1094 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1096 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1098 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1100 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1102 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1104 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1106 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1115 #include "X86GenRegisterInfo.inc"
1118 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1120 MSAC() : MachineFunctionPass((intptr_t)&ID) {}
1122 virtual bool runOnMachineFunction(MachineFunction &MF) {
1123 MachineFrameInfo *FFI = MF.getFrameInfo();
1124 MachineRegisterInfo &RI = MF.getRegInfo();
1126 // Calculate max stack alignment of all already allocated stack objects.
1127 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1129 // Be over-conservative: scan over all vreg defs and find, whether vector
1130 // registers are used. If yes - there is probability, that vector register
1131 // will be spilled and thus stack needs to be aligned properly.
1132 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1133 RegNum < RI.getLastVirtReg(); ++RegNum)
1134 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1136 FFI->setMaxAlignment(MaxAlign);
1141 virtual const char *getPassName() const {
1142 return "X86 Maximal Stack Alignment Calculator";
1150 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }