1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/ErrorHandling.h"
46 StrictIndexRegclass("strict-index-regclass",
47 cl::desc("Use a special register class to avoid letting SP "
48 "be used as an index"));
50 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
51 const TargetInstrInfo &tii)
52 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
53 X86::ADJCALLSTACKDOWN64 :
54 X86::ADJCALLSTACKDOWN32,
55 tm.getSubtarget<X86Subtarget>().is64Bit() ?
56 X86::ADJCALLSTACKUP64 :
57 X86::ADJCALLSTACKUP32),
59 // Cache some information.
60 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
61 Is64Bit = Subtarget->is64Bit();
62 IsWin64 = Subtarget->isTargetWin64();
63 StackAlign = TM.getFrameInfo()->getStackAlignment();
75 // getDwarfRegNum - This function maps LLVM register identifiers to the
76 // Dwarf specific numbering, used in debug info and exception tables.
78 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
79 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
80 unsigned Flavour = DWARFFlavour::X86_64;
81 if (!Subtarget->is64Bit()) {
82 if (Subtarget->isTargetDarwin()) {
84 Flavour = DWARFFlavour::X86_32_DarwinEH;
86 Flavour = DWARFFlavour::X86_32_Generic;
87 } else if (Subtarget->isTargetCygMing()) {
88 // Unsupported by now, just quick fallback
89 Flavour = DWARFFlavour::X86_32_Generic;
91 Flavour = DWARFFlavour::X86_32_Generic;
95 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
98 // getX86RegNum - This function maps LLVM register identifiers to their X86
99 // specific numbering, which is used in various places encoding instructions.
101 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
103 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
104 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
105 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
106 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
107 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
109 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
111 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
113 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
116 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
118 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
120 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
122 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
124 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
126 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
128 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
130 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
133 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
134 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
135 return RegNo-X86::ST0;
137 case X86::XMM0: case X86::XMM8: case X86::MM0:
139 case X86::XMM1: case X86::XMM9: case X86::MM1:
141 case X86::XMM2: case X86::XMM10: case X86::MM2:
143 case X86::XMM3: case X86::XMM11: case X86::MM3:
145 case X86::XMM4: case X86::XMM12: case X86::MM4:
147 case X86::XMM5: case X86::XMM13: case X86::MM5:
149 case X86::XMM6: case X86::XMM14: case X86::MM6:
151 case X86::XMM7: case X86::XMM15: case X86::MM7:
155 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
156 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
161 const TargetRegisterClass *
162 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
163 const TargetRegisterClass *B,
164 unsigned SubIdx) const {
169 if (B == &X86::GR8RegClass) {
170 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
172 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
173 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
174 A == &X86::GR64_NOREXRegClass ||
175 A == &X86::GR64_NOSPRegClass ||
176 A == &X86::GR64_NOREX_NOSPRegClass)
177 return &X86::GR64_ABCDRegClass;
178 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
179 A == &X86::GR32_NOREXRegClass ||
180 A == &X86::GR32_NOSPRegClass)
181 return &X86::GR32_ABCDRegClass;
182 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
183 A == &X86::GR16_NOREXRegClass)
184 return &X86::GR16_ABCDRegClass;
185 } else if (B == &X86::GR8_NOREXRegClass) {
186 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
187 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
188 return &X86::GR64_NOREXRegClass;
189 else if (A == &X86::GR64_ABCDRegClass)
190 return &X86::GR64_ABCDRegClass;
191 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
192 A == &X86::GR32_NOSPRegClass)
193 return &X86::GR32_NOREXRegClass;
194 else if (A == &X86::GR32_ABCDRegClass)
195 return &X86::GR32_ABCDRegClass;
196 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
197 return &X86::GR16_NOREXRegClass;
198 else if (A == &X86::GR16_ABCDRegClass)
199 return &X86::GR16_ABCDRegClass;
204 if (B == &X86::GR8_ABCD_HRegClass) {
205 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
206 A == &X86::GR64_NOREXRegClass ||
207 A == &X86::GR64_NOSPRegClass ||
208 A == &X86::GR64_NOREX_NOSPRegClass)
209 return &X86::GR64_ABCDRegClass;
210 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
211 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
212 return &X86::GR32_ABCDRegClass;
213 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
214 A == &X86::GR16_NOREXRegClass)
215 return &X86::GR16_ABCDRegClass;
220 if (B == &X86::GR16RegClass) {
221 if (A->getSize() == 4 || A->getSize() == 8)
223 } else if (B == &X86::GR16_ABCDRegClass) {
224 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
225 A == &X86::GR64_NOREXRegClass ||
226 A == &X86::GR64_NOSPRegClass ||
227 A == &X86::GR64_NOREX_NOSPRegClass)
228 return &X86::GR64_ABCDRegClass;
229 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
230 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
231 return &X86::GR32_ABCDRegClass;
232 } else if (B == &X86::GR16_NOREXRegClass) {
233 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
234 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
235 return &X86::GR64_NOREXRegClass;
236 else if (A == &X86::GR64_ABCDRegClass)
237 return &X86::GR64_ABCDRegClass;
238 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
239 A == &X86::GR32_NOSPRegClass)
240 return &X86::GR32_NOREXRegClass;
241 else if (A == &X86::GR32_ABCDRegClass)
242 return &X86::GR64_ABCDRegClass;
247 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
248 if (A->getSize() == 8)
250 } else if (B == &X86::GR32_ABCDRegClass) {
251 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
252 A == &X86::GR64_NOREXRegClass ||
253 A == &X86::GR64_NOSPRegClass ||
254 A == &X86::GR64_NOREX_NOSPRegClass)
255 return &X86::GR64_ABCDRegClass;
256 } else if (B == &X86::GR32_NOREXRegClass) {
257 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
258 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
259 return &X86::GR64_NOREXRegClass;
260 else if (A == &X86::GR64_ABCDRegClass)
261 return &X86::GR64_ABCDRegClass;
268 const TargetRegisterClass *X86RegisterInfo::
269 getPointerRegClass(unsigned Kind) const {
271 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
272 case 0: // Normal GPRs.
273 if (TM.getSubtarget<X86Subtarget>().is64Bit())
274 return &X86::GR64RegClass;
275 return &X86::GR32RegClass;
276 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
277 if (!StrictIndexRegclass) {
278 if (TM.getSubtarget<X86Subtarget>().is64Bit())
279 return &X86::GR64RegClass;
280 return &X86::GR32RegClass;
282 if (TM.getSubtarget<X86Subtarget>().is64Bit())
283 return &X86::GR64_NOSPRegClass;
284 return &X86::GR32_NOSPRegClass;
289 const TargetRegisterClass *
290 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
291 if (RC == &X86::CCRRegClass) {
293 return &X86::GR64RegClass;
295 return &X86::GR32RegClass;
301 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
302 bool callsEHReturn = false;
305 const MachineFrameInfo *MFI = MF->getFrameInfo();
306 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
307 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
310 static const unsigned CalleeSavedRegs32Bit[] = {
311 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
314 static const unsigned CalleeSavedRegs32EHRet[] = {
315 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
318 static const unsigned CalleeSavedRegs64Bit[] = {
319 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
322 static const unsigned CalleeSavedRegs64EHRet[] = {
323 X86::RAX, X86::RDX, X86::RBX, X86::R12,
324 X86::R13, X86::R14, X86::R15, X86::RBP, 0
327 static const unsigned CalleeSavedRegsWin64[] = {
328 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
329 X86::R12, X86::R13, X86::R14, X86::R15,
330 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
331 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
332 X86::XMM14, X86::XMM15, 0
337 return CalleeSavedRegsWin64;
339 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
341 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
345 const TargetRegisterClass* const*
346 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
347 bool callsEHReturn = false;
350 const MachineFrameInfo *MFI = MF->getFrameInfo();
351 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
352 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
355 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
356 &X86::GR32RegClass, &X86::GR32RegClass,
357 &X86::GR32RegClass, &X86::GR32RegClass, 0
359 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
360 &X86::GR32RegClass, &X86::GR32RegClass,
361 &X86::GR32RegClass, &X86::GR32RegClass,
362 &X86::GR32RegClass, &X86::GR32RegClass, 0
364 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
365 &X86::GR64RegClass, &X86::GR64RegClass,
366 &X86::GR64RegClass, &X86::GR64RegClass,
367 &X86::GR64RegClass, &X86::GR64RegClass, 0
369 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
370 &X86::GR64RegClass, &X86::GR64RegClass,
371 &X86::GR64RegClass, &X86::GR64RegClass,
372 &X86::GR64RegClass, &X86::GR64RegClass,
373 &X86::GR64RegClass, &X86::GR64RegClass, 0
375 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
376 &X86::GR64RegClass, &X86::GR64RegClass,
377 &X86::GR64RegClass, &X86::GR64RegClass,
378 &X86::GR64RegClass, &X86::GR64RegClass,
379 &X86::GR64RegClass, &X86::GR64RegClass,
380 &X86::VR128RegClass, &X86::VR128RegClass,
381 &X86::VR128RegClass, &X86::VR128RegClass,
382 &X86::VR128RegClass, &X86::VR128RegClass,
383 &X86::VR128RegClass, &X86::VR128RegClass,
384 &X86::VR128RegClass, &X86::VR128RegClass, 0
389 return CalleeSavedRegClassesWin64;
391 return (callsEHReturn ?
392 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
394 return (callsEHReturn ?
395 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
399 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
400 BitVector Reserved(getNumRegs());
401 // Set the stack-pointer register and its aliases as reserved.
402 Reserved.set(X86::RSP);
403 Reserved.set(X86::ESP);
404 Reserved.set(X86::SP);
405 Reserved.set(X86::SPL);
406 // Set the frame-pointer register and its aliases as reserved if needed.
408 Reserved.set(X86::RBP);
409 Reserved.set(X86::EBP);
410 Reserved.set(X86::BP);
411 Reserved.set(X86::BPL);
413 // Mark the x87 stack registers as reserved, since they don't
414 // behave normally with respect to liveness. We don't fully
415 // model the effects of x87 stack pushes and pops after
417 Reserved.set(X86::ST0);
418 Reserved.set(X86::ST1);
419 Reserved.set(X86::ST2);
420 Reserved.set(X86::ST3);
421 Reserved.set(X86::ST4);
422 Reserved.set(X86::ST5);
423 Reserved.set(X86::ST6);
424 Reserved.set(X86::ST7);
428 //===----------------------------------------------------------------------===//
429 // Stack Frame Processing methods
430 //===----------------------------------------------------------------------===//
432 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
433 unsigned MaxAlign = 0;
434 for (int i = FFI->getObjectIndexBegin(),
435 e = FFI->getObjectIndexEnd(); i != e; ++i) {
436 if (FFI->isDeadObjectIndex(i))
438 unsigned Align = FFI->getObjectAlignment(i);
439 MaxAlign = std::max(MaxAlign, Align);
445 // hasFP - Return true if the specified function should have a dedicated frame
446 // pointer register. This is true if the function has variable sized allocas or
447 // if frame pointer elimination is disabled.
449 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
450 const MachineFrameInfo *MFI = MF.getFrameInfo();
451 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
453 return (NoFramePointerElim ||
454 needsStackRealignment(MF) ||
455 MFI->hasVarSizedObjects() ||
456 MFI->isFrameAddressTaken() ||
457 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
458 (MMI && MMI->callsUnwindInit()));
461 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
462 const MachineFrameInfo *MFI = MF.getFrameInfo();
464 // FIXME: Currently we don't support stack realignment for functions with
465 // variable-sized allocas
466 return (RealignStack &&
467 (MFI->getMaxAlignment() > StackAlign &&
468 !MFI->hasVarSizedObjects()));
471 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
472 return !MF.getFrameInfo()->hasVarSizedObjects();
475 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
476 int &FrameIdx) const {
477 if (Reg == FramePtr && hasFP(MF)) {
478 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
486 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
487 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
488 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
490 if (needsStackRealignment(MF)) {
492 // Skip the saved EBP
495 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
496 assert( (-(Offset + StackSize)) % Align == 0);
498 return Offset + StackSize;
501 // FIXME: Support tail calls
504 return Offset + StackSize;
506 // Skip the saved EBP
509 // Skip the RETADDR move area
510 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
511 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
512 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
518 void X86RegisterInfo::
519 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
520 MachineBasicBlock::iterator I) const {
521 if (!hasReservedCallFrame(MF)) {
522 // If the stack pointer can be changed after prologue, turn the
523 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
524 // adjcallstackdown instruction into 'add ESP, <amt>'
525 // TODO: consider using push / pop instead of sub + store / add
526 MachineInstr *Old = I;
527 uint64_t Amount = Old->getOperand(0).getImm();
529 // We need to keep the stack aligned properly. To do this, we round the
530 // amount of space needed for the outgoing arguments up to the next
531 // alignment boundary.
532 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
534 MachineInstr *New = 0;
535 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
536 New = BuildMI(MF, Old->getDebugLoc(),
537 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
538 StackPtr).addReg(StackPtr).addImm(Amount);
540 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
541 // factor out the amount the callee already popped.
542 uint64_t CalleeAmt = Old->getOperand(1).getImm();
545 unsigned Opc = (Amount < 128) ?
546 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
547 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
548 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
549 .addReg(StackPtr).addImm(Amount);
554 // The EFLAGS implicit def is dead.
555 New->getOperand(3).setIsDead();
557 // Replace the pseudo instruction with a new instruction...
561 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
562 // If we are performing frame pointer elimination and if the callee pops
563 // something off the stack pointer, add it back. We do this until we have
564 // more advanced stack pointer tracking ability.
565 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
566 unsigned Opc = (CalleeAmt < 128) ?
567 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
568 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
569 MachineInstr *Old = I;
571 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
572 StackPtr).addReg(StackPtr).addImm(CalleeAmt);
573 // The EFLAGS implicit def is dead.
574 New->getOperand(3).setIsDead();
583 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
584 int SPAdj, RegScavenger *RS) const{
585 assert(SPAdj == 0 && "Unexpected");
588 MachineInstr &MI = *II;
589 MachineFunction &MF = *MI.getParent()->getParent();
590 while (!MI.getOperand(i).isFI()) {
592 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
595 int FrameIndex = MI.getOperand(i).getIndex();
598 if (needsStackRealignment(MF))
599 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
601 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
603 // This must be part of a four operand memory reference. Replace the
604 // FrameIndex with base register with EBP. Add an offset to the offset.
605 MI.getOperand(i).ChangeToRegister(BasePtr, false);
607 // Now add the frame object offset to the offset from EBP.
608 if (MI.getOperand(i+3).isImm()) {
609 // Offset is a 32-bit integer.
610 int Offset = getFrameIndexOffset(MF, FrameIndex) +
611 (int)(MI.getOperand(i+3).getImm());
613 MI.getOperand(i+3).ChangeToImmediate(Offset);
615 // Offset is symbolic. This is extremely rare.
616 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
617 (uint64_t)MI.getOperand(i+3).getOffset();
618 MI.getOperand(i+3).setOffset(Offset);
623 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
624 RegScavenger *RS) const {
625 MachineFrameInfo *FFI = MF.getFrameInfo();
627 // Calculate and set max stack object alignment early, so we can decide
628 // whether we will need stack realignment (and thus FP).
629 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
630 calculateMaxStackAlignment(FFI));
632 FFI->setMaxAlignment(MaxAlign);
634 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
635 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
636 if (TailCallReturnAddrDelta < 0) {
637 // create RETURNADDR area
647 CreateFixedObject(-TailCallReturnAddrDelta,
648 (-1*SlotSize)+TailCallReturnAddrDelta);
651 assert((TailCallReturnAddrDelta <= 0) &&
652 "The Delta should always be zero or negative");
653 // Create a frame entry for the EBP register that must be saved.
654 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
656 TailCallReturnAddrDelta);
657 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
658 "Slot for EBP register must be last in order to be found!");
663 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
664 /// stack pointer by a constant value.
666 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
667 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
668 const TargetInstrInfo &TII) {
669 bool isSub = NumBytes < 0;
670 uint64_t Offset = isSub ? -NumBytes : NumBytes;
673 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
674 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
676 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
677 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
678 uint64_t Chunk = (1LL << 31) - 1;
679 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
680 DebugLoc::getUnknownLoc());
683 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
685 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
686 .addReg(StackPtr).addImm(ThisVal);
687 // The EFLAGS implicit def is dead.
688 MI->getOperand(3).setIsDead();
693 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
695 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
696 unsigned StackPtr, uint64_t *NumBytes = NULL) {
697 if (MBBI == MBB.begin()) return;
699 MachineBasicBlock::iterator PI = prior(MBBI);
700 unsigned Opc = PI->getOpcode();
701 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
702 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
703 PI->getOperand(0).getReg() == StackPtr) {
705 *NumBytes += PI->getOperand(2).getImm();
707 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
708 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
709 PI->getOperand(0).getReg() == StackPtr) {
711 *NumBytes -= PI->getOperand(2).getImm();
716 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
718 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
719 MachineBasicBlock::iterator &MBBI,
720 unsigned StackPtr, uint64_t *NumBytes = NULL) {
723 if (MBBI == MBB.end()) return;
725 MachineBasicBlock::iterator NI = next(MBBI);
726 if (NI == MBB.end()) return;
728 unsigned Opc = NI->getOpcode();
729 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
730 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
731 NI->getOperand(0).getReg() == StackPtr) {
733 *NumBytes -= NI->getOperand(2).getImm();
736 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
737 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
738 NI->getOperand(0).getReg() == StackPtr) {
740 *NumBytes += NI->getOperand(2).getImm();
746 /// mergeSPUpdates - Checks the instruction before/after the passed
747 /// instruction. If it is an ADD/SUB instruction it is deleted
748 /// argument and the stack adjustment is returned as a positive value for ADD
749 /// and a negative for SUB.
750 static int mergeSPUpdates(MachineBasicBlock &MBB,
751 MachineBasicBlock::iterator &MBBI,
753 bool doMergeWithPrevious) {
755 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
756 (!doMergeWithPrevious && MBBI == MBB.end()))
761 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
762 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
763 unsigned Opc = PI->getOpcode();
764 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
765 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
766 PI->getOperand(0).getReg() == StackPtr){
767 Offset += PI->getOperand(2).getImm();
769 if (!doMergeWithPrevious) MBBI = NI;
770 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
771 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
772 PI->getOperand(0).getReg() == StackPtr) {
773 Offset -= PI->getOperand(2).getImm();
775 if (!doMergeWithPrevious) MBBI = NI;
781 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
783 unsigned FramePtr) const {
784 MachineFrameInfo *MFI = MF.getFrameInfo();
785 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
788 // Add callee saved registers to move list.
789 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
790 if (CSI.empty()) return;
792 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
793 const TargetData *TD = MF.getTarget().getTargetData();
794 bool HasFP = hasFP(MF);
796 // Calculate amount of bytes used for return address storing
798 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
799 TargetFrameInfo::StackGrowsUp ?
800 TD->getPointerSize() : -TD->getPointerSize());
802 // FIXME: This is dirty hack. The code itself is pretty mess right now.
803 // It should be rewritten from scratch and generalized sometimes.
805 // Determine maximum offset (minumum due to stack growth)
806 int64_t MaxOffset = 0;
807 for (std::vector<CalleeSavedInfo>::const_iterator
808 I = CSI.begin(), E = CSI.end(); I != E; ++I)
809 MaxOffset = std::min(MaxOffset,
810 MFI->getObjectOffset(I->getFrameIdx()));
812 // Calculate offsets.
813 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
814 for (std::vector<CalleeSavedInfo>::const_iterator
815 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
816 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
817 unsigned Reg = I->getReg();
818 Offset = MaxOffset - Offset + saveAreaOffset;
820 // Don't output a new machine move if we're re-saving the frame
821 // pointer. This happens when the PrologEpilogInserter has inserted an extra
822 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
823 // generates one when frame pointers are used. If we generate a "machine
824 // move" for this extra "PUSH", the linker will lose track of the fact that
825 // the frame pointer should have the value of the first "PUSH" when it's
828 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
829 // another bug. I.e., one where we generate a prolog like this:
837 // The immediate re-push of EBP is unnecessary. At the least, it's an
838 // optimization bug. EBP can be used as a scratch register in certain
839 // cases, but probably not when we have a frame pointer.
840 if (HasFP && FramePtr == Reg)
843 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
844 MachineLocation CSSrc(Reg);
845 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
849 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
850 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
851 MachineFrameInfo *MFI = MF.getFrameInfo();
852 const Function* Fn = MF.getFunction();
853 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
854 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
855 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
856 MachineBasicBlock::iterator MBBI = MBB.begin();
857 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
858 !Fn->doesNotThrow() ||
859 UnwindTablesMandatory;
860 bool HasFP = hasFP(MF);
863 // Get the number of bytes to allocate from the FrameInfo.
864 uint64_t StackSize = MFI->getStackSize();
866 // Get desired stack alignment
867 uint64_t MaxAlign = MFI->getMaxAlignment();
869 // Add RETADDR move area to callee saved frame size.
870 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
871 if (TailCallReturnAddrDelta < 0)
872 X86FI->setCalleeSavedFrameSize(
873 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
875 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
876 // function, and use up to 128 bytes of stack space, don't have a frame
877 // pointer, calls, or dynamic alloca then we do not need to adjust the
878 // stack pointer (we fit in the Red Zone).
879 bool DisableRedZone = Fn->hasFnAttr(Attribute::NoRedZone);
880 if (Is64Bit && !DisableRedZone &&
881 !needsStackRealignment(MF) &&
882 !MFI->hasVarSizedObjects() && // No dynamic alloca.
883 !MFI->hasCalls() && // No calls.
884 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
885 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
886 if (HasFP) MinSize += SlotSize;
887 StackSize = std::max(MinSize,
888 StackSize > 128 ? StackSize - 128 : 0);
889 MFI->setStackSize(StackSize);
892 // Insert stack pointer adjustment for later moving of return addr. Only
893 // applies to tail call optimized functions where the callee argument stack
894 // size is bigger than the callers.
895 if (TailCallReturnAddrDelta < 0) {
897 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
898 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
899 // The EFLAGS implicit def is dead.
900 MI->getOperand(3).setIsDead();
903 // uint64_t StackSize = MFI->getStackSize();
904 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
905 const TargetData *TD = MF.getTarget().getTargetData();
907 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
908 TargetFrameInfo::StackGrowsUp ?
909 TD->getPointerSize() : -TD->getPointerSize());
911 uint64_t NumBytes = 0;
913 // Calculate required stack adjustment
914 uint64_t FrameSize = StackSize - SlotSize;
915 if (needsStackRealignment(MF))
916 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
918 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
920 // Get the offset of the stack slot for the EBP register, which is
921 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
922 // Update the frame offset adjustment.
923 MFI->setOffsetAdjustment(-NumBytes);
925 // Save EBP/RBP into the appropriate stack slot...
926 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
927 .addReg(FramePtr, RegState::Kill);
929 if (needsFrameMoves) {
930 // Mark effective beginning of when frame pointer becomes valid.
931 unsigned FrameLabelId = MMI->NextLabelID();
932 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
934 // Define the current CFA rule to use the provided offset.
936 MachineLocation SPDst(MachineLocation::VirtualFP);
937 MachineLocation SPSrc(MachineLocation::VirtualFP,
938 HasFP ? 2 * stackGrowth :
939 -StackSize + stackGrowth);
940 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
942 // FIXME: Verify & implement for FP
943 MachineLocation SPDst(StackPtr);
944 MachineLocation SPSrc(StackPtr, stackGrowth);
945 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
948 // Change the rule for the FramePtr to be an "offset" rule.
949 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
950 MachineLocation FPSrc(FramePtr);
951 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
954 // Update EBP with the new base value...
955 BuildMI(MBB, MBBI, DL,
956 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
959 if (needsFrameMoves) {
960 unsigned FrameLabelId = MMI->NextLabelID();
961 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
963 // Define the current CFA to use the EBP/RBP register.
964 MachineLocation FPDst(FramePtr);
965 MachineLocation FPSrc(MachineLocation::VirtualFP);
966 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
969 // Mark the FramePtr as live-in in every block except the entry.
970 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
972 I->addLiveIn(FramePtr);
975 if (needsStackRealignment(MF)) {
977 BuildMI(MBB, MBBI, DL,
978 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
979 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
981 // The EFLAGS implicit def is dead.
982 MI->getOperand(3).setIsDead();
985 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
988 // Skip the callee-saved push instructions.
989 bool RegsSaved = false;
990 while (MBBI != MBB.end() &&
991 (MBBI->getOpcode() == X86::PUSH32r ||
992 MBBI->getOpcode() == X86::PUSH64r)) {
997 if (RegsSaved && needsFrameMoves) {
998 // Mark end of callee-saved push instructions.
999 unsigned LabelId = MMI->NextLabelID();
1000 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1002 // Emit DWARF info specifying the offsets of the callee-saved registers.
1003 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1006 if (MBBI != MBB.end())
1007 DL = MBBI->getDebugLoc();
1009 // Adjust stack pointer: ESP -= numbytes.
1010 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1011 // Check, whether EAX is livein for this function.
1012 bool isEAXAlive = false;
1013 for (MachineRegisterInfo::livein_iterator
1014 II = MF.getRegInfo().livein_begin(),
1015 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1016 unsigned Reg = II->first;
1017 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1018 Reg == X86::AH || Reg == X86::AL);
1021 // Function prologue calls _alloca to probe the stack when allocating more
1022 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1023 // to ensure that the guard pages used by the OS virtual memory manager are
1024 // allocated in correct sequence.
1026 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1028 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1029 .addExternalSymbol("_alloca");
1032 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1033 .addReg(X86::EAX, RegState::Kill);
1035 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1036 // allocated bytes for EAX.
1037 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1038 .addImm(NumBytes - 4);
1039 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1040 .addExternalSymbol("_alloca");
1043 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1045 StackPtr, false, NumBytes - 4);
1046 MBB.insert(MBBI, MI);
1048 } else if (NumBytes) {
1049 // If there is an SUB32ri of ESP immediately before this instruction, merge
1050 // the two. This can be the case when tail call elimination is enabled and
1051 // the callee has more arguments then the caller.
1052 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1054 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1055 // instruction, merge the two instructions.
1056 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1059 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1062 if (!HasFP && needsFrameMoves && NumBytes) {
1063 // Mark end of stack pointer adjustment.
1064 unsigned LabelId = MMI->NextLabelID();
1065 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1067 // Define the current CFA rule to use the provided offset.
1069 MachineLocation SPDst(MachineLocation::VirtualFP);
1070 MachineLocation SPSrc(MachineLocation::VirtualFP,
1071 -StackSize + stackGrowth);
1072 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1074 // FIXME: Verify & implement for FP
1075 MachineLocation SPDst(StackPtr);
1076 MachineLocation SPSrc(StackPtr, stackGrowth);
1077 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1082 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1083 MachineBasicBlock &MBB) const {
1084 const MachineFrameInfo *MFI = MF.getFrameInfo();
1085 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1086 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1087 unsigned RetOpcode = MBBI->getOpcode();
1088 DebugLoc DL = MBBI->getDebugLoc();
1090 switch (RetOpcode) {
1093 case X86::TCRETURNdi:
1094 case X86::TCRETURNri:
1095 case X86::TCRETURNri64:
1096 case X86::TCRETURNdi64:
1097 case X86::EH_RETURN:
1098 case X86::EH_RETURN64:
1101 case X86::TAILJMPm: break; // These are ok
1103 llvm_unreachable("Can only insert epilog into returning blocks");
1106 // Get the number of bytes to allocate from the FrameInfo
1107 uint64_t StackSize = MFI->getStackSize();
1108 uint64_t MaxAlign = MFI->getMaxAlignment();
1109 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1110 uint64_t NumBytes = 0;
1113 // Calculate required stack adjustment
1114 uint64_t FrameSize = StackSize - SlotSize;
1115 if (needsStackRealignment(MF))
1116 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1118 NumBytes = FrameSize - CSSize;
1121 BuildMI(MBB, MBBI, DL,
1122 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1124 NumBytes = StackSize - CSSize;
1127 // Skip the callee-saved pop instructions.
1128 MachineBasicBlock::iterator LastCSPop = MBBI;
1129 while (MBBI != MBB.begin()) {
1130 MachineBasicBlock::iterator PI = prior(MBBI);
1131 unsigned Opc = PI->getOpcode();
1132 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1133 !PI->getDesc().isTerminator())
1138 DL = MBBI->getDebugLoc();
1140 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1141 // instruction, merge the two instructions.
1142 if (NumBytes || MFI->hasVarSizedObjects())
1143 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1145 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1146 // slot before popping them off! Same applies for the case, when stack was
1148 if (needsStackRealignment(MF)) {
1149 // We cannot use LEA here, because stack pointer was realigned. We need to
1150 // deallocate local frame back
1152 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1153 MBBI = prior(LastCSPop);
1156 BuildMI(MBB, MBBI, DL,
1157 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1158 StackPtr).addReg(FramePtr);
1159 } else if (MFI->hasVarSizedObjects()) {
1161 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1162 MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1163 FramePtr, false, -CSSize);
1164 MBB.insert(MBBI, MI);
1166 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1167 StackPtr).addReg(FramePtr);
1170 // adjust stack pointer back: ESP += numbytes
1172 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1175 // We're returning from function via eh_return.
1176 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1177 MBBI = prior(MBB.end());
1178 MachineOperand &DestAddr = MBBI->getOperand(0);
1179 assert(DestAddr.isReg() && "Offset should be in register!");
1180 BuildMI(MBB, MBBI, DL,
1181 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1182 StackPtr).addReg(DestAddr.getReg());
1183 // Tail call return: adjust the stack pointer and jump to callee
1184 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1185 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1186 MBBI = prior(MBB.end());
1187 MachineOperand &JumpTarget = MBBI->getOperand(0);
1188 MachineOperand &StackAdjust = MBBI->getOperand(1);
1189 assert(StackAdjust.isImm() && "Expecting immediate value.");
1191 // Adjust stack pointer.
1192 int StackAdj = StackAdjust.getImm();
1193 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1195 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1196 // Incoporate the retaddr area.
1197 Offset = StackAdj-MaxTCDelta;
1198 assert(Offset >= 0 && "Offset should never be negative");
1201 // Check for possible merge with preceeding ADD instruction.
1202 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1203 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1206 // Jump to label or value in register.
1207 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1208 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1209 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1210 else if (RetOpcode== X86::TCRETURNri64)
1211 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1213 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1215 // Delete the pseudo instruction TCRETURN.
1217 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1218 (X86FI->getTCReturnAddrDelta() < 0)) {
1219 // Add the return addr area delta back since we are not tail calling.
1220 int delta = -1*X86FI->getTCReturnAddrDelta();
1221 MBBI = prior(MBB.end());
1222 // Check for possible merge with preceeding ADD instruction.
1223 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1224 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1228 unsigned X86RegisterInfo::getRARegister() const {
1230 return X86::RIP; // Should have dwarf #16
1232 return X86::EIP; // Should have dwarf #8
1235 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1236 return hasFP(MF) ? FramePtr : StackPtr;
1239 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1241 // Calculate amount of bytes used for return address storing
1242 int stackGrowth = (Is64Bit ? -8 : -4);
1244 // Initial state of the frame pointer is esp+4.
1245 MachineLocation Dst(MachineLocation::VirtualFP);
1246 MachineLocation Src(StackPtr, stackGrowth);
1247 Moves.push_back(MachineMove(0, Dst, Src));
1249 // Add return address to move list
1250 MachineLocation CSDst(StackPtr, stackGrowth);
1251 MachineLocation CSSrc(getRARegister());
1252 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1255 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1256 llvm_unreachable("What is the exception register");
1260 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1261 llvm_unreachable("What is the exception handler register");
1266 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1267 switch (VT.getSimpleVT()) {
1268 default: return Reg;
1273 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1275 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1277 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1279 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1285 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1287 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1289 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1291 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1293 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1295 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1297 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1299 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1301 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1303 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1305 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1307 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1309 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1311 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1313 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1315 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1321 default: return Reg;
1322 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1324 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1326 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1328 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1330 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1332 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1334 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1336 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1338 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1340 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1342 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1344 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1346 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1348 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1350 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1352 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1357 default: return Reg;
1358 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1360 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1362 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1364 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1366 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1368 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1370 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1372 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1374 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1376 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1378 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1380 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1382 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1384 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1386 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1388 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1393 default: return Reg;
1394 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1396 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1398 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1400 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1402 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1404 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1406 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1408 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1410 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1412 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1414 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1416 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1418 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1420 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1422 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1424 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1433 #include "X86GenRegisterInfo.inc"
1436 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1438 MSAC() : MachineFunctionPass(&ID) {}
1440 virtual bool runOnMachineFunction(MachineFunction &MF) {
1441 MachineFrameInfo *FFI = MF.getFrameInfo();
1442 MachineRegisterInfo &RI = MF.getRegInfo();
1444 // Calculate max stack alignment of all already allocated stack objects.
1445 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1447 // Be over-conservative: scan over all vreg defs and find, whether vector
1448 // registers are used. If yes - there is probability, that vector register
1449 // will be spilled and thus stack needs to be aligned properly.
1450 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1451 RegNum < RI.getLastVirtReg(); ++RegNum)
1452 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1454 if (FFI->getMaxAlignment() == MaxAlign)
1457 FFI->setMaxAlignment(MaxAlign);
1461 virtual const char *getPassName() const {
1462 return "X86 Maximal Stack Alignment Calculator";
1465 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1466 AU.setPreservesCFG();
1467 MachineFunctionPass::getAnalysisUsage(AU);
1475 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }